2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the SH2A port.
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77 *----------------------------------------------------------*/
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79 /* Standard C includes. */
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82 /* Scheduler includes. */
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83 #include "FreeRTOS.h"
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86 /* Library includes. */
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89 /* Hardware specifics. */
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90 #include "iorx111.h"
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92 /*-----------------------------------------------------------*/
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94 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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95 PSW is set with U and I set, and PM and IPL clear. */
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96 #define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )
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98 /* The peripheral clock is divided by this value before being supplying the
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100 #if ( configUSE_TICKLESS_IDLE == 0 )
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101 /* If tickless idle is not used then the divisor can be fixed. */
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102 #define portCLOCK_DIVISOR 8UL
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103 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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104 #define portCLOCK_DIVISOR 512UL
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105 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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106 #define portCLOCK_DIVISOR 128UL
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107 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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108 #define portCLOCK_DIVISOR 32UL
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110 #define portCLOCK_DIVISOR 8UL
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114 /* Keys required to lock and unlock access to certain system registers
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116 #define portUNLOCK_KEY 0xA50B
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117 #define portLOCK_KEY 0xA500
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119 /*-----------------------------------------------------------*/
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122 * Function to start the first task executing - written in asm code as direct
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123 * access to registers is required.
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125 extern void prvStartFirstTask( void );
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128 * The tick ISR handler. The peripheral used is configured by the application
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129 * via a hook/callback function.
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131 __interrupt static void prvTickISR( void );
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134 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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135 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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136 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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137 * in place of prvSetupTimerInterrupt().
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139 static void prvSetupTimerInterrupt( void );
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140 #ifndef configSETUP_TICK_INTERRUPT
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141 /* The user has not provided their own tick interrupt configuration so use
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142 the definition in this file (which uses the interval timer). */
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143 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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144 #endif /* configSETUP_TICK_INTERRUPT */
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147 * Called after the sleep mode registers have been configured, prvSleep()
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148 * executes the pre and post sleep macros, and actually calls the wait
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151 #if configUSE_TICKLESS_IDLE == 1
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152 static void prvSleep( portTickType xExpectedIdleTime );
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153 #endif /* configUSE_TICKLESS_IDLE */
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155 /*-----------------------------------------------------------*/
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157 extern void *pxCurrentTCB;
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159 /*-----------------------------------------------------------*/
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161 /* Calculate how many clock increments make up a single tick period. */
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162 static const unsigned long ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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164 #if configUSE_TICKLESS_IDLE == 1
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166 /* Holds the maximum number of ticks that can be suppressed - which is
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167 basically how far into the future an interrupt can be generated. Set
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168 during initialisation. This is the maximum possible value that the
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169 compare match register can hold divided by ulMatchValueForOneTick. */
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170 static const portTickType xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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172 /* Flag set from the tick interrupt to allow the sleep processing to know if
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173 sleep mode was exited because of a tick interrupt, or an interrupt
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174 generated by something else. */
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175 static volatile uint32_t ulTickFlag = pdFALSE;
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177 /* The CMT counter is stopped temporarily each time it is re-programmed.
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178 The following constant offsets the CMT counter match value by the number of
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179 CMT counts that would typically be missed while the counter was stopped to
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180 compensate for the lost time. The large difference between the divided CMT
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181 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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182 equal zero - and be optimised away. */
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183 static const unsigned long ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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187 /*-----------------------------------------------------------*/
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190 * See header file for description.
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192 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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194 /* Offset to end up on 8 byte boundary. */
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197 /* R0 is not included as it is the stack pointer. */
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198 *pxTopOfStack = 0x00;
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200 *pxTopOfStack = 0x00;
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202 *pxTopOfStack = portINITIAL_PSW;
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204 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
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206 /* When debugging it can be useful if every register is set to a known
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207 value. Otherwise code space can be saved by just setting the registers
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208 that need to be set. */
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209 #ifdef USE_FULL_REGISTER_INITIALISATION
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212 *pxTopOfStack = 0x12345678; /* r15. */
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214 *pxTopOfStack = 0xaaaabbbb;
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216 *pxTopOfStack = 0xdddddddd;
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218 *pxTopOfStack = 0xcccccccc;
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220 *pxTopOfStack = 0xbbbbbbbb;
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222 *pxTopOfStack = 0xaaaaaaaa;
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224 *pxTopOfStack = 0x99999999;
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226 *pxTopOfStack = 0x88888888;
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228 *pxTopOfStack = 0x77777777;
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230 *pxTopOfStack = 0x66666666;
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232 *pxTopOfStack = 0x55555555;
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234 *pxTopOfStack = 0x44444444;
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236 *pxTopOfStack = 0x33333333;
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238 *pxTopOfStack = 0x22222222;
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243 /* Leave space for the registers that will get popped from the stack
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244 when the task first starts executing. */
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245 pxTopOfStack -= 15;
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249 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */
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251 *pxTopOfStack = 0x12345678; /* Accumulator. */
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253 *pxTopOfStack = 0x87654321; /* Accumulator. */
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255 return pxTopOfStack;
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257 /*-----------------------------------------------------------*/
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259 portBASE_TYPE xPortStartScheduler( void )
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261 /* Use pxCurrentTCB just so it does not get optimised away. */
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262 if( pxCurrentTCB != NULL )
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264 /* Call an application function to set up the timer that will generate
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265 the tick interrupt. This way the application can decide which
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266 peripheral to use. If tickless mode is used then the default
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267 implementation defined in this file (which uses CMT0) should not be
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269 configSETUP_TICK_INTERRUPT();
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271 /* Enable the software interrupt. */
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272 _IEN( _ICU_SWINT ) = 1;
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274 /* Ensure the software interrupt is clear. */
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275 _IR( _ICU_SWINT ) = 0;
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277 /* Ensure the software interrupt is set to the kernel priority. */
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278 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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280 /* Start the first task. */
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281 prvStartFirstTask();
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284 /* Execution should not reach here as the tasks are now running!
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285 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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286 a warning about a statically declared function not being referenced in the
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287 case that the application writer has provided their own tick interrupt
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288 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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289 their own routine will be called in place of prvSetupTimerInterrupt()). */
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290 prvSetupTimerInterrupt();
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292 /* Should not get here. */
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295 /*-----------------------------------------------------------*/
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297 #pragma vector = configTICK_VECTOR
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298 __interrupt static void prvTickISR( void )
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300 /* Re-enable interrupts. */
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301 __enable_interrupt();
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303 /* Increment the tick, and perform any processing the new tick value
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305 __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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307 vTaskIncrementTick();
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309 __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
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311 /* Only select a new task if the preemptive scheduler is being used. */
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312 #if( configUSE_PREEMPTION == 1 )
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318 #if configUSE_TICKLESS_IDLE == 1
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320 /* The CPU woke because of a tick. */
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321 ulTickFlag = pdTRUE;
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323 /* If this is the first tick since exiting tickless mode then the CMT
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324 compare match value needs resetting. */
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325 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
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329 /*-----------------------------------------------------------*/
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331 void vPortEndScheduler( void )
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333 /* Not implemented as there is nothing to return to. */
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335 /*-----------------------------------------------------------*/
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337 static void prvSetupTimerInterrupt( void )
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340 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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346 SYSTEM.PRCR.WORD = portLOCK_KEY;
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348 /* Interrupt on compare match. */
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349 CMT0.CMCR.BIT.CMIE = 1;
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351 /* Set the compare match value. */
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352 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
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354 /* Divide the PCLK. */
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355 #if portCLOCK_DIVISOR == 512
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357 CMT0.CMCR.BIT.CKS = 3;
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359 #elif portCLOCK_DIVISOR == 128
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361 CMT0.CMCR.BIT.CKS = 2;
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363 #elif portCLOCK_DIVISOR == 32
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365 CMT0.CMCR.BIT.CKS = 1;
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367 #elif portCLOCK_DIVISOR == 8
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369 CMT0.CMCR.BIT.CKS = 0;
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373 #error Invalid portCLOCK_DIVISOR setting
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378 /* Enable the interrupt... */
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379 _IEN( _CMT0_CMI0 ) = 1;
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381 /* ...and set its priority to the application defined kernel priority. */
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382 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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384 /* Start the timer. */
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385 CMT.CMSTR0.BIT.STR0 = 1;
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387 /*-----------------------------------------------------------*/
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389 #if configUSE_TICKLESS_IDLE == 1
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391 static void prvSleep( portTickType xExpectedIdleTime )
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393 /* Allow the application to define some pre-sleep processing. */
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394 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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396 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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397 means the application defined code has already executed the WAIT
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399 if( xExpectedIdleTime > 0 )
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401 __wait_for_interrupt();
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404 /* Allow the application to define some post sleep processing. */
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405 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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408 #endif /* configUSE_TICKLESS_IDLE */
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409 /*-----------------------------------------------------------*/
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411 #if configUSE_TICKLESS_IDLE == 1
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413 void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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415 unsigned long ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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416 eSleepModeStatus eSleepAction;
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418 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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420 /* Make sure the CMT reload value does not overflow the counter. */
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421 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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423 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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426 /* Calculate the reload value required to wait xExpectedIdleTime tick
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428 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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429 if( ulMatchValue > ulStoppedTimerCompensation )
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431 /* Compensate for the fact that the CMT is going to be stopped
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433 ulMatchValue -= ulStoppedTimerCompensation;
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436 /* Stop the CMT momentarily. The time the CMT is stopped for is
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437 accounted for as best it can be, but using the tickless mode will
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438 inevitably result in some tiny drift of the time maintained by the
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439 kernel with respect to calendar time. */
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440 CMT.CMSTR0.BIT.STR0 = 0;
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441 while( CMT.CMSTR0.BIT.STR0 == 1 )
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443 /* Nothing to do here. */
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446 /* Critical section using the global interrupt bit as the i bit is
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447 automatically reset by the WAIT instruction. */
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448 __disable_interrupt();
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450 /* The tick flag is set to false before sleeping. If it is true when
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451 sleep mode is exited then sleep mode was probably exited because the
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452 tick was suppressed for the entire xExpectedIdleTime period. */
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453 ulTickFlag = pdFALSE;
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455 /* If a context switch is pending then abandon the low power entry as
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456 the context switch might have been pended by an external interrupt that
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457 requires processing. */
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458 eSleepAction = eTaskConfirmSleepModeStatus();
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459 if( eSleepAction == eAbortSleep )
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461 /* Restart tick. */
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462 CMT.CMSTR0.BIT.STR0 = 1;
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463 __enable_interrupt();
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465 else if( eSleepAction == eNoTasksWaitingTimeout )
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467 /* Protection off. */
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468 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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470 /* Ready for software standby with all clocks stopped. */
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471 SYSTEM.SBYCR.BIT.SSBY = 1;
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473 /* Protection on. */
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474 SYSTEM.PRCR.WORD = portLOCK_KEY;
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476 /* Sleep until something happens. Calling prvSleep() will
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477 automatically reset the i bit in the PSW. */
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478 prvSleep( xExpectedIdleTime );
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480 /* Restart the CMT. */
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481 CMT.CMSTR0.BIT.STR0 = 1;
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485 /* Protection off. */
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486 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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488 /* Ready for deep sleep mode. */
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489 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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490 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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491 SYSTEM.SBYCR.BIT.SSBY = 0;
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493 /* Protection on. */
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494 SYSTEM.PRCR.WORD = portLOCK_KEY;
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496 /* Adjust the match value to take into account that the current
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497 time slice is already partially complete. */
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498 ulMatchValue -= ( unsigned long ) CMT0.CMCNT;
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499 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
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501 /* Restart the CMT to count up to the new match value. */
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503 CMT.CMSTR0.BIT.STR0 = 1;
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505 /* Sleep until something happens. Calling prvSleep() will
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506 automatically reset the i bit in the PSW. */
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507 prvSleep( xExpectedIdleTime );
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509 /* Stop CMT. Again, the time the SysTick is stopped for is
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510 accounted for as best it can be, but using the tickless mode will
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511 inevitably result in some tiny drift of the time maintained by the
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512 kernel with respect to calendar time. */
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513 CMT.CMSTR0.BIT.STR0 = 0;
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514 while( CMT.CMSTR0.BIT.STR0 == 1 )
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516 /* Nothing to do here. */
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519 ulCurrentCount = ( unsigned long ) CMT0.CMCNT;
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521 if( ulTickFlag != pdFALSE )
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523 /* The tick interrupt has already executed, although because
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524 this function is called with the scheduler suspended the actual
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525 tick processing will not occur until after this function has
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526 exited. Reset the match value with whatever remains of this
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528 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
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529 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
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531 /* The tick interrupt handler will already have pended the tick
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532 processing in the kernel. As the pending tick will be
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533 processed as soon as this function exits, the tick value
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534 maintained by the tick is stepped forward by one less than the
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535 time spent sleeping. The actual stepping of the tick appears
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536 later in this function. */
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537 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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541 /* Something other than the tick interrupt ended the sleep.
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542 How many complete tick periods passed while the processor was
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544 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
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546 /* The match value is set to whatever fraction of a single tick
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548 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
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549 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
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552 /* Restart the CMT so it runs up to the match value. The match value
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553 will get set to the value required to generate exactly one tick period
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554 the next time the CMT interrupt executes. */
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556 CMT.CMSTR0.BIT.STR0 = 1;
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558 /* Wind the tick forward by the number of tick periods that the CPU
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559 remained in a low power state. */
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560 vTaskStepTick( ulCompleteTickPeriods );
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564 #endif /* configUSE_TICKLESS_IDLE */
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