2 FreeRTOS V7.1.1 - Copyright (C) 2012 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 ***************************************************************************
\r
46 * Having a problem? Start by reading the FAQ "My application does *
\r
47 * not run, what could be wrong? *
\r
49 * http://www.FreeRTOS.org/FAQHelp.html *
\r
51 ***************************************************************************
\r
54 http://www.FreeRTOS.org - Documentation, training, latest information,
\r
55 license and contact details.
\r
57 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
58 including FreeRTOS+Trace - an indispensable productivity tool.
\r
60 Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell
\r
61 the code with commercial support, indemnification, and middleware, under
\r
62 the OpenRTOS brand: http://www.OpenRTOS.com. High Integrity Systems also
\r
63 provide a safety engineered and independently SIL3 certified version under
\r
64 the SafeRTOS brand: http://www.SafeRTOS.com.
\r
67 /*-----------------------------------------------------------
\r
68 * Implementation of functions defined in portable.h for the ST STR75x ARM7
\r
70 *----------------------------------------------------------*/
\r
72 /* Library includes. */
\r
74 #include "75x_eic.h"
\r
76 /* Scheduler includes. */
\r
77 #include "FreeRTOS.h"
\r
80 /* Constants required to setup the initial stack. */
\r
81 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
\r
82 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
\r
84 /* Constants required to handle critical sections. */
\r
85 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
87 /* Prescale used on the timer clock when calculating the tick period. */
\r
88 #define portPRESCALE 20
\r
91 /*-----------------------------------------------------------*/
\r
93 /* Setup the TB to generate the tick interrupts. */
\r
94 static void prvSetupTimerInterrupt( void );
\r
96 /* ulCriticalNesting will get set to zero when the first task starts. It
\r
97 cannot be initialised to 0 as this will cause interrupts to be enabled
\r
98 during the kernel initialisation process. */
\r
99 unsigned long ulCriticalNesting = ( unsigned long ) 9999;
\r
101 /* Tick interrupt routines for preemptive operation. */
\r
102 __arm void vPortPreemptiveTick( void );
\r
104 /*-----------------------------------------------------------*/
\r
107 * Initialise the stack of a task to look exactly as if a call to
\r
108 * portSAVE_CONTEXT had been called.
\r
110 * See header file for description.
\r
112 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
114 portSTACK_TYPE *pxOriginalTOS;
\r
116 pxOriginalTOS = pxTopOfStack;
\r
118 /* To ensure asserts in tasks.c don't fail, although in this case the assert
\r
119 is not really required. */
\r
122 /* Setup the initial stack of the task. The stack is set exactly as
\r
123 expected by the portRESTORE_CONTEXT() macro. */
\r
125 /* First on the stack is the return address - which in this case is the
\r
126 start of the task. The offset is added to make the return address appear
\r
127 as it would within an IRQ ISR. */
\r
128 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
\r
131 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
\r
133 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
\r
135 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
137 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
139 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
141 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
143 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
145 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
147 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
149 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
151 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
153 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
155 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
157 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
160 /* When the task starts is will expect to find the function parameter in
\r
162 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
165 /* The status register is set for system mode, with interrupts enabled. */
\r
166 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
169 /* Interrupt flags cannot always be stored on the stack and will
\r
170 instead be stored in a variable, which is then saved as part of the
\r
172 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
174 return pxTopOfStack;
\r
176 /*-----------------------------------------------------------*/
\r
178 portBASE_TYPE xPortStartScheduler( void )
\r
180 extern void vPortStartFirstTask( void );
\r
182 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
184 prvSetupTimerInterrupt();
\r
186 /* Start the first task. */
\r
187 vPortStartFirstTask();
\r
189 /* Should not get here! */
\r
192 /*-----------------------------------------------------------*/
\r
194 void vPortEndScheduler( void )
\r
196 /* It is unlikely that the ARM port will require this function as there
\r
197 is nothing to return to. */
\r
199 /*-----------------------------------------------------------*/
\r
201 __arm void vPortPreemptiveTick( void )
\r
203 /* Increment the tick counter. */
\r
204 vTaskIncrementTick();
\r
206 /* The new tick value might unblock a task. Ensure the highest task that
\r
207 is ready to execute is the task that will execute when the tick ISR
\r
209 #if configUSE_PREEMPTION == 1
\r
210 vTaskSwitchContext();
\r
213 TB_ClearITPendingBit( TB_IT_Update );
\r
215 /*-----------------------------------------------------------*/
\r
217 static void prvSetupTimerInterrupt( void )
\r
219 EIC_IRQInitTypeDef EIC_IRQInitStructure;
\r
220 TB_InitTypeDef TB_InitStructure;
\r
222 /* Setup the EIC for the TB. */
\r
223 EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
\r
224 EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
\r
225 EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
\r
226 EIC_IRQInit(&EIC_IRQInitStructure);
\r
228 /* Setup the TB for the generation of the tick interrupt. */
\r
229 TB_InitStructure.TB_Mode = TB_Mode_Timing;
\r
230 TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
\r
231 TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
\r
232 TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
\r
233 TB_Init(&TB_InitStructure);
\r
235 /* Enable TB Update interrupt */
\r
236 TB_ITConfig(TB_IT_Update, ENABLE);
\r
238 /* Clear TB Update interrupt pending bit */
\r
239 TB_ClearITPendingBit(TB_IT_Update);
\r
244 /*-----------------------------------------------------------*/
\r
246 __arm __interwork void vPortEnterCritical( void )
\r
248 /* Disable interrupts first! */
\r
249 __disable_interrupt();
\r
251 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
252 directly. Increment ulCriticalNesting to keep a count of how many times
\r
253 portENTER_CRITICAL() has been called. */
\r
254 ulCriticalNesting++;
\r
256 /*-----------------------------------------------------------*/
\r
258 __arm __interwork void vPortExitCritical( void )
\r
260 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
262 /* Decrement the nesting count as we are leaving a critical section. */
\r
263 ulCriticalNesting--;
\r
265 /* If the nesting level has reached zero then interrupts should be
\r
267 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
269 __enable_interrupt();
\r
273 /*-----------------------------------------------------------*/
\r