2 FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not itcan be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the ST STR91x ARM9
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78 *----------------------------------------------------------*/
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80 /* Library includes. */
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81 #include "91x_lib.h"
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83 /* Standard includes. */
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87 /* Scheduler includes. */
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88 #include "FreeRTOS.h"
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91 #ifndef configUSE_WATCHDOG_TICK
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92 #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
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95 /* Constants required to setup the initial stack. */
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96 #ifndef _RUN_TASK_IN_ARM_MODE_
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97 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
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99 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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102 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
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104 /* Constants required to handle critical sections. */
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105 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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108 #define abs(x) ((x)>0 ? (x) : -(x))
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112 * Toggle a led using the following algorithm:
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113 * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
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115 * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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119 * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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123 #define TOGGLE_LED(port,pin) \
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124 if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
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126 (port)->DR[(pin) <<2] = 0x00; \
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130 (port)->DR[(pin) <<2] = (pin); \
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134 /*-----------------------------------------------------------*/
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136 /* Setup the watchdog to generate the tick interrupts. */
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137 static void prvSetupTimerInterrupt( void );
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139 /* ulCriticalNesting will get set to zero when the first task starts. It
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140 cannot be initialised to 0 as this will cause interrupts to be enabled
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141 during the kernel initialisation process. */
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142 unsigned long ulCriticalNesting = ( unsigned long ) 9999;
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144 /* Tick interrupt routines for cooperative and preemptive operation
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145 respectively. The preemptive version is not defined as __irq as it is called
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146 from an asm wrapper function. */
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147 void WDG_IRQHandler( void );
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149 /* VIC interrupt default handler. */
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150 static void prvDefaultHandler( void );
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152 #if configUSE_WATCHDOG_TICK == 0
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153 /* Used to update the OCR timer register */
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154 static u16 s_nPulseLength;
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157 /*-----------------------------------------------------------*/
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160 * Initialise the stack of a task to look exactly as if a call to
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161 * portSAVE_CONTEXT had been called.
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163 * See header file for description.
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165 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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167 portSTACK_TYPE *pxOriginalTOS;
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169 pxOriginalTOS = pxTopOfStack;
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171 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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172 is not really required. */
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175 /* Setup the initial stack of the task. The stack is set exactly as
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176 expected by the portRESTORE_CONTEXT() macro. */
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178 /* First on the stack is the return address - which in this case is the
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179 start of the task. The offset is added to make the return address appear
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180 as it would within an IRQ ISR. */
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181 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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184 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
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186 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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188 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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190 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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192 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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194 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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196 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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198 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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200 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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202 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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204 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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206 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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208 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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210 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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213 /* When the task starts is will expect to find the function parameter in
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215 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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218 /* The status register is set for system mode, with interrupts enabled. */
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219 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
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222 /* Interrupt flags cannot always be stored on the stack and will
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223 instead be stored in a variable, which is then saved as part of the
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225 *pxTopOfStack = portNO_CRITICAL_NESTING;
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227 return pxTopOfStack;
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229 /*-----------------------------------------------------------*/
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231 portBASE_TYPE xPortStartScheduler( void )
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233 extern void vPortStartFirstTask( void );
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235 /* Start the timer that generates the tick ISR. Interrupts are disabled
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237 prvSetupTimerInterrupt();
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239 /* Start the first task. */
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240 vPortStartFirstTask();
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242 /* Should not get here! */
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245 /*-----------------------------------------------------------*/
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247 void vPortEndScheduler( void )
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249 /* It is unlikely that the ARM port will require this function as there
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250 is nothing to return to. */
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252 /*-----------------------------------------------------------*/
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254 /* This function is called from an asm wrapper, so does not require the __irq
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256 #if configUSE_WATCHDOG_TICK == 1
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258 static void prvFindFactors(u32 n, u16 *a, u32 *b)
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260 /* This function is copied from the ST STR7 library and is
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261 copyright STMicroelectronics. Reproduced with permission. */
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265 long err, err_min=n;
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267 *a = a0 = ((n-1)/65536ul) + 1;
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270 for (; *a <= 256; (*a)++)
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273 err = (long)*a * (long)*b - (long)n;
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274 if (abs(err) > (*a / 2))
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277 err = (long)*a * (long)*b - (long)n;
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279 if (abs(err) < abs(err_min))
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284 if (err == 0) break;
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291 /*-----------------------------------------------------------*/
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293 static void prvSetupTimerInterrupt( void )
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295 WDG_InitTypeDef xWdg;
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297 unsigned long n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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299 /* Configure the watchdog as a free running timer that generates a
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300 periodic interrupt. */
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302 SCU_APBPeriphClockConfig( __WDG, ENABLE );
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304 WDG_StructInit(&xWdg);
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305 prvFindFactors( n, &a, &b );
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306 xWdg.WDG_Prescaler = a - 1;
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307 xWdg.WDG_Preload = b - 1;
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309 WDG_ITConfig(ENABLE);
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311 /* Configure the VIC for the WDG interrupt. */
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312 VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
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313 VIC_ITCmd( WDG_ITLine, ENABLE );
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315 /* Install the default handlers for both VIC's. */
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316 VIC0->DVAR = ( unsigned long ) prvDefaultHandler;
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317 VIC1->DVAR = ( unsigned long ) prvDefaultHandler;
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321 /*-----------------------------------------------------------*/
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323 void WDG_IRQHandler( void )
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326 /* Increment the tick counter. */
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327 vTaskIncrementTick();
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329 #if configUSE_PREEMPTION == 1
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331 /* The new tick value might unblock a task. Ensure the highest task that
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332 is ready to execute is the task that will execute when the tick ISR
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334 vTaskSwitchContext();
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336 #endif /* configUSE_PREEMPTION. */
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338 /* Clear the interrupt in the watchdog. */
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339 WDG->SR &= ~0x0001;
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345 static void prvFindFactors(u32 n, u8 *a, u16 *b)
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347 /* This function is copied from the ST STR7 library and is
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348 copyright STMicroelectronics. Reproduced with permission. */
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352 long err, err_min=n;
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355 *a = a0 = ((n-1)/256) + 1;
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358 for (; *a <= 256; (*a)++)
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361 err = (long)*a * (long)*b - (long)n;
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362 if (abs(err) > (*a / 2))
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365 err = (long)*a * (long)*b - (long)n;
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367 if (abs(err) < abs(err_min))
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372 if (err == 0) break;
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379 /*-----------------------------------------------------------*/
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381 static void prvSetupTimerInterrupt( void )
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385 unsigned long n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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387 TIM_InitTypeDef timer;
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389 SCU_APBPeriphClockConfig( __TIM23, ENABLE );
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391 TIM_StructInit(&timer);
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392 prvFindFactors( n, &a, &b );
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394 timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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395 timer.TIM_OC1_Modes = TIM_TIMING;
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396 timer.TIM_Clock_Source = TIM_CLK_APB;
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397 timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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398 timer.TIM_Prescaler = a-1;
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399 timer.TIM_Pulse_Level_1 = TIM_HIGH;
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400 timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
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402 TIM_Init (TIM2, &timer);
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403 TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
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404 /* Configure the VIC for the WDG interrupt. */
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405 VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
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406 VIC_ITCmd( TIM2_ITLine, ENABLE );
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408 /* Install the default handlers for both VIC's. */
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409 VIC0->DVAR = ( unsigned long ) prvDefaultHandler;
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410 VIC1->DVAR = ( unsigned long ) prvDefaultHandler;
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412 TIM_CounterCmd(TIM2, TIM_CLEAR);
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413 TIM_CounterCmd(TIM2, TIM_START);
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415 /*-----------------------------------------------------------*/
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417 void TIM2_IRQHandler( void )
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419 /* Reset the timer counter to avioid overflow. */
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420 TIM2->OC1R += s_nPulseLength;
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422 /* Increment the tick counter. */
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423 vTaskIncrementTick();
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425 #if configUSE_PREEMPTION == 1
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427 /* The new tick value might unblock a task. Ensure the highest task that
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428 is ready to execute is the task that will execute when the tick ISR
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430 vTaskSwitchContext();
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434 /* Clear the interrupt in the watchdog. */
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435 TIM2->SR &= ~TIM_FLAG_OC1;
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438 #endif /* USE_WATCHDOG_TICK */
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440 /*-----------------------------------------------------------*/
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442 __arm __interwork void vPortEnterCritical( void )
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444 /* Disable interrupts first! */
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445 portDISABLE_INTERRUPTS();
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447 /* Now interrupts are disabled ulCriticalNesting can be accessed
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448 directly. Increment ulCriticalNesting to keep a count of how many times
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449 portENTER_CRITICAL() has been called. */
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450 ulCriticalNesting++;
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452 /*-----------------------------------------------------------*/
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454 __arm __interwork void vPortExitCritical( void )
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456 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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458 /* Decrement the nesting count as we are leaving a critical section. */
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459 ulCriticalNesting--;
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461 /* If the nesting level has reached zero then interrupts should be
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463 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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465 portENABLE_INTERRUPTS();
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469 /*-----------------------------------------------------------*/
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471 static void prvDefaultHandler( void )
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