2 * FreeRTOS Kernel V10.1.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /*-----------------------------------------------------------
\r
29 * Implementation of functions defined in portable.h for the PIC32MEC14xx port.
\r
30 *----------------------------------------------------------*/
\r
32 /* Scheduler include files. */
\r
33 #include "FreeRTOS.h"
\r
36 /* Microchip includes. */
\r
38 #include <cp0defs.h>
\r
40 #if !defined(__MEC__)
\r
41 #error This port is designed to work with XC32 on MEC14xx. Please update your C compiler version or settings.
\r
44 #if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
\r
45 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
\r
48 /* Bits within various registers. */
\r
49 #define portIE_BIT ( 0x00000001 )
\r
50 #define portEXL_BIT ( 0x00000002 )
\r
52 /* The EXL bit is set to ensure interrupts do not occur while the context of
\r
53 the first task is being restored. MEC14xx does not have DSP HW. */
\r
54 #define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
\r
56 /* MEC14xx RTOS Timer MMCR's. */
\r
57 #define portMMCR_RTMR_PRELOAD *((volatile uint32_t *)(0xA0007404ul))
\r
58 #define portMMCR_RTMR_CONTROL *((volatile uint32_t *)(0xA0007408ul))
\r
60 /* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
\r
61 peripheral space. */
\r
62 #define portGIRQ23_RTOS_TIMER_BITPOS ( 4 )
\r
63 #define portGIRQ23_RTOS_TIMER_MASK ( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
\r
64 #define portMMCR_JTVIC_GIRQ23_SRC *((volatile uint32_t *)(0xBFFFC0F0ul))
\r
65 #define portMMCR_JTVIC_GIRQ23_SETEN *((volatile uint32_t *)(0xBFFFC0F4ul))
\r
66 #define portMMCR_JTVIC_GIRQ23_PRIA *((volatile uint32_t *)(0xBFFFC3F0ul))
\r
68 /* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
\r
69 #define portGIRQ24_M14K_SOFTIRQ0_BITPOS ( 1 )
\r
70 #define portGIRQ24_M14K_SOFTIRQ0_MASK ( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
\r
71 #define portMMCR_JTVIC_GIRQ24_SRC *((volatile uint32_t *)(0xBFFFC100ul))
\r
72 #define portMMCR_JTVIC_GIRQ24_SETEN *((volatile uint32_t *)(0xBFFFC104ul))
\r
73 #define portMMCR_JTVIC_GIRQ24_PRIA *((volatile uint32_t *)(0xBFFFC400ul))
\r
76 By default port.c generates its tick interrupt from the RTOS timer. The user
\r
77 can override this behaviour by:
\r
78 1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
\r
79 which is the function that configures the timer. The function is defined
\r
80 as a weak symbol in this file so if the same function name is used in the
\r
81 application code then the version in the application code will be linked
\r
82 into the application in preference to the version defined in this file.
\r
83 2: Provide a vector implementation in port_asm.S that overrides the default
\r
84 behaviour for the specified interrupt vector.
\r
85 3: Specify the correct bit to clear the interrupt during the timer interrupt
\r
88 #ifndef configTICK_INTERRUPT_VECTOR
\r
89 #define configTICK_INTERRUPT_VECTOR girq23_b4
\r
90 #define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
\r
92 #ifndef configCLEAR_TICK_TIMER_INTERRUPT
\r
93 #error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
\r
97 /* Let the user override the pre-loading of the initial RA with the address of
\r
98 prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
\r
99 in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
\r
100 #ifdef configTASK_RETURN_ADDRESS
\r
101 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
103 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
106 /* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
\r
107 stack checking. A problem in the ISR stack will trigger an assert, not call the
\r
108 stack overflow hook function (because the stack overflow hook is specific to a
\r
109 task stack, not the ISR stack). */
\r
110 #if( configCHECK_FOR_STACK_OVERFLOW > 2 )
\r
112 /* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
\r
113 the task stacks, and so will legitimately appear in many positions within
\r
115 #define portISR_STACK_FILL_BYTE 0xee
\r
117 static const uint8_t ucExpectedStackBytes[] = {
\r
118 portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
119 portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
120 portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
121 portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
\r
122 portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
\r
124 #define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
\r
126 /* Define the function away. */
\r
127 #define portCHECK_ISR_STACK()
\r
128 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
\r
131 /*-----------------------------------------------------------*/
\r
134 * Used to catch tasks that attempt to return from their implementing function.
\r
136 static void prvTaskExitError( void );
\r
138 /*-----------------------------------------------------------*/
\r
140 /* Records the interrupt nesting depth. This is initialised to one as it is
\r
141 decremented to 0 when the first task starts. */
\r
142 volatile UBaseType_t uxInterruptNesting = 0x01;
\r
144 /* Stores the task stack pointer when a switch is made to use the system stack. */
\r
145 UBaseType_t uxSavedTaskStackPointer = 0;
\r
147 /* The stack used by interrupt service routines that cause a context switch. */
\r
148 StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
\r
150 /* The top of stack value ensures there is enough space to store 6 registers on
\r
151 the callers stack, as some functions seem to want to do this. */
\r
152 const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
\r
154 /*-----------------------------------------------------------*/
\r
157 * See header file for description.
\r
159 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
161 /* Ensure byte alignment is maintained when leaving this function. */
\r
164 *pxTopOfStack = (StackType_t) 0xDEADBEEF;
\r
167 *pxTopOfStack = (StackType_t) 0x12345678; /* Word to which the stack pointer will be left pointing after context restore. */
\r
170 *pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
\r
173 *pxTopOfStack = (StackType_t) portINITIAL_SR; /* CP0_STATUS */
\r
176 *pxTopOfStack = (StackType_t) pxCode; /* CP0_EPC */
\r
179 *pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS; /* ra */
\r
180 pxTopOfStack -= 15;
\r
182 *pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
\r
183 pxTopOfStack -= 15;
\r
185 return pxTopOfStack;
\r
187 /*-----------------------------------------------------------*/
\r
189 static __inline uint32_t prvDisableInterrupt( void )
\r
191 uint32_t prev_state;
\r
193 __asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
\r
196 /*-----------------------------------------------------------*/
\r
198 static void prvTaskExitError( void )
\r
200 /* A function that implements a task must not exit or attempt to return to
\r
201 its caller as there is nothing to return to. If a task wants to exit it
\r
202 should instead call vTaskDelete( NULL ).
\r
204 Artificially force an assert() to be triggered if configASSERT() is
\r
205 defined, then stop here so application writers can catch the error. */
\r
206 configASSERT( uxSavedTaskStackPointer == 0UL );
\r
207 portDISABLE_INTERRUPTS();
\r
210 /*-----------------------------------------------------------*/
\r
213 * Setup a timer for a regular tick. This function uses the RTOS timer.
\r
214 * The function is declared weak so an application writer can use a different
\r
215 * timer by redefining this implementation. If a different timer is used then
\r
216 * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
\r
217 * ensure the RTOS provided tick interrupt handler is installed on the correct
\r
220 __attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
\r
222 /* MEC14xx RTOS Timer whose input clock is 32KHz. */
\r
223 const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
\r
225 configASSERT( ulPreload != 0UL );
\r
227 /* Configure the RTOS timer. */
\r
228 portMMCR_RTMR_CONTROL = 0ul;
\r
229 portMMCR_RTMR_PRELOAD = ulPreload;
\r
231 /* Configure interrupts from the RTOS timer. */
\r
232 portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
\r
233 portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
\r
234 portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
\r
235 portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
\r
237 /* Enable the RTOS timer. */
\r
238 portMMCR_RTMR_CONTROL = 0x0Fu;
\r
240 /*-----------------------------------------------------------*/
\r
242 void vPortEndScheduler(void)
\r
244 /* Not implemented in ports where there is nothing to return to.
\r
245 Artificially force an assert. */
\r
246 configASSERT( uxInterruptNesting == 1000UL );
\r
248 /*-----------------------------------------------------------*/
\r
250 BaseType_t xPortStartScheduler( void )
\r
252 extern void vPortStartFirstTask( void );
\r
253 extern void *pxCurrentTCB;
\r
255 #if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
\r
257 /* Fill the ISR stack to make it easy to asses how much is being used. */
\r
258 memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
\r
260 #endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
\r
262 /* Clear the software interrupt flag. */
\r
263 portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
\r
265 /* Set software timer priority. Each GIRQn has one nibble containing its
\r
267 portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
\r
268 portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
\r
270 /* Enable software interrupt. */
\r
271 portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
\r
273 /* Setup the timer to generate the tick. Interrupts will have been disabled
\r
274 by the time we get here. */
\r
275 vApplicationSetupTickTimerInterrupt();
\r
277 /* Start the highest priority task that has been created so far. Its stack
\r
278 location is loaded into uxSavedTaskStackPointer. */
\r
279 uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
\r
280 vPortStartFirstTask();
\r
282 /* Should never get here as the tasks will now be executing! Call the task
\r
283 exit error function to prevent compiler warnings about a static function
\r
284 not being called in the case that the application writer overrides this
\r
285 functionality by defining configTASK_RETURN_ADDRESS. */
\r
286 prvTaskExitError();
\r
290 /*-----------------------------------------------------------*/
\r
292 void vPortIncrementTick( void )
\r
294 UBaseType_t uxSavedStatus;
\r
297 uxSavedStatus = uxPortSetInterruptMaskFromISR();
\r
299 if( xTaskIncrementTick() != pdFALSE )
\r
301 /* Pend a context switch. */
\r
302 ulCause = ulPortGetCP0Cause();
\r
303 ulCause |= ( 1ul << 8UL );
\r
304 vPortSetCP0Cause( ulCause );
\r
307 vPortClearInterruptMaskFromISR( uxSavedStatus );
\r
309 /* Look for the ISR stack getting near or past its limit. */
\r
310 portCHECK_ISR_STACK();
\r
312 /* Clear timer interrupt. */
\r
313 configCLEAR_TICK_TIMER_INTERRUPT();
\r
315 /*-----------------------------------------------------------*/
\r
317 UBaseType_t uxPortSetInterruptMaskFromISR( void )
\r
319 UBaseType_t uxSavedStatusRegister;
\r
321 prvDisableInterrupt();
\r
322 uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
\r
324 /* This clears the IPL bits, then sets them to
\r
325 configMAX_SYSCALL_INTERRUPT_PRIORITY. This function should not be called
\r
326 from an interrupt that has a priority above
\r
327 configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
\r
328 can only result in the IPL being unchanged or raised, and therefore never
\r
330 vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
\r
332 return uxSavedStatusRegister;
\r
334 /*-----------------------------------------------------------*/
\r
336 void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
\r
338 vPortSetCP0Status( uxSavedStatusRegister );
\r
340 /*-----------------------------------------------------------*/
\r