2 FreeRTOS V9.0.0rc1 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 #include "FreeRTOSConfig.h"
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72 #define portCONTEXT_SIZE 160
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73 #define portEPC_STACK_LOCATION 152
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74 #define portSTATUS_STACK_LOCATION 156
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75 #define portFPCSR_STACK_LOCATION 0
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76 #define portTASK_HAS_FPU_STACK_LOCATION 0
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77 #define portFPU_CONTEXT_SIZE 264
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79 /******************************************************************/
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80 .macro portSAVE_FPU_REGS offset, base
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81 /* Macro to assist with saving just the FPU registers to the
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82 * specified address and base offset,
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83 * offset is a constant, base is the base pointer register */
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85 sdc1 $f31, \offset + 248(\base)
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86 sdc1 $f30, \offset + 240(\base)
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87 sdc1 $f29, \offset + 232(\base)
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88 sdc1 $f28, \offset + 224(\base)
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89 sdc1 $f27, \offset + 216(\base)
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90 sdc1 $f26, \offset + 208(\base)
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91 sdc1 $f25, \offset + 200(\base)
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92 sdc1 $f24, \offset + 192(\base)
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93 sdc1 $f23, \offset + 184(\base)
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94 sdc1 $f22, \offset + 176(\base)
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95 sdc1 $f21, \offset + 168(\base)
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96 sdc1 $f20, \offset + 160(\base)
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97 sdc1 $f19, \offset + 152(\base)
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98 sdc1 $f18, \offset + 144(\base)
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99 sdc1 $f17, \offset + 136(\base)
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100 sdc1 $f16, \offset + 128(\base)
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101 sdc1 $f15, \offset + 120(\base)
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102 sdc1 $f14, \offset + 112(\base)
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103 sdc1 $f13, \offset + 104(\base)
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104 sdc1 $f12, \offset + 96(\base)
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105 sdc1 $f11, \offset + 88(\base)
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106 sdc1 $f10, \offset + 80(\base)
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107 sdc1 $f9, \offset + 72(\base)
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108 sdc1 $f8, \offset + 64(\base)
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109 sdc1 $f7, \offset + 56(\base)
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110 sdc1 $f6, \offset + 48(\base)
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111 sdc1 $f5, \offset + 40(\base)
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112 sdc1 $f4, \offset + 32(\base)
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113 sdc1 $f3, \offset + 24(\base)
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114 sdc1 $f2, \offset + 16(\base)
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115 sdc1 $f1, \offset + 8(\base)
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116 sdc1 $f0, \offset + 0(\base)
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120 /******************************************************************/
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121 .macro portLOAD_FPU_REGS offset, base
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122 /* Macro to assist with loading just the FPU registers from the
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123 * specified address and base offset, offset is a constant,
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124 * base is the base pointer register */
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126 ldc1 $f0, \offset + 0(\base)
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127 ldc1 $f1, \offset + 8(\base)
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128 ldc1 $f2, \offset + 16(\base)
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129 ldc1 $f3, \offset + 24(\base)
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130 ldc1 $f4, \offset + 32(\base)
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131 ldc1 $f5, \offset + 40(\base)
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132 ldc1 $f6, \offset + 48(\base)
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133 ldc1 $f7, \offset + 56(\base)
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134 ldc1 $f8, \offset + 64(\base)
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135 ldc1 $f9, \offset + 72(\base)
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136 ldc1 $f10, \offset + 80(\base)
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137 ldc1 $f11, \offset + 88(\base)
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138 ldc1 $f12, \offset + 96(\base)
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139 ldc1 $f13, \offset + 104(\base)
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140 ldc1 $f14, \offset + 112(\base)
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141 ldc1 $f15, \offset + 120(\base)
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142 ldc1 $f16, \offset + 128(\base)
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143 ldc1 $f17, \offset + 136(\base)
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144 ldc1 $f18, \offset + 144(\base)
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145 ldc1 $f19, \offset + 152(\base)
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146 ldc1 $f20, \offset + 160(\base)
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147 ldc1 $f21, \offset + 168(\base)
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148 ldc1 $f22, \offset + 176(\base)
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149 ldc1 $f23, \offset + 184(\base)
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150 ldc1 $f24, \offset + 192(\base)
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151 ldc1 $f25, \offset + 200(\base)
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152 ldc1 $f26, \offset + 208(\base)
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153 ldc1 $f27, \offset + 216(\base)
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154 ldc1 $f28, \offset + 224(\base)
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155 ldc1 $f29, \offset + 232(\base)
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156 ldc1 $f30, \offset + 240(\base)
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157 ldc1 $f31, \offset + 248(\base)
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161 /******************************************************************/
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162 .macro portSAVE_CONTEXT
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164 /* Make room for the context. First save the current status so it can be
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165 manipulated, and the cause and EPC registers so their original values are
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167 mfc0 k0, _CP0_CAUSE
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168 addiu sp, sp, -portCONTEXT_SIZE
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170 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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171 /* Test if we are already using the system stack. Only tasks may use the
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172 FPU so if we are already in a nested interrupt then the FPU context does
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173 not require saving. */
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174 la k1, uxInterruptNesting
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179 /* Test if the current task needs the FPU context saving. */
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180 la k1, ulTaskHasFPUContext
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185 /* Adjust the stack to account for the additional FPU context.*/
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186 addiu sp, sp, -portFPU_CONTEXT_SIZE
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189 /* Save the ulTaskHasFPUContext flag. */
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190 sw k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
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195 mfc0 k1, _CP0_STATUS
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197 /* Also save s7, s6 and s5 so they can be used. Any nesting interrupts
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198 should maintain the values of these registers across the ISR. */
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202 sw k1, portSTATUS_STACK_LOCATION(sp)
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204 /* Prepare to enable interrupts above the current priority. */
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207 srl k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
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211 /* s5 is used as the frame pointer. */
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214 /* Check the nesting count value. */
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215 la k0, uxInterruptNesting
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218 /* If the nesting count is 0 then swap to the the system stack, otherwise
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219 the system stack is already being used. */
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223 /* Swap to the system stack. */
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224 la sp, xISRStackTop
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227 /* Increment and save the nesting count. */
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231 /* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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234 /* Re-enable interrupts. */
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235 mtc0 k1, _CP0_STATUS
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237 /* Save the context into the space just created. s6 is saved again
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238 here as it now contains the EPC value. No other s registers need be
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258 sw s6, portEPC_STACK_LOCATION(s5)
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261 /* Save the AC0, AC1, AC2, AC3 registers from the DSP. s6 is used as a
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262 scratch register. */
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278 /* Save the DSP Control register */
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282 /* ac0 is done separately to match the MX port. */
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288 /* Save the FPU context if the nesting count was zero. */
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289 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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290 la s6, uxInterruptNesting
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296 /* Test if the current task needs the FPU context saving. */
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297 lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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301 /* Save the FPU registers. */
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302 portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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304 /* Save the FPU status register */
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306 sw s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
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311 /* Update the task stack pointer value if nesting is zero. */
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312 la s6, uxInterruptNesting
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318 /* Save the stack pointer. */
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319 la s6, uxSavedTaskStackPointer
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324 /******************************************************************/
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325 .macro portRESTORE_CONTEXT
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327 /* Restore the stack pointer from the TCB. This is only done if the
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328 nesting count is 1. */
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329 la s6, uxInterruptNesting
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334 la s6, uxSavedTaskStackPointer
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337 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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338 /* Restore the FPU context if required. */
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339 lw s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
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343 /* Restore the FPU registers. */
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344 portLOAD_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
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346 /* Restore the FPU status register. */
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347 lw s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
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353 /* Restore the context. */
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369 /* Restore DSPControl. */
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379 /* s6 is loaded as it was used as a scratch register and therefore saved
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380 as part of the interrupt context. */
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402 /* Protect access to the k registers, and others. */
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406 /* Decrement the nesting count. */
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407 la k0, uxInterruptNesting
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412 #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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413 /* If the nesting count is now zero then the FPU context may be restored. */
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417 /* Restore the value of ulTaskHasFPUContext */
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418 la k0, ulTaskHasFPUContext
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422 /* If the task does not have an FPU context then adjust the stack normally. */
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426 /* Restore the STATUS and EPC registers */
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427 lw k0, portSTATUS_STACK_LOCATION(s5)
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428 lw k1, portEPC_STACK_LOCATION(s5)
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430 /* Leave the stack in its original state. First load sp from s5, then
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431 restore s5 from the stack. */
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435 /* Adjust the stack pointer to remove the FPU context */
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436 addiu sp, sp, portFPU_CONTEXT_SIZE
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440 1: /* Restore the STATUS and EPC registers */
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441 lw k0, portSTATUS_STACK_LOCATION(s5)
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442 lw k1, portEPC_STACK_LOCATION(s5)
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444 /* Leave the stack in its original state. First load sp from s5, then
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445 restore s5 from the stack. */
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449 2: /* Adjust the stack pointer */
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450 addiu sp, sp, portCONTEXT_SIZE
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454 /* Restore the frame when there is no hardware FP support. */
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455 lw k0, portSTATUS_STACK_LOCATION(s5)
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456 lw k1, portEPC_STACK_LOCATION(s5)
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458 /* Leave the stack in its original state. First load sp from s5, then
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459 restore s5 from the stack. */
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463 addiu sp, sp, portCONTEXT_SIZE
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465 #endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
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467 mtc0 k0, _CP0_STATUS
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