2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM4F port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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79 #ifndef configSYSTICK_CLOCK_HZ
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80 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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81 /* Ensure the SysTick is clocked at the same frequency as the core. */
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82 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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84 /* The way the SysTick is clocked is not modified in case it is not the same
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86 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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89 /* Constants required to manipulate the core. Registers first... */
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90 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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91 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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92 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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93 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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94 /* ...then bits in the registers. */
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95 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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96 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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97 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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98 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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99 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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101 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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102 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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104 /* Constants required to check the validity of an interrupt priority. */
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105 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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106 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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107 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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108 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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109 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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110 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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111 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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112 #define portPRIGROUP_SHIFT ( 8UL )
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114 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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115 #define portVECTACTIVE_MASK ( 0xFFUL )
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117 /* Constants required to manipulate the VFP. */
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118 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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119 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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121 /* Constants required to set up the initial stack. */
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122 #define portINITIAL_XPSR ( 0x01000000 )
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123 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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125 /* The systick is a 24-bit counter. */
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126 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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128 /* A fiddle factor to estimate the number of SysTick counts that would have
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129 occurred while the SysTick counter is stopped during tickless idle
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131 #define portMISSED_COUNTS_FACTOR ( 45UL )
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133 /* Let the user override the pre-loading of the initial LR with the address of
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134 prvTaskExitError() in case it messes up unwinding of the stack in the
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136 #ifdef configTASK_RETURN_ADDRESS
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137 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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139 #define portTASK_RETURN_ADDRESS prvTaskExitError
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142 /* Cannot find a weak linkage attribute, so the
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143 configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the
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144 application writer wants to provide their own implementation of
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145 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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147 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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148 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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151 /* Manual definition of missing asm names. */
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159 extern void *pxCurrentTCB;
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161 /* Each task maintains its own interrupt status in the critical nesting
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163 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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166 * Setup the timer to generate the tick interrupts. The implementation in this
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167 * file is weak to allow application writers to change the timer used to
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168 * generate the tick interrupt.
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170 void vPortSetupTimerInterrupt( void );
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173 * Exception handlers.
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175 void xPortPendSVHandler( void );
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176 void xPortSysTickHandler( void );
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177 void vPortSVCHandler( void );
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180 * Start first task is a separate function so it can be tested in isolation.
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182 static void prvPortStartFirstTask( void );
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185 * Function to enable the VFP.
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187 static void vPortEnableVFP( void );
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190 * Used to catch tasks that attempt to return from their implementing function.
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192 static void prvTaskExitError( void );
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194 /*-----------------------------------------------------------*/
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197 * The number of SysTick increments that make up one tick period.
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199 #if configUSE_TICKLESS_IDLE == 1
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200 static uint32_t ulTimerCountsForOneTick = 0;
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201 #endif /* configUSE_TICKLESS_IDLE */
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204 * The maximum number of tick periods that can be suppressed is limited by the
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205 * 24 bit resolution of the SysTick timer.
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207 #if configUSE_TICKLESS_IDLE == 1
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208 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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209 #endif /* configUSE_TICKLESS_IDLE */
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212 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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213 * power functionality only.
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215 #if configUSE_TICKLESS_IDLE == 1
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216 static uint32_t ulStoppedTimerCompensation = 0;
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217 #endif /* configUSE_TICKLESS_IDLE */
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220 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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221 * FreeRTOS API functions are not called from interrupts that have been assigned
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222 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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224 #if ( configASSERT_DEFINED == 1 )
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225 static uint8_t ucMaxSysCallPriority = 0;
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226 static uint32_t ulMaxPRIGROUPValue = 0;
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227 #endif /* configASSERT_DEFINED */
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229 /*-----------------------------------------------------------*/
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232 * See header file for description.
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234 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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236 /* Simulate the stack frame as it would be created by a context switch
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239 /* Offset added to account for the way the MCU uses the stack on entry/exit
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240 of interrupts, and to ensure alignment. */
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243 /* Sometimes the parameters are loaded from the stack. */
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244 *pxTopOfStack = ( StackType_t ) pvParameters;
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247 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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249 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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251 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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253 /* Save code space by skipping register initialisation. */
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254 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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255 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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257 /* A save method is being used that requires each task to maintain its
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258 own exec return value. */
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260 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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262 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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264 return pxTopOfStack;
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266 /*-----------------------------------------------------------*/
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268 static void prvTaskExitError( void )
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270 /* A function that implements a task must not exit or attempt to return to
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271 its caller as there is nothing to return to. If a task wants to exit it
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272 should instead call vTaskDelete( NULL ).
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274 Artificially force an assert() to be triggered if configASSERT() is
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275 defined, then stop here so application writers can catch the error. */
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276 configASSERT( uxCriticalNesting == ~0UL );
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277 portDISABLE_INTERRUPTS();
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280 /*-----------------------------------------------------------*/
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282 void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
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285 ldr r3, =_pxCurrentTCB /* Restore the context. */
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286 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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287 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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288 ldm r0!, (r4-r11, r14)/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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289 msr psp, r0 /* Restore the task stack pointer. */
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296 /*-----------------------------------------------------------*/
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298 static void prvPortStartFirstTask( void )
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301 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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304 msr msp, r0 /* Set the msp back to the start of the stack. */
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305 /* Clear the bit that indicates the FPU is in use in case the FPU was used
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306 before the scheduler was started - which would otherwise result in the
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307 unnecessary leaving of space in the SVC stack for lazy saving of FPU
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311 cpsie i /* Globally enable interrupts. */
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315 svc #0 /* System call to start first task. */
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319 /*-----------------------------------------------------------*/
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322 * See header file for description.
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324 BaseType_t xPortStartScheduler( void )
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326 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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327 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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328 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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330 #if( configASSERT_DEFINED == 1 )
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332 volatile uint32_t ulOriginalPriority;
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333 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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334 volatile uint8_t ucMaxPriorityValue;
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336 /* Determine the maximum priority from which ISR safe FreeRTOS API
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337 functions can be called. ISR safe functions are those that end in
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338 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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339 ensure interrupt entry is as fast and simple as possible.
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341 Save the interrupt priority value that is about to be clobbered. */
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342 ulOriginalPriority = *pucFirstUserPriorityRegister;
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344 /* Determine the number of priority bits available. First write to all
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346 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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348 /* Read the value back to see how many bits stuck. */
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349 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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351 /* The kernel interrupt priority should be set to the lowest
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353 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
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355 /* Use the same mask on the maximum system call priority. */
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356 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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358 /* Calculate the maximum acceptable priority group value for the number
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359 of bits read back. */
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360 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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361 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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363 ulMaxPRIGROUPValue--;
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364 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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367 #ifdef __NVIC_PRIO_BITS
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369 /* Check the CMSIS configuration that defines the number of
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370 priority bits matches the number of priority bits actually queried
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371 from the hardware. */
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372 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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376 #ifdef configPRIO_BITS
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378 /* Check the FreeRTOS configuration that defines the number of
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379 priority bits matches the number of priority bits actually queried
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380 from the hardware. */
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381 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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385 /* Shift the priority group value back to its position within the AIRCR
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387 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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388 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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390 /* Restore the clobbered interrupt priority register to its original
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392 *pucFirstUserPriorityRegister = ulOriginalPriority;
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394 #endif /* conifgASSERT_DEFINED */
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396 /* Make PendSV and SysTick the lowest priority interrupts. */
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397 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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398 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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400 /* Start the timer that generates the tick ISR. Interrupts are disabled
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402 vPortSetupTimerInterrupt();
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404 /* Initialise the critical nesting count ready for the first task. */
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405 uxCriticalNesting = 0;
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407 /* Ensure the VFP is enabled - it should be anyway. */
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410 /* Lazy save always. */
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411 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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413 /* Start the first task. */
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414 prvPortStartFirstTask();
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416 /* Should never get here as the tasks will now be executing! Call the task
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417 exit error function to prevent compiler warnings about a static function
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418 not being called in the case that the application writer overrides this
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419 functionality by defining configTASK_RETURN_ADDRESS. */
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420 prvTaskExitError();
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422 /* Should not get here! */
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425 /*-----------------------------------------------------------*/
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427 void vPortEndScheduler( void )
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429 /* Not implemented in ports where there is nothing to return to.
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430 Artificially force an assert. */
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431 configASSERT( uxCriticalNesting == 1000UL );
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433 /*-----------------------------------------------------------*/
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435 void vPortEnterCritical( void )
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437 portDISABLE_INTERRUPTS();
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438 uxCriticalNesting++;
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440 /* This is not the interrupt safe version of the enter critical function so
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441 assert() if it is being called from an interrupt context. Only API
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442 functions that end in "FromISR" can be used in an interrupt. Only assert if
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443 the critical nesting count is 1 to protect against recursive calls if the
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444 assert function also uses a critical section. */
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445 if( uxCriticalNesting == 1 )
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447 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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450 /*-----------------------------------------------------------*/
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452 void vPortExitCritical( void )
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454 configASSERT( uxCriticalNesting );
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455 uxCriticalNesting--;
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456 if( uxCriticalNesting == 0 )
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458 portENABLE_INTERRUPTS();
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461 /*-----------------------------------------------------------*/
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463 const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
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464 void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
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468 /* The function is not truly naked, so add back the 4 bytes subtracted
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469 from the stack pointer by the function prologue. */
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475 ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */
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478 tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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480 vstmdbeq r0!, (s16-s31)
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482 stmdb r0!, (r4-r11, r14) /* Save the core registers. */
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484 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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487 ldr r0, =_ucMaxSyscallInterruptPriority
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492 bl _vTaskSwitchContext
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497 ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. */
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500 ldm r0!, (r4-r11, r14) /* Pop the core registers. */
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502 tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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504 vldmiaeq r0!, (s16-s31)
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511 /*-----------------------------------------------------------*/
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513 void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
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515 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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516 executes all interrupts must be unmasked. There is therefore no need to
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517 save and then restore the interrupt mask value as its value is already
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518 known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
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519 used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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520 portDISABLE_INTERRUPTS();
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522 /* Increment the RTOS tick. */
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523 if( xTaskIncrementTick() != pdFALSE )
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525 /* A context switch is required. Context switching is performed in
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526 the PendSV interrupt. Pend the PendSV interrupt. */
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527 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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530 portENABLE_INTERRUPTS();
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532 /*-----------------------------------------------------------*/
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534 #if( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
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536 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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538 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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539 TickType_t xModifiableIdleTime;
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541 /* Make sure the SysTick reload value does not overflow the counter. */
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542 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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544 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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547 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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548 is accounted for as best it can be, but using the tickless mode will
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549 inevitably result in some tiny drift of the time maintained by the
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550 kernel with respect to calendar time. */
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551 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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553 /* Calculate the reload value required to wait xExpectedIdleTime
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554 tick periods. -1 is used because this code will execute part way
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555 through one of the tick periods. */
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556 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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557 if( ulReloadValue > ulStoppedTimerCompensation )
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559 ulReloadValue -= ulStoppedTimerCompensation;
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562 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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563 method as that will mask interrupts that should exit sleep mode. */
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564 __asm { "cpsid i" };
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568 /* If a context switch is pending or a task is waiting for the scheduler
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569 to be unsuspended then abandon the low power entry. */
\r
570 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
572 /* Restart from whatever is left in the count register to complete
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573 this tick period. */
\r
574 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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576 /* Restart SysTick. */
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577 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
579 /* Reset the reload register to the value required for normal tick
\r
581 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
583 /* Re-enable interrupts - see comments above the cpsid instruction()
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585 __asm { "cpsie i" };
\r
589 /* Set the new reload value. */
\r
590 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
592 /* Clear the SysTick count flag and set the count value back to
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594 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
596 /* Restart SysTick. */
\r
597 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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599 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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600 set its parameter to 0 to indicate that its implementation contains
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601 its own wait for interrupt or wait for event instruction, and so wfi
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602 should not be executed again. However, the original expected idle
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603 time variable must remain unmodified, so a copy is taken. */
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604 xModifiableIdleTime = xExpectedIdleTime;
\r
605 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
606 if( xModifiableIdleTime > 0 )
\r
612 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
614 /* Stop SysTick. Again, the time the SysTick is stopped for is
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615 accounted for as best it can be, but using the tickless mode will
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616 inevitably result in some tiny drift of the time maintained by the
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617 kernel with respect to calendar time. */
\r
618 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
619 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
\r
621 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
623 __asm { "cpsie i" };
\r
627 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
629 uint32_t ulCalculatedLoadValue;
\r
631 /* The tick interrupt has already executed, and the SysTick
\r
632 count reloaded with ulReloadValue. Reset the
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633 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
635 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
637 /* Don't allow a tiny value, or values that have somehow
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638 underflowed because the post sleep hook did something
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639 that took too long. */
\r
640 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
642 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
645 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
647 /* The tick interrupt handler will already have pended the tick
\r
648 processing in the kernel. As the pending tick will be
\r
649 processed as soon as this function exits, the tick value
\r
650 maintained by the tick is stepped forward by one less than the
\r
651 time spent waiting. */
\r
652 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
656 /* Something other than the tick interrupt ended the sleep.
\r
657 Work out how long the sleep lasted rounded to complete tick
\r
658 periods (not the ulReload value which accounted for part
\r
660 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
662 /* How many complete tick periods passed while the processor
\r
664 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
666 /* The reload value is set to whatever fraction of a single tick
\r
668 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
671 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
672 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
673 value. The critical section is used to ensure the tick interrupt
\r
674 can only execute once in the case that the reload register is near
\r
676 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
677 portENTER_CRITICAL();
\r
679 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
680 vTaskStepTick( ulCompleteTickPeriods );
\r
681 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
683 portEXIT_CRITICAL();
\r
687 #endif /* #if configUSE_TICKLESS_IDLE */
\r
688 /*-----------------------------------------------------------*/
\r
691 * Setup the systick timer to generate the tick interrupts at the required
\r
694 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
696 void vPortSetupTimerInterrupt( void )
\r
698 /* Calculate the constants required to configure the tick interrupt. */
\r
699 #if configUSE_TICKLESS_IDLE == 1
\r
701 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
702 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
703 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
705 #endif /* configUSE_TICKLESS_IDLE */
\r
707 /* Reset SysTick. */
\r
708 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
709 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
711 /* Configure SysTick to interrupt at the requested rate. */
\r
712 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
713 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
716 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
717 /*-----------------------------------------------------------*/
\r
719 /* This is a naked function. */
\r
720 static void vPortEnableVFP( void )
\r
723 ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
\r
726 orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
\r
731 /*-----------------------------------------------------------*/
\r
733 BaseType_t xPortIsInsideInterrupt( void )
\r
735 BaseType_t xReturn;
\r
737 /* Obtain the number of the currently executing interrupt. */
\r
738 if( CPU_REG_GET( CPU_IPSR ) == 0 )
\r
749 /*-----------------------------------------------------------*/
\r
751 #if( configASSERT_DEFINED == 1 )
\r
753 /* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
\r
754 global - which makes vPortValidateInterruptPriority() non re-entrant.
\r
755 However that should not matter as an interrupt can only itself be
\r
756 interrupted by a higher priority interrupt. That means if
\r
757 ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to
\r
758 an invalid interrupt priority being missed. */
\r
759 uint32_t ulCurrentInterrupt;
\r
760 uint8_t ucCurrentPriority;
\r
761 void vPortValidateInterruptPriority( void )
\r
763 /* Obtain the number of the currently executing interrupt. */
\r
764 __asm { push (r0, r1)
\r
766 ldr r1, =_ulCurrentInterrupt
\r
771 /* Is the interrupt number a user defined interrupt? */
\r
772 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
774 /* Look up the interrupt's priority. */
\r
775 ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) );
\r
777 /* The following assertion will fail if a service routine (ISR) for
\r
778 an interrupt that has been assigned a priority above
\r
779 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
780 function. ISR safe FreeRTOS API functions must *only* be called
\r
781 from interrupts that have been assigned a priority at or below
\r
782 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
784 Numerically low interrupt priority numbers represent logically high
\r
785 interrupt priorities, therefore the priority of the interrupt must
\r
786 be set to a value equal to or numerically *higher* than
\r
787 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
789 Interrupts that use the FreeRTOS API must not be left at their
\r
790 default priority of zero as that is the highest possible priority,
\r
791 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
792 and therefore also guaranteed to be invalid.
\r
794 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
795 interrupt entry is as fast and simple as possible.
\r
797 The following links provide detailed information:
\r
798 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
799 http://www.freertos.org/FAQHelp.html */
\r
800 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
803 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
804 that define each interrupt's priority to be split between bits that
\r
805 define the interrupt's pre-emption priority bits and bits that define
\r
806 the interrupt's sub-priority. For simplicity all bits must be defined
\r
807 to be pre-emption priority bits. The following assertion will fail if
\r
808 this is not the case (if some bits represent a sub-priority).
\r
810 If the application only uses CMSIS libraries for interrupt
\r
811 configuration then the correct setting can be achieved on all Cortex-M
\r
812 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
813 scheduler. Note however that some vendor specific peripheral libraries
\r
814 assume a non-zero priority group setting, in which cases using a value
\r
815 of zero will result in unpredicable behaviour. */
\r
816 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
819 #endif /* configASSERT_DEFINED */