2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /*-----------------------------------------------------------
\r
71 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
72 *----------------------------------------------------------*/
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
79 #ifndef configSYSTICK_CLOCK_HZ
\r
80 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
81 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
82 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
84 /* The way the SysTick is clocked is not modified in case it is not the same
\r
86 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
89 /* Constants required to manipulate the core. Registers first... */
\r
90 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
91 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
92 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
93 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
94 /* ...then bits in the registers. */
\r
95 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
96 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
97 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
98 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
99 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
101 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
102 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
104 /* Constants required to check the validity of an interrupt priority. */
\r
105 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
106 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
107 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
108 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
109 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
110 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
111 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
112 #define portPRIGROUP_SHIFT ( 8UL )
\r
114 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
115 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
117 /* Constants required to manipulate the VFP. */
\r
118 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
119 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
121 /* Constants required to set up the initial stack. */
\r
122 #define portINITIAL_XPSR ( 0x01000000 )
\r
123 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
\r
125 /* The systick is a 24-bit counter. */
\r
126 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
128 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
129 occurred while the SysTick counter is stopped during tickless idle
\r
131 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
133 /* Let the user override the pre-loading of the initial LR with the address of
\r
134 prvTaskExitError() in case it messes up unwinding of the stack in the
\r
136 #ifdef configTASK_RETURN_ADDRESS
\r
137 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
139 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
142 /* Cannot find a weak linkage attribute, so the
\r
143 configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the
\r
144 application writer wants to provide their own implementation of
\r
145 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
147 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
148 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
\r
151 /* Manual definition of missing asm names. */
\r
158 extern void *pxCurrentTCB;
\r
160 /* Each task maintains its own interrupt status in the critical nesting
\r
162 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
165 * Setup the timer to generate the tick interrupts. The implementation in this
\r
166 * file is weak to allow application writers to change the timer used to
\r
167 * generate the tick interrupt.
\r
169 void vPortSetupTimerInterrupt( void );
\r
172 * Exception handlers.
\r
174 void xPortPendSVHandler( void );
\r
175 void xPortSysTickHandler( void );
\r
176 void vPortSVCHandler( void );
\r
179 * Start first task is a separate function so it can be tested in isolation.
\r
181 static void prvPortStartFirstTask( void );
\r
184 * Function to enable the VFP.
\r
186 static void vPortEnableVFP( void );
\r
189 * Used to catch tasks that attempt to return from their implementing function.
\r
191 static void prvTaskExitError( void );
\r
193 /*-----------------------------------------------------------*/
\r
196 * The number of SysTick increments that make up one tick period.
\r
198 #if configUSE_TICKLESS_IDLE == 1
\r
199 static uint32_t ulTimerCountsForOneTick = 0;
\r
200 #endif /* configUSE_TICKLESS_IDLE */
\r
203 * The maximum number of tick periods that can be suppressed is limited by the
\r
204 * 24 bit resolution of the SysTick timer.
\r
206 #if configUSE_TICKLESS_IDLE == 1
\r
207 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
208 #endif /* configUSE_TICKLESS_IDLE */
\r
211 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
212 * power functionality only.
\r
214 #if configUSE_TICKLESS_IDLE == 1
\r
215 static uint32_t ulStoppedTimerCompensation = 0;
\r
216 #endif /* configUSE_TICKLESS_IDLE */
\r
219 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
220 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
221 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
223 #if ( configASSERT_DEFINED == 1 )
\r
224 static uint8_t ucMaxSysCallPriority = 0;
\r
225 static uint32_t ulMaxPRIGROUPValue = 0;
\r
226 #endif /* configASSERT_DEFINED */
\r
228 /*-----------------------------------------------------------*/
\r
231 * See header file for description.
\r
233 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
235 /* Simulate the stack frame as it would be created by a context switch
\r
238 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
239 of interrupts, and to ensure alignment. */
\r
242 /* Sometimes the parameters are loaded from the stack. */
\r
243 *pxTopOfStack = ( StackType_t ) pvParameters;
\r
246 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
248 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
250 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
252 /* Save code space by skipping register initialisation. */
\r
253 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
254 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
256 /* A save method is being used that requires each task to maintain its
\r
257 own exec return value. */
\r
259 *pxTopOfStack = portINITIAL_EXEC_RETURN;
\r
261 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
263 return pxTopOfStack;
\r
265 /*-----------------------------------------------------------*/
\r
267 static void prvTaskExitError( void )
\r
269 /* A function that implements a task must not exit or attempt to return to
\r
270 its caller as there is nothing to return to. If a task wants to exit it
\r
271 should instead call vTaskDelete( NULL ).
\r
273 Artificially force an assert() to be triggered if configASSERT() is
\r
274 defined, then stop here so application writers can catch the error. */
\r
275 configASSERT( uxCriticalNesting == ~0UL );
\r
276 portDISABLE_INTERRUPTS();
\r
279 /*-----------------------------------------------------------*/
\r
281 void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
\r
284 ldr r3, =_pxCurrentTCB /* Restore the context. */
\r
285 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
286 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
287 ldm r0!, (r4-r11, r14)/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
288 msr psp, r0 /* Restore the task stack pointer. */
\r
295 /*-----------------------------------------------------------*/
\r
297 static void prvPortStartFirstTask( void )
\r
300 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
\r
303 msr msp, r0 /* Set the msp back to the start of the stack. */
\r
304 cpsie i /* Globally enable interrupts. */
\r
308 svc #0 /* System call to start first task. */
\r
312 /*-----------------------------------------------------------*/
\r
315 * See header file for description.
\r
317 BaseType_t xPortStartScheduler( void )
\r
319 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
320 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
321 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
323 #if( configASSERT_DEFINED == 1 )
\r
325 volatile uint32_t ulOriginalPriority;
\r
326 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
327 volatile uint8_t ucMaxPriorityValue;
\r
329 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
330 functions can be called. ISR safe functions are those that end in
\r
331 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
332 ensure interrupt entry is as fast and simple as possible.
\r
334 Save the interrupt priority value that is about to be clobbered. */
\r
335 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
337 /* Determine the number of priority bits available. First write to all
\r
339 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
341 /* Read the value back to see how many bits stuck. */
\r
342 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
344 /* The kernel interrupt priority should be set to the lowest
\r
346 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
\r
348 /* Use the same mask on the maximum system call priority. */
\r
349 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
351 /* Calculate the maximum acceptable priority group value for the number
\r
352 of bits read back. */
\r
353 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
354 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
356 ulMaxPRIGROUPValue--;
\r
357 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
360 /* Shift the priority group value back to its position within the AIRCR
\r
362 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
363 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
365 /* Restore the clobbered interrupt priority register to its original
\r
367 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
369 #endif /* conifgASSERT_DEFINED */
\r
371 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
372 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
373 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
375 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
377 vPortSetupTimerInterrupt();
\r
379 /* Initialise the critical nesting count ready for the first task. */
\r
380 uxCriticalNesting = 0;
\r
382 /* Ensure the VFP is enabled - it should be anyway. */
\r
385 /* Lazy save always. */
\r
386 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
388 /* Start the first task. */
\r
389 prvPortStartFirstTask();
\r
391 /* Should never get here as the tasks will now be executing! Call the task
\r
392 exit error function to prevent compiler warnings about a static function
\r
393 not being called in the case that the application writer overrides this
\r
394 functionality by defining configTASK_RETURN_ADDRESS. */
\r
395 prvTaskExitError();
\r
397 /* Should not get here! */
\r
400 /*-----------------------------------------------------------*/
\r
402 void vPortEndScheduler( void )
\r
404 /* Not implemented in ports where there is nothing to return to.
\r
405 Artificially force an assert. */
\r
406 configASSERT( uxCriticalNesting == 1000UL );
\r
408 /*-----------------------------------------------------------*/
\r
410 void vPortEnterCritical( void )
\r
412 portDISABLE_INTERRUPTS();
\r
413 uxCriticalNesting++;
\r
415 /* This is not the interrupt safe version of the enter critical function so
\r
416 assert() if it is being called from an interrupt context. Only API
\r
417 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
418 the critical nesting count is 1 to protect against recursive calls if the
\r
419 assert function also uses a critical section. */
\r
420 if( uxCriticalNesting == 1 )
\r
422 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
425 /*-----------------------------------------------------------*/
\r
427 void vPortExitCritical( void )
\r
429 configASSERT( uxCriticalNesting );
\r
430 uxCriticalNesting--;
\r
431 if( uxCriticalNesting == 0 )
\r
433 portENABLE_INTERRUPTS();
\r
436 /*-----------------------------------------------------------*/
\r
438 const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
\r
439 void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
\r
443 /* The function is not truly naked, so add back the 4 bytes subtracted
\r
444 from the stack pointer by the function prologue. */
\r
450 ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */
\r
453 tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
\r
455 vstmdbeq r0!, (s16-s31)
\r
457 stmdb r0!, (r4-r11, r14) /* Save the core registers. */
\r
459 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
\r
460 /*_RB_? mrs r0, psp why was this here? */
\r
463 ldr r0, =_ucMaxSyscallInterruptPriority
\r
468 bl _vTaskSwitchContext
\r
473 ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. */
\r
476 ldm r0!, (r4-r11, r14) /* Pop the core registers. */
\r
478 tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
480 vldmiaeq r0!, (s16-s31)
\r
487 /*-----------------------------------------------------------*/
\r
489 void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
\r
491 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
492 executes all interrupts must be unmasked. There is therefore no need to
\r
493 save and then restore the interrupt mask value as its value is already
\r
494 known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
\r
495 used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
\r
496 portDISABLE_INTERRUPTS();
\r
498 /* Increment the RTOS tick. */
\r
499 if( xTaskIncrementTick() != pdFALSE )
\r
501 /* A context switch is required. Context switching is performed in
\r
502 the PendSV interrupt. Pend the PendSV interrupt. */
\r
503 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
506 portENABLE_INTERRUPTS();
\r
508 /*-----------------------------------------------------------*/
\r
510 #if( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
\r
512 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
514 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
\r
515 TickType_t xModifiableIdleTime;
\r
517 /* Make sure the SysTick reload value does not overflow the counter. */
\r
518 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
520 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
523 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
524 is accounted for as best it can be, but using the tickless mode will
\r
525 inevitably result in some tiny drift of the time maintained by the
\r
526 kernel with respect to calendar time. */
\r
527 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
529 /* Calculate the reload value required to wait xExpectedIdleTime
\r
530 tick periods. -1 is used because this code will execute part way
\r
531 through one of the tick periods. */
\r
532 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
533 if( ulReloadValue > ulStoppedTimerCompensation )
\r
535 ulReloadValue -= ulStoppedTimerCompensation;
\r
538 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
539 method as that will mask interrupts that should exit sleep mode. */
\r
540 __asm { "cpsid i" };
\r
544 /* If a context switch is pending or a task is waiting for the scheduler
\r
545 to be unsuspended then abandon the low power entry. */
\r
546 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
548 /* Restart from whatever is left in the count register to complete
\r
549 this tick period. */
\r
550 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
552 /* Restart SysTick. */
\r
553 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
555 /* Reset the reload register to the value required for normal tick
\r
557 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
559 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
561 __asm { "cpsie i" };
\r
565 /* Set the new reload value. */
\r
566 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
568 /* Clear the SysTick count flag and set the count value back to
\r
570 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
572 /* Restart SysTick. */
\r
573 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
575 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
576 set its parameter to 0 to indicate that its implementation contains
\r
577 its own wait for interrupt or wait for event instruction, and so wfi
\r
578 should not be executed again. However, the original expected idle
\r
579 time variable must remain unmodified, so a copy is taken. */
\r
580 xModifiableIdleTime = xExpectedIdleTime;
\r
581 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
582 if( xModifiableIdleTime > 0 )
\r
588 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
590 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
591 accounted for as best it can be, but using the tickless mode will
\r
592 inevitably result in some tiny drift of the time maintained by the
\r
593 kernel with respect to calendar time. */
\r
594 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
595 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
\r
597 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
599 __asm { "cpsie i" };
\r
603 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
605 uint32_t ulCalculatedLoadValue;
\r
607 /* The tick interrupt has already executed, and the SysTick
\r
608 count reloaded with ulReloadValue. Reset the
\r
609 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
611 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
613 /* Don't allow a tiny value, or values that have somehow
\r
614 underflowed because the post sleep hook did something
\r
615 that took too long. */
\r
616 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
618 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
621 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
623 /* The tick interrupt handler will already have pended the tick
\r
624 processing in the kernel. As the pending tick will be
\r
625 processed as soon as this function exits, the tick value
\r
626 maintained by the tick is stepped forward by one less than the
\r
627 time spent waiting. */
\r
628 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
632 /* Something other than the tick interrupt ended the sleep.
\r
633 Work out how long the sleep lasted rounded to complete tick
\r
634 periods (not the ulReload value which accounted for part
\r
636 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
638 /* How many complete tick periods passed while the processor
\r
640 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
642 /* The reload value is set to whatever fraction of a single tick
\r
644 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
647 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
648 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
649 value. The critical section is used to ensure the tick interrupt
\r
650 can only execute once in the case that the reload register is near
\r
652 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
653 portENTER_CRITICAL();
\r
655 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
656 vTaskStepTick( ulCompleteTickPeriods );
\r
657 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
659 portEXIT_CRITICAL();
\r
663 #endif /* #if configUSE_TICKLESS_IDLE */
\r
664 /*-----------------------------------------------------------*/
\r
667 * Setup the systick timer to generate the tick interrupts at the required
\r
670 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
672 void vPortSetupTimerInterrupt( void )
\r
674 /* Calculate the constants required to configure the tick interrupt. */
\r
675 #if configUSE_TICKLESS_IDLE == 1
\r
677 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
678 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
679 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
681 #endif /* configUSE_TICKLESS_IDLE */
\r
683 /* Configure SysTick to interrupt at the requested rate. */
\r
684 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
685 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
688 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
689 /*-----------------------------------------------------------*/
\r
691 /* This is a naked function. */
\r
692 static void vPortEnableVFP( void )
\r
695 ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
\r
698 orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
\r
703 /*-----------------------------------------------------------*/
\r
705 BaseType_t xPortIsInsideInterrupt( void )
\r
707 BaseType_t xReturn;
\r
709 /* Obtain the number of the currently executing interrupt. */
\r
710 if( CPU_REG_GET( CPU_IPSR ) == 0 )
\r
721 /*-----------------------------------------------------------*/
\r
723 #if( configASSERT_DEFINED == 1 )
\r
725 /* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
\r
726 global - which makes vPortValidateInterruptPriority() non re-entrant.
\r
727 However that should not matter as an interrupt can only itself be
\r
728 interrupted by a higher priority interrupt. That means if
\r
729 ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to
\r
730 an invalid interrupt priority being missed. */
\r
731 uint32_t ulCurrentInterrupt;
\r
732 uint8_t ucCurrentPriority;
\r
733 void vPortValidateInterruptPriority( void )
\r
735 /* Obtain the number of the currently executing interrupt. */
\r
736 __asm { push (r0, r1)
\r
738 ldr r1, =_ulCurrentInterrupt
\r
743 /* Is the interrupt number a user defined interrupt? */
\r
744 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
746 /* Look up the interrupt's priority. */
\r
747 ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) );
\r
749 /* The following assertion will fail if a service routine (ISR) for
\r
750 an interrupt that has been assigned a priority above
\r
751 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
752 function. ISR safe FreeRTOS API functions must *only* be called
\r
753 from interrupts that have been assigned a priority at or below
\r
754 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
756 Numerically low interrupt priority numbers represent logically high
\r
757 interrupt priorities, therefore the priority of the interrupt must
\r
758 be set to a value equal to or numerically *higher* than
\r
759 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
761 Interrupts that use the FreeRTOS API must not be left at their
\r
762 default priority of zero as that is the highest possible priority,
\r
763 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
764 and therefore also guaranteed to be invalid.
\r
766 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
767 interrupt entry is as fast and simple as possible.
\r
769 The following links provide detailed information:
\r
770 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
771 http://www.freertos.org/FAQHelp.html */
\r
772 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
775 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
776 that define each interrupt's priority to be split between bits that
\r
777 define the interrupt's pre-emption priority bits and bits that define
\r
778 the interrupt's sub-priority. For simplicity all bits must be defined
\r
779 to be pre-emption priority bits. The following assertion will fail if
\r
780 this is not the case (if some bits represent a sub-priority).
\r
782 If the application only uses CMSIS libraries for interrupt
\r
783 configuration then the correct setting can be achieved on all Cortex-M
\r
784 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
785 scheduler. Note however that some vendor specific peripheral libraries
\r
786 assume a non-zero priority group setting, in which cases using a value
\r
787 of zero will result in unpredicable behaviour. */
\r
788 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
791 #endif /* configASSERT_DEFINED */