2 * FreeRTOS Kernel V10.1.1
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3 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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29 /* Standard includes. */
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 /* Constants required to setup the initial task context. */
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37 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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38 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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39 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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40 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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42 /* Constants required to setup the tick ISR. */
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43 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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44 #define portPRESCALE_VALUE 0x00
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45 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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46 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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48 /* Constants required to setup the VIC for the tick ISR. */
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49 #define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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50 #define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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51 #define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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53 /* Constants required to handle interrupts. */
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54 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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55 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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57 /*-----------------------------------------------------------*/
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59 /* The code generated by the Keil compiler does not maintain separate
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60 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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61 use the stack as per other ports. Instead a variable is used to keep
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62 track of the critical section nesting. This variable has to be stored
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63 as part of the task context and must be initialised to a non zero value. */
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65 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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66 volatile uint32_t ulCriticalNesting = 9999UL;
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68 /*-----------------------------------------------------------*/
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70 /* Setup the timer to generate the tick interrupts. */
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71 static void prvSetupTimerInterrupt( void );
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74 * The scheduler can only be started from ARM mode, so
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75 * vPortStartFirstSTask() is defined in portISR.c.
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77 extern __asm void vPortStartFirstTask( void );
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79 /*-----------------------------------------------------------*/
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82 * See header file for description.
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84 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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86 StackType_t *pxOriginalTOS;
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88 /* Setup the initial stack of the task. The stack is set exactly as
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89 expected by the portRESTORE_CONTEXT() macro.
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91 Remember where the top of the (simulated) stack is before we place
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93 pxOriginalTOS = pxTopOfStack;
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95 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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96 is not really required. */
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99 /* First on the stack is the return address - which in this case is the
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100 start of the task. The offset is added to make the return address appear
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101 as it would within an IRQ ISR. */
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102 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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105 *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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107 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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109 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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111 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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113 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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115 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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117 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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119 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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121 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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123 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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125 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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127 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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129 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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131 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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133 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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136 /* The last thing onto the stack is the status register, which is set for
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137 system mode, with interrupts enabled. */
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138 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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140 if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
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142 /* We want the task to start in thumb mode. */
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143 *pxTopOfStack |= portTHUMB_MODE_BIT;
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148 /* The code generated by the Keil compiler does not maintain separate
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149 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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150 use the stack as per other ports. Instead a variable is used to keep
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151 track of the critical section nesting. This variable has to be stored
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152 as part of the task context and is initially set to zero. */
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153 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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155 return pxTopOfStack;
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157 /*-----------------------------------------------------------*/
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159 BaseType_t xPortStartScheduler( void )
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161 /* Start the timer that generates the tick ISR. */
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162 prvSetupTimerInterrupt();
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164 /* Start the first task. This is done from portISR.c as ARM mode must be
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166 vPortStartFirstTask();
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168 /* Should not get here! */
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171 /*-----------------------------------------------------------*/
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173 void vPortEndScheduler( void )
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175 /* It is unlikely that the ARM port will require this function as there
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176 is nothing to return to. If this is required - stop the tick ISR then
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177 return back to main. */
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179 /*-----------------------------------------------------------*/
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181 #if configUSE_PREEMPTION == 0
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184 * The cooperative scheduler requires a normal IRQ service routine to
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185 * simply increment the system tick.
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187 void vNonPreemptiveTick( void ) __irq;
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188 void vNonPreemptiveTick( void ) __irq
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190 /* Increment the tick count - this may make a delaying task ready
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191 to run - but a context switch is not performed. */
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192 xTaskIncrementTick();
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194 T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */
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195 VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
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201 **************************************************************************
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202 * The preemptive scheduler ISR is written in assembler and can be found
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203 * in the portASM.s file. This will only get used if portUSE_PREEMPTION
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204 * is set to 1 in portmacro.h
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205 **************************************************************************
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208 void vPreemptiveTick( void );
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211 /*-----------------------------------------------------------*/
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213 static void prvSetupTimerInterrupt( void )
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215 uint32_t ulCompareMatch;
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217 /* A 1ms tick does not require the use of the timer prescale. This is
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218 defaulted to zero but can be used if necessary. */
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219 T0PR = portPRESCALE_VALUE;
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221 /* Calculate the match value required for our wanted tick rate. */
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222 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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224 /* Protect against divide by zero. Using an if() statement still results
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225 in a warning - hence the #if. */
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226 #if portPRESCALE_VALUE != 0
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228 ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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232 T0MR0 = ulCompareMatch;
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234 /* Generate tick with timer 0 compare match. */
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235 T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
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237 /* Setup the VIC for the timer. */
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238 VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
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239 VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
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241 /* The ISR installed depends on whether the preemptive or cooperative
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242 scheduler is being used. */
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243 #if configUSE_PREEMPTION == 1
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245 VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
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249 VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
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253 VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
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255 /* Start the timer - interrupts are disabled when this function is called
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256 so it is okay to do this here. */
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257 T0TCR = portENABLE_TIMER;
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259 /*-----------------------------------------------------------*/
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261 void vPortEnterCritical( void )
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263 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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266 /* Now interrupts are disabled ulCriticalNesting can be accessed
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267 directly. Increment ulCriticalNesting to keep a count of how many times
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268 portENTER_CRITICAL() has been called. */
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269 ulCriticalNesting++;
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271 /*-----------------------------------------------------------*/
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273 void vPortExitCritical( void )
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275 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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277 /* Decrement the nesting count as we are leaving a critical section. */
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278 ulCriticalNesting--;
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280 /* If the nesting level has reached zero then interrupts should be
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282 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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284 /* Enable interrupts as per portEXIT_CRITICAL(). */
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289 /*-----------------------------------------------------------*/
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