2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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71 /* Standard includes. */
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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78 /* Constants required to setup the initial task context. */
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79 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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80 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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81 #define portINSTRUCTION_SIZE ( ( StackType_t ) 4 )
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82 #define portNO_CRITICAL_SECTION_NESTING ( ( StackType_t ) 0 )
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84 /* Constants required to setup the tick ISR. */
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85 #define portENABLE_TIMER ( ( uint8_t ) 0x01 )
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86 #define portPRESCALE_VALUE 0x00
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87 #define portINTERRUPT_ON_MATCH ( ( uint32_t ) 0x01 )
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88 #define portRESET_COUNT_ON_MATCH ( ( uint32_t ) 0x02 )
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90 /* Constants required to setup the VIC for the tick ISR. */
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91 #define portTIMER_VIC_CHANNEL ( ( uint32_t ) 0x0004 )
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92 #define portTIMER_VIC_CHANNEL_BIT ( ( uint32_t ) 0x0010 )
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93 #define portTIMER_VIC_ENABLE ( ( uint32_t ) 0x0020 )
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95 /* Constants required to handle interrupts. */
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96 #define portTIMER_MATCH_ISR_BIT ( ( uint8_t ) 0x01 )
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97 #define portCLEAR_VIC_INTERRUPT ( ( uint32_t ) 0 )
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99 /*-----------------------------------------------------------*/
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101 /* The code generated by the Keil compiler does not maintain separate
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102 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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103 use the stack as per other ports. Instead a variable is used to keep
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104 track of the critical section nesting. This variable has to be stored
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105 as part of the task context and must be initialised to a non zero value. */
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107 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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108 volatile uint32_t ulCriticalNesting = 9999UL;
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110 /*-----------------------------------------------------------*/
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112 /* Setup the timer to generate the tick interrupts. */
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113 static void prvSetupTimerInterrupt( void );
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116 * The scheduler can only be started from ARM mode, so
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117 * vPortStartFirstSTask() is defined in portISR.c.
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119 extern __asm void vPortStartFirstTask( void );
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121 /*-----------------------------------------------------------*/
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124 * See header file for description.
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126 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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128 StackType_t *pxOriginalTOS;
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130 /* Setup the initial stack of the task. The stack is set exactly as
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131 expected by the portRESTORE_CONTEXT() macro.
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133 Remember where the top of the (simulated) stack is before we place
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135 pxOriginalTOS = pxTopOfStack;
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137 /* To ensure asserts in tasks.c don't fail, although in this case the assert
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138 is not really required. */
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141 /* First on the stack is the return address - which in this case is the
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142 start of the task. The offset is added to make the return address appear
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143 as it would within an IRQ ISR. */
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144 *pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
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147 *pxTopOfStack = ( StackType_t ) 0xaaaaaaaa; /* R14 */
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149 *pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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151 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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153 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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155 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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157 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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159 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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161 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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163 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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165 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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167 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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169 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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171 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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173 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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175 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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178 /* The last thing onto the stack is the status register, which is set for
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179 system mode, with interrupts enabled. */
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180 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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182 if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
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184 /* We want the task to start in thumb mode. */
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185 *pxTopOfStack |= portTHUMB_MODE_BIT;
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190 /* The code generated by the Keil compiler does not maintain separate
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191 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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192 use the stack as per other ports. Instead a variable is used to keep
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193 track of the critical section nesting. This variable has to be stored
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194 as part of the task context and is initially set to zero. */
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195 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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197 return pxTopOfStack;
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199 /*-----------------------------------------------------------*/
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201 BaseType_t xPortStartScheduler( void )
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203 /* Start the timer that generates the tick ISR. */
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204 prvSetupTimerInterrupt();
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206 /* Start the first task. This is done from portISR.c as ARM mode must be
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208 vPortStartFirstTask();
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210 /* Should not get here! */
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213 /*-----------------------------------------------------------*/
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215 void vPortEndScheduler( void )
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217 /* It is unlikely that the ARM port will require this function as there
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218 is nothing to return to. If this is required - stop the tick ISR then
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219 return back to main. */
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221 /*-----------------------------------------------------------*/
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223 #if configUSE_PREEMPTION == 0
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226 * The cooperative scheduler requires a normal IRQ service routine to
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227 * simply increment the system tick.
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229 void vNonPreemptiveTick( void ) __irq;
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230 void vNonPreemptiveTick( void ) __irq
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232 /* Increment the tick count - this may make a delaying task ready
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233 to run - but a context switch is not performed. */
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234 xTaskIncrementTick();
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236 T0IR = portTIMER_MATCH_ISR_BIT; /* Clear the timer event */
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237 VICVectAddr = portCLEAR_VIC_INTERRUPT; /* Acknowledge the Interrupt */
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243 **************************************************************************
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244 * The preemptive scheduler ISR is written in assembler and can be found
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245 * in the portASM.s file. This will only get used if portUSE_PREEMPTION
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246 * is set to 1 in portmacro.h
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247 **************************************************************************
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250 void vPreemptiveTick( void );
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253 /*-----------------------------------------------------------*/
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255 static void prvSetupTimerInterrupt( void )
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257 uint32_t ulCompareMatch;
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259 /* A 1ms tick does not require the use of the timer prescale. This is
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260 defaulted to zero but can be used if necessary. */
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261 T0PR = portPRESCALE_VALUE;
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263 /* Calculate the match value required for our wanted tick rate. */
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264 ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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266 /* Protect against divide by zero. Using an if() statement still results
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267 in a warning - hence the #if. */
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268 #if portPRESCALE_VALUE != 0
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270 ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
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274 T0MR0 = ulCompareMatch;
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276 /* Generate tick with timer 0 compare match. */
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277 T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
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279 /* Setup the VIC for the timer. */
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280 VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
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281 VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
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283 /* The ISR installed depends on whether the preemptive or cooperative
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284 scheduler is being used. */
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285 #if configUSE_PREEMPTION == 1
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287 VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
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291 VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
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295 VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
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297 /* Start the timer - interrupts are disabled when this function is called
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298 so it is okay to do this here. */
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299 T0TCR = portENABLE_TIMER;
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301 /*-----------------------------------------------------------*/
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303 void vPortEnterCritical( void )
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305 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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308 /* Now interrupts are disabled ulCriticalNesting can be accessed
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309 directly. Increment ulCriticalNesting to keep a count of how many times
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310 portENTER_CRITICAL() has been called. */
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311 ulCriticalNesting++;
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313 /*-----------------------------------------------------------*/
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315 void vPortExitCritical( void )
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317 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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319 /* Decrement the nesting count as we are leaving a critical section. */
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320 ulCriticalNesting--;
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322 /* If the nesting level has reached zero then interrupts should be
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324 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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326 /* Enable interrupts as per portEXIT_CRITICAL(). */
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331 /*-----------------------------------------------------------*/
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