2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /* Standard includes. */
\r
73 /* Scheduler includes. */
\r
74 #include "FreeRTOS.h"
\r
77 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
\r
78 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
81 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
\r
82 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
85 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
\r
86 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
89 #ifndef configSETUP_TICK_INTERRUPT
\r
90 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
91 #endif /* configSETUP_TICK_INTERRUPT */
\r
93 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
\r
94 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
97 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
\r
98 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
\r
101 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
\r
102 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
\r
105 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
\r
106 /* Check the configuration. */
\r
107 #if( configMAX_PRIORITIES > 32 )
\r
108 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
\r
110 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
112 /* In case security extensions are implemented. */
\r
113 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
114 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
117 #ifndef configCLEAR_TICK_INTERRUPT
\r
118 #define configCLEAR_TICK_INTERRUPT()
\r
121 /* The number of bits to shift for an interrupt priority is dependent on the
\r
122 number of bits implemented by the interrupt controller. */
\r
123 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
\r
124 #define portPRIORITY_SHIFT 4
\r
125 #define portMAX_BINARY_POINT_VALUE 3
\r
126 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
\r
127 #define portPRIORITY_SHIFT 3
\r
128 #define portMAX_BINARY_POINT_VALUE 2
\r
129 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
\r
130 #define portPRIORITY_SHIFT 2
\r
131 #define portMAX_BINARY_POINT_VALUE 1
\r
132 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
\r
133 #define portPRIORITY_SHIFT 1
\r
134 #define portMAX_BINARY_POINT_VALUE 0
\r
135 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
\r
136 #define portPRIORITY_SHIFT 0
\r
137 #define portMAX_BINARY_POINT_VALUE 0
\r
139 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
\r
142 /* A critical section is exited when the critical section nesting count reaches
\r
144 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
\r
146 /* In all GICs 255 can be written to the priority mask register to unmask all
\r
147 (but the lowest) interrupt priority. */
\r
148 #define portUNMASK_VALUE ( 0xFFUL )
\r
150 /* Tasks are not created with a floating point context, but can be given a
\r
151 floating point context after they have been created. A variable is stored as
\r
152 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
\r
153 does not have an FPU context, or any other value if the task does have an FPU
\r
155 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
\r
157 /* Interrupt controller access addresses. */
\r
158 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
\r
159 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
\r
160 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
\r
161 #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
\r
162 #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
\r
163 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
\r
164 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
\r
165 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
\r
166 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
\r
167 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
\r
168 #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
\r
169 #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
\r
171 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
\r
173 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
\r
175 /* Constants required to setup the initial task context. */
\r
176 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
\r
177 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
\r
178 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
\r
180 /* Masks all bits in the APSR other than the mode bits. */
\r
181 #define portAPSR_MODE_BITS_MASK ( 0x1F )
\r
183 /* The value of the mode bits in the APSR when the CPU is executing in user
\r
185 #define portAPSR_USER_MODE ( 0x10 )
\r
187 /* Macro to unmask all interrupt priorities. */
\r
188 #define portCLEAR_INTERRUPT_MASK() \
\r
191 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
\r
197 /*-----------------------------------------------------------*/
\r
200 * Starts the first task executing. This function is necessarily written in
\r
201 * assembly code so is implemented in portASM.s.
\r
203 extern void vPortRestoreTaskContext( void );
\r
206 * Used to catch tasks that attempt to return from their implementing function.
\r
208 static void prvTaskExitError( void );
\r
210 /*-----------------------------------------------------------*/
\r
212 /* A variable is used to keep track of the critical section nesting. This
\r
213 variable has to be stored as part of the task context and must be initialised to
\r
214 a non zero value to ensure interrupts don't inadvertently become unmasked before
\r
215 the scheduler starts. As it is stored as part of the task context it will
\r
216 automatically be set to 0 when the first task is started. */
\r
217 volatile uint32_t ulCriticalNesting = 9999UL;
\r
219 /* Used to pass constants into the ASM code. The address at which variables are
\r
220 placed is the constant value so indirect loads in the asm code are not
\r
222 uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
\r
223 uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
\r
224 uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
\r
225 uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
\r
227 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
\r
228 a floating point context must be saved and restored for the task. */
\r
229 uint32_t ulPortTaskHasFPUContext = pdFALSE;
\r
231 /* Set to 1 to pend a context switch from an ISR. */
\r
232 uint32_t ulPortYieldRequired = pdFALSE;
\r
234 /* Counts the interrupt nesting depth. A context switch is only performed if
\r
235 if the nesting depth is 0. */
\r
236 uint32_t ulPortInterruptNesting = 0UL;
\r
238 /*-----------------------------------------------------------*/
\r
241 * See header file for description.
\r
243 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
245 /* Setup the initial stack of the task. The stack is set exactly as
\r
246 expected by the portRESTORE_CONTEXT() macro.
\r
248 The fist real value on the stack is the status register, which is set for
\r
249 system mode, with interrupts enabled. A few NULLs are added first to ensure
\r
250 GDB does not try decoding a non-existent return address. */
\r
251 *pxTopOfStack = NULL;
\r
253 *pxTopOfStack = NULL;
\r
255 *pxTopOfStack = NULL;
\r
257 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
\r
259 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
\r
261 /* The task will start in THUMB mode. */
\r
262 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
267 /* Next the return address, which in this case is the start of the task. */
\r
268 *pxTopOfStack = ( StackType_t ) pxCode;
\r
271 /* Next all the registers other than the stack pointer. */
\r
272 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
\r
274 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
\r
276 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
\r
278 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
\r
280 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
\r
282 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
\r
284 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
\r
286 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
\r
288 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
\r
290 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
\r
292 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
\r
294 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
\r
296 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
\r
298 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
301 /* The task will start with a critical nesting count of 0 as interrupts are
\r
303 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
306 /* The task will start without a floating point context. A task that uses
\r
307 the floating point hardware must call vPortTaskUsesFPU() before executing
\r
308 any floating point instructions. */
\r
309 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
\r
311 return pxTopOfStack;
\r
313 /*-----------------------------------------------------------*/
\r
315 static void prvTaskExitError( void )
\r
317 /* A function that implements a task must not exit or attempt to return to
\r
318 its caller as there is nothing to return to. If a task wants to exit it
\r
319 should instead call vTaskDelete( NULL ).
\r
321 Artificially force an assert() to be triggered if configASSERT() is
\r
322 defined, then stop here so application writers can catch the error. */
\r
323 configASSERT( ulPortInterruptNesting == ~0UL );
\r
324 portDISABLE_INTERRUPTS();
\r
327 /*-----------------------------------------------------------*/
\r
329 BaseType_t xPortStartScheduler( void )
\r
333 /* Only continue if the CPU is not in User mode. The CPU must be in a
\r
334 Privileged mode for the scheduler to start. */
\r
335 __asm( "MRS ulAPSR, APSR" );
\r
336 ulAPSR &= portAPSR_MODE_BITS_MASK;
\r
337 configASSERT( ulAPSR != portAPSR_USER_MODE );
\r
339 if( ulAPSR != portAPSR_USER_MODE )
\r
341 /* Only continue if the binary point value is set to its lowest possible
\r
342 setting. See the comments in vPortValidateInterruptPriority() below for
\r
343 more information. */
\r
344 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
346 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
\r
348 /* Start the timer that generates the tick ISR. */
\r
349 configSETUP_TICK_INTERRUPT();
\r
352 vPortRestoreTaskContext();
\r
356 /* Will only get here if vTaskStartScheduler() was called with the CPU in
\r
357 a non-privileged mode or the binary point register was not set to its lowest
\r
361 /*-----------------------------------------------------------*/
\r
363 void vPortEndScheduler( void )
\r
365 /* Not implemented in ports where there is nothing to return to.
\r
366 Artificially force an assert. */
\r
367 configASSERT( ulCriticalNesting == 1000UL );
\r
369 /*-----------------------------------------------------------*/
\r
371 void vPortEnterCritical( void )
\r
373 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
\r
374 ulPortSetInterruptMask();
\r
376 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
377 directly. Increment ulCriticalNesting to keep a count of how many times
\r
378 portENTER_CRITICAL() has been called. */
\r
379 ulCriticalNesting++;
\r
381 /* This is not the interrupt safe version of the enter critical function so
\r
382 assert() if it is being called from an interrupt context. Only API
\r
383 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
384 the critical nesting count is 1 to protect against recursive calls if the
\r
385 assert function also uses a critical section. */
\r
386 if( ulCriticalNesting == 1 )
\r
388 configASSERT( ulPortInterruptNesting == 0 );
\r
391 /*-----------------------------------------------------------*/
\r
393 void vPortExitCritical( void )
\r
395 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
397 /* Decrement the nesting count as the critical section is being
\r
399 ulCriticalNesting--;
\r
401 /* If the nesting level has reached zero then all interrupt
\r
402 priorities must be re-enabled. */
\r
403 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
405 /* Critical nesting has reached zero so all interrupt priorities
\r
406 should be unmasked. */
\r
407 portCLEAR_INTERRUPT_MASK();
\r
411 /*-----------------------------------------------------------*/
\r
413 void FreeRTOS_Tick_Handler( void )
\r
415 /* Set interrupt mask before altering scheduler structures. The tick
\r
416 handler runs at the lowest priority, so interrupts cannot already be masked,
\r
417 so there is no need to save and restore the current mask value. */
\r
419 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
424 /* Increment the RTOS tick. */
\r
425 if( xTaskIncrementTick() != pdFALSE )
\r
427 ulPortYieldRequired = pdTRUE;
\r
430 /* Ensure all interrupt priorities are active again. */
\r
431 portCLEAR_INTERRUPT_MASK();
\r
432 configCLEAR_TICK_INTERRUPT();
\r
434 /*-----------------------------------------------------------*/
\r
436 void vPortTaskUsesFPU( void )
\r
438 uint32_t ulInitialFPSCR = 0;
\r
440 /* A task is registering the fact that it needs an FPU context. Set the
\r
441 FPU flag (which is saved as part of the task context). */
\r
442 ulPortTaskHasFPUContext = pdTRUE;
\r
444 /* Initialise the floating point status register. */
\r
445 __asm( "FMXR FPSCR, ulInitialFPSCR" );
\r
447 /*-----------------------------------------------------------*/
\r
449 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
\r
451 if( ulNewMaskValue == pdFALSE )
\r
453 portCLEAR_INTERRUPT_MASK();
\r
456 /*-----------------------------------------------------------*/
\r
458 uint32_t ulPortSetInterruptMask( void )
\r
463 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
\r
465 /* Interrupts were already masked. */
\r
470 ulReturn = pdFALSE;
\r
471 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
479 /*-----------------------------------------------------------*/
\r
481 #if( configASSERT_DEFINED == 1 )
\r
483 void vPortValidateInterruptPriority( void )
\r
485 /* The following assertion will fail if a service routine (ISR) for
\r
486 an interrupt that has been assigned a priority above
\r
487 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
488 function. ISR safe FreeRTOS API functions must *only* be called
\r
489 from interrupts that have been assigned a priority at or below
\r
490 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
492 Numerically low interrupt priority numbers represent logically high
\r
493 interrupt priorities, therefore the priority of the interrupt must
\r
494 be set to a value equal to or numerically *higher* than
\r
495 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
497 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
498 interrupt entry is as fast and simple as possible.
\r
500 The following links provide detailed information:
\r
501 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
502 http://www.freertos.org/FAQHelp.html */
\r
503 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
\r
505 /* Priority grouping: The interrupt controller (GIC) allows the bits
\r
506 that define each interrupt's priority to be split between bits that
\r
507 define the interrupt's pre-emption priority bits and bits that define
\r
508 the interrupt's sub-priority. For simplicity all bits must be defined
\r
509 to be pre-emption priority bits. The following assertion will fail if
\r
510 this is not the case (if some bits represent a sub-priority).
\r
512 The priority grouping is configured by the GIC's binary point register
\r
513 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
\r
514 possible value (which may be above 0). */
\r
515 configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
\r
518 #endif /* configASSERT_DEFINED */
\r