2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /* Standard includes. */
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31 /* Scheduler includes. */
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32 #include "FreeRTOS.h"
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35 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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36 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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39 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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40 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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43 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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44 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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47 #ifndef configSETUP_TICK_INTERRUPT
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48 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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49 #endif /* configSETUP_TICK_INTERRUPT */
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51 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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52 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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55 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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56 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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59 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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60 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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63 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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64 /* Check the configuration. */
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65 #if( configMAX_PRIORITIES > 32 )
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66 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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68 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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70 /* In case security extensions are implemented. */
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71 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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72 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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75 #ifndef configCLEAR_TICK_INTERRUPT
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76 #define configCLEAR_TICK_INTERRUPT()
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79 /* The number of bits to shift for an interrupt priority is dependent on the
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80 number of bits implemented by the interrupt controller. */
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81 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
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82 #define portPRIORITY_SHIFT 4
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83 #define portMAX_BINARY_POINT_VALUE 3
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84 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
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85 #define portPRIORITY_SHIFT 3
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86 #define portMAX_BINARY_POINT_VALUE 2
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87 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
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88 #define portPRIORITY_SHIFT 2
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89 #define portMAX_BINARY_POINT_VALUE 1
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90 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
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91 #define portPRIORITY_SHIFT 1
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92 #define portMAX_BINARY_POINT_VALUE 0
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93 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
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94 #define portPRIORITY_SHIFT 0
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95 #define portMAX_BINARY_POINT_VALUE 0
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97 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
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100 /* A critical section is exited when the critical section nesting count reaches
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102 #define portNO_CRITICAL_NESTING ( ( uint32_t ) 0 )
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104 /* In all GICs 255 can be written to the priority mask register to unmask all
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105 (but the lowest) interrupt priority. */
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106 #define portUNMASK_VALUE ( 0xFFUL )
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108 /* Tasks are not created with a floating point context, but can be given a
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109 floating point context after they have been created. A variable is stored as
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110 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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111 does not have an FPU context, or any other value if the task does have an FPU
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113 #define portNO_FLOATING_POINT_CONTEXT ( ( StackType_t ) 0 )
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115 /* Interrupt controller access addresses. */
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116 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
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117 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
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118 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
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119 #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
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120 #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
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121 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
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122 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
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123 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
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124 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
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125 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
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126 #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
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127 #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
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129 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
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131 #define portBINARY_POINT_BITS ( ( uint8_t ) 0x03 )
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133 /* Constants required to setup the initial task context. */
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134 #define portINITIAL_SPSR ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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135 #define portTHUMB_MODE_BIT ( ( StackType_t ) 0x20 )
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136 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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138 /* Masks all bits in the APSR other than the mode bits. */
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139 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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141 /* The value of the mode bits in the APSR when the CPU is executing in user
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143 #define portAPSR_USER_MODE ( 0x10 )
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145 /* Macro to unmask all interrupt priorities. */
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146 #define portCLEAR_INTERRUPT_MASK() \
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149 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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155 /*-----------------------------------------------------------*/
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158 * Starts the first task executing. This function is necessarily written in
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159 * assembly code so is implemented in portASM.s.
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161 extern void vPortRestoreTaskContext( void );
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164 * Used to catch tasks that attempt to return from their implementing function.
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166 static void prvTaskExitError( void );
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168 /*-----------------------------------------------------------*/
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170 /* A variable is used to keep track of the critical section nesting. This
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171 variable has to be stored as part of the task context and must be initialised to
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172 a non zero value to ensure interrupts don't inadvertently become unmasked before
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173 the scheduler starts. As it is stored as part of the task context it will
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174 automatically be set to 0 when the first task is started. */
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175 volatile uint32_t ulCriticalNesting = 9999UL;
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177 /* Used to pass constants into the ASM code. The address at which variables are
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178 placed is the constant value so indirect loads in the asm code are not
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180 uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
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181 uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
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182 uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
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183 uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
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185 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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186 a floating point context must be saved and restored for the task. */
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187 uint32_t ulPortTaskHasFPUContext = pdFALSE;
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189 /* Set to 1 to pend a context switch from an ISR. */
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190 uint32_t ulPortYieldRequired = pdFALSE;
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192 /* Counts the interrupt nesting depth. A context switch is only performed if
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193 if the nesting depth is 0. */
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194 uint32_t ulPortInterruptNesting = 0UL;
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196 /*-----------------------------------------------------------*/
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199 * See header file for description.
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201 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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203 /* Setup the initial stack of the task. The stack is set exactly as
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204 expected by the portRESTORE_CONTEXT() macro.
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206 The fist real value on the stack is the status register, which is set for
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207 system mode, with interrupts enabled. A few NULLs are added first to ensure
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208 GDB does not try decoding a non-existent return address. */
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209 *pxTopOfStack = NULL;
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211 *pxTopOfStack = NULL;
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213 *pxTopOfStack = NULL;
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215 *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
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217 if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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219 /* The task will start in THUMB mode. */
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220 *pxTopOfStack |= portTHUMB_MODE_BIT;
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225 /* Next the return address, which in this case is the start of the task. */
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226 *pxTopOfStack = ( StackType_t ) pxCode;
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229 /* Next all the registers other than the stack pointer. */
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230 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* R14 */
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232 *pxTopOfStack = ( StackType_t ) 0x12121212; /* R12 */
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234 *pxTopOfStack = ( StackType_t ) 0x11111111; /* R11 */
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236 *pxTopOfStack = ( StackType_t ) 0x10101010; /* R10 */
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238 *pxTopOfStack = ( StackType_t ) 0x09090909; /* R9 */
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240 *pxTopOfStack = ( StackType_t ) 0x08080808; /* R8 */
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242 *pxTopOfStack = ( StackType_t ) 0x07070707; /* R7 */
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244 *pxTopOfStack = ( StackType_t ) 0x06060606; /* R6 */
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246 *pxTopOfStack = ( StackType_t ) 0x05050505; /* R5 */
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248 *pxTopOfStack = ( StackType_t ) 0x04040404; /* R4 */
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250 *pxTopOfStack = ( StackType_t ) 0x03030303; /* R3 */
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252 *pxTopOfStack = ( StackType_t ) 0x02020202; /* R2 */
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254 *pxTopOfStack = ( StackType_t ) 0x01010101; /* R1 */
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256 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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259 /* The task will start with a critical nesting count of 0 as interrupts are
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261 *pxTopOfStack = portNO_CRITICAL_NESTING;
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264 /* The task will start without a floating point context. A task that uses
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265 the floating point hardware must call vPortTaskUsesFPU() before executing
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266 any floating point instructions. */
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267 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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269 return pxTopOfStack;
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271 /*-----------------------------------------------------------*/
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273 static void prvTaskExitError( void )
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275 /* A function that implements a task must not exit or attempt to return to
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276 its caller as there is nothing to return to. If a task wants to exit it
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277 should instead call vTaskDelete( NULL ).
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279 Artificially force an assert() to be triggered if configASSERT() is
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280 defined, then stop here so application writers can catch the error. */
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281 configASSERT( ulPortInterruptNesting == ~0UL );
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282 portDISABLE_INTERRUPTS();
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285 /*-----------------------------------------------------------*/
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287 BaseType_t xPortStartScheduler( void )
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291 /* Only continue if the CPU is not in User mode. The CPU must be in a
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292 Privileged mode for the scheduler to start. */
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293 __asm( "MRS ulAPSR, APSR" );
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294 ulAPSR &= portAPSR_MODE_BITS_MASK;
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295 configASSERT( ulAPSR != portAPSR_USER_MODE );
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297 if( ulAPSR != portAPSR_USER_MODE )
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299 /* Only continue if the binary point value is set to its lowest possible
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300 setting. See the comments in vPortValidateInterruptPriority() below for
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301 more information. */
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302 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
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304 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
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306 /* Start the timer that generates the tick ISR. */
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307 configSETUP_TICK_INTERRUPT();
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310 vPortRestoreTaskContext();
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314 /* Will only get here if vTaskStartScheduler() was called with the CPU in
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315 a non-privileged mode or the binary point register was not set to its lowest
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319 /*-----------------------------------------------------------*/
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321 void vPortEndScheduler( void )
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323 /* Not implemented in ports where there is nothing to return to.
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324 Artificially force an assert. */
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325 configASSERT( ulCriticalNesting == 1000UL );
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327 /*-----------------------------------------------------------*/
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329 void vPortEnterCritical( void )
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331 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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332 ulPortSetInterruptMask();
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334 /* Now interrupts are disabled ulCriticalNesting can be accessed
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335 directly. Increment ulCriticalNesting to keep a count of how many times
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336 portENTER_CRITICAL() has been called. */
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337 ulCriticalNesting++;
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339 /* This is not the interrupt safe version of the enter critical function so
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340 assert() if it is being called from an interrupt context. Only API
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341 functions that end in "FromISR" can be used in an interrupt. Only assert if
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342 the critical nesting count is 1 to protect against recursive calls if the
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343 assert function also uses a critical section. */
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344 if( ulCriticalNesting == 1 )
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346 configASSERT( ulPortInterruptNesting == 0 );
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349 /*-----------------------------------------------------------*/
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351 void vPortExitCritical( void )
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353 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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355 /* Decrement the nesting count as the critical section is being
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357 ulCriticalNesting--;
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359 /* If the nesting level has reached zero then all interrupt
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360 priorities must be re-enabled. */
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361 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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363 /* Critical nesting has reached zero so all interrupt priorities
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364 should be unmasked. */
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365 portCLEAR_INTERRUPT_MASK();
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369 /*-----------------------------------------------------------*/
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371 void FreeRTOS_Tick_Handler( void )
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373 /* Set interrupt mask before altering scheduler structures. The tick
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374 handler runs at the lowest priority, so interrupts cannot already be masked,
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375 so there is no need to save and restore the current mask value. */
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377 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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382 /* Increment the RTOS tick. */
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383 if( xTaskIncrementTick() != pdFALSE )
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385 ulPortYieldRequired = pdTRUE;
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388 /* Ensure all interrupt priorities are active again. */
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389 portCLEAR_INTERRUPT_MASK();
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390 configCLEAR_TICK_INTERRUPT();
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392 /*-----------------------------------------------------------*/
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394 void vPortTaskUsesFPU( void )
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396 uint32_t ulInitialFPSCR = 0;
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398 /* A task is registering the fact that it needs an FPU context. Set the
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399 FPU flag (which is saved as part of the task context). */
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400 ulPortTaskHasFPUContext = pdTRUE;
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402 /* Initialise the floating point status register. */
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403 __asm( "FMXR FPSCR, ulInitialFPSCR" );
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405 /*-----------------------------------------------------------*/
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407 void vPortClearInterruptMask( uint32_t ulNewMaskValue )
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409 if( ulNewMaskValue == pdFALSE )
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411 portCLEAR_INTERRUPT_MASK();
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414 /*-----------------------------------------------------------*/
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416 uint32_t ulPortSetInterruptMask( void )
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421 if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
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423 /* Interrupts were already masked. */
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428 ulReturn = pdFALSE;
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429 portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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437 /*-----------------------------------------------------------*/
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439 #if( configASSERT_DEFINED == 1 )
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441 void vPortValidateInterruptPriority( void )
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443 /* The following assertion will fail if a service routine (ISR) for
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444 an interrupt that has been assigned a priority above
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445 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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446 function. ISR safe FreeRTOS API functions must *only* be called
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447 from interrupts that have been assigned a priority at or below
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448 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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450 Numerically low interrupt priority numbers represent logically high
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451 interrupt priorities, therefore the priority of the interrupt must
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452 be set to a value equal to or numerically *higher* than
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453 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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455 FreeRTOS maintains separate thread and ISR API functions to ensure
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456 interrupt entry is as fast and simple as possible.
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458 The following links provide detailed information:
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459 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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460 http://www.freertos.org/FAQHelp.html */
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461 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
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463 /* Priority grouping: The interrupt controller (GIC) allows the bits
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464 that define each interrupt's priority to be split between bits that
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465 define the interrupt's pre-emption priority bits and bits that define
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466 the interrupt's sub-priority. For simplicity all bits must be defined
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467 to be pre-emption priority bits. The following assertion will fail if
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468 this is not the case (if some bits represent a sub-priority).
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470 The priority grouping is configured by the GIC's binary point register
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471 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
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472 possible value (which may be above 0). */
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473 configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
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476 #endif /* configASSERT_DEFINED */
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