2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* Standard includes. */
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78 /* Scheduler includes. */
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79 #include "FreeRTOS.h"
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82 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
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83 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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86 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
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87 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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90 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
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91 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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94 #ifndef configSETUP_TICK_INTERRUPT
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95 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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96 #endif /* configSETUP_TICK_INTERRUPT */
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98 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
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99 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
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102 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
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103 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
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106 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
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107 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
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110 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
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111 /* Check the configuration. */
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112 #if( configMAX_PRIORITIES > 32 )
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113 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
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115 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
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117 /* In case security extensions are implemented. */
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118 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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119 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
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122 /* The number of bits to shift for an interrupt priority is dependent on the
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123 number of bits implemented by the interrupt controller. */
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124 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
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125 #define portPRIORITY_SHIFT 4
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126 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
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127 #define portPRIORITY_SHIFT 3
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128 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
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129 #define portPRIORITY_SHIFT 2
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130 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
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131 #define portPRIORITY_SHIFT 1
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132 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
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133 #define portPRIORITY_SHIFT 0
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135 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
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138 /* A critical section is exited when the critical section nesting count reaches
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140 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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142 /* In all GICs 255 can be written to the priority mask register to unmask all
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143 (but the lowest) interrupt priority. */
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144 #define portUNMASK_VALUE ( 0xFF )
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146 /* Tasks are not created with a floating point context, but can be given a
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147 floating point context after they have been created. A variable is stored as
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148 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
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149 does not have an FPU context, or any other value if the task does have an FPU
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151 #define portNO_FLOATING_POINT_CONTEXT ( ( portSTACK_TYPE ) 0 )
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153 /* Interrupt controller access addresses. */
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154 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
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155 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
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156 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
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157 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
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158 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
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159 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
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160 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
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161 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
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163 /* Constants required to setup the initial task context. */
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164 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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165 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
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166 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
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167 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
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169 /* Masks all bits in the APSR other than the mode bits. */
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170 #define portAPSR_MODE_BITS_MASK ( 0x1F )
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172 /* The value of the mode bits in the APSR when the CPU is executing in user
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174 #define portAPSR_USER_MODE ( 0x10 )
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176 /* Macro to unmask all interrupt priorities. */
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177 #define portCLEAR_INTERRUPT_MASK() \
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180 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
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186 /*-----------------------------------------------------------*/
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189 * Starts the first task executing. This function is necessarily written in
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190 * assembly code so is implemented in portASM.s.
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192 extern void vPortRestoreTaskContext( void );
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194 /*-----------------------------------------------------------*/
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196 /* A variable is used to keep track of the critical section nesting. This
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197 variable has to be stored as part of the task context and must be initialised to
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198 a non zero value to ensure interrupts don't inadvertently become unmasked before
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199 the scheduler starts. As it is stored as part of the task context it will
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200 automatically be set to 0 when the first task is started. */
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201 volatile unsigned long ulCriticalNesting = 9999UL;
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203 /* The value to be written to the interrupt controllers priority mask register
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204 to mask interrupts that can use the FreeRTOS API without masking higher priority
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206 const unsigned long ulPortAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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208 /* Used to pass constants into the ASM code. The address at which variables are
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209 placed is the constant value so indirect loads in the asm code are not
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211 unsigned long ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
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212 unsigned long ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
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213 unsigned long ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
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214 unsigned long ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
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216 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
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217 a floating point context must be saved and restored for the task. */
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218 unsigned long ulPortTaskHasFPUContext = pdFALSE;
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220 /* Set to 1 to pend a context switch from an ISR. */
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221 unsigned long ulPortYieldRequired = pdFALSE;
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223 /* Counts the interrupt nesting depth. A context switch is only performed if
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224 if the nesting depth is 0. */
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225 unsigned long ulPortInterruptNesting = 0UL;
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227 /*-----------------------------------------------------------*/
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230 * See header file for description.
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232 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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234 /* Setup the initial stack of the task. The stack is set exactly as
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235 expected by the portRESTORE_CONTEXT() macro.
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237 The fist real value on the stack is the status register, which is set for
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238 system mode, with interrupts enabled. A few NULLs are added first to ensure
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239 GDB does not try decoding a non-existent return address. */
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240 *pxTopOfStack = NULL;
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242 *pxTopOfStack = NULL;
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244 *pxTopOfStack = NULL;
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246 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
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248 if( ( ( unsigned long ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
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250 /* The task will start in THUMB mode. */
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251 *pxTopOfStack |= portTHUMB_MODE_BIT;
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256 /* Next the return address, which in this case is the start of the task. */
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257 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
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260 /* Next all the registers other than the stack pointer. */
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261 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
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263 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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265 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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267 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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269 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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271 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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273 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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275 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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277 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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279 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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281 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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283 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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285 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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287 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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290 /* The task will start with a critical nesting count of 0 as interrupts are
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292 *pxTopOfStack = portNO_CRITICAL_NESTING;
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295 /* The task will start without a floating point context. A task that uses
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296 the floating point hardware must call vPortTaskUsesFPU() before executing
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297 any floating point instructions. */
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298 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
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300 return pxTopOfStack;
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302 /*-----------------------------------------------------------*/
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304 portBASE_TYPE xPortStartScheduler( void )
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306 unsigned long ulAPSR;
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308 /* Only continue if the CPU is not in User mode. The CPU must be in a
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309 Privileged mode for the scheduler to start. */
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310 __asm( "MRS ulAPSR, APSR" );
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311 ulAPSR &= portAPSR_MODE_BITS_MASK;
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312 configASSERT( ulAPSR != portAPSR_USER_MODE );
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314 if( ulAPSR != portAPSR_USER_MODE )
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316 /* Start the timer that generates the tick ISR. */
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317 configSETUP_TICK_INTERRUPT();
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320 vPortRestoreTaskContext();
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323 /* Will only get here if xTaskStartScheduler() was called with the CPU in
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324 a non-privileged mode. */
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327 /*-----------------------------------------------------------*/
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329 void vPortEndScheduler( void )
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331 /* It is unlikely that the ARM port will require this function as there
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332 is nothing to return to. */
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334 /*-----------------------------------------------------------*/
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336 void vPortEnterCritical( void )
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338 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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339 ulPortSetInterruptMask();
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341 /* Now interrupts are disabled ulCriticalNesting can be accessed
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342 directly. Increment ulCriticalNesting to keep a count of how many times
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343 portENTER_CRITICAL() has been called. */
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344 ulCriticalNesting++;
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346 /*-----------------------------------------------------------*/
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348 void vPortExitCritical( void )
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350 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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352 /* Decrement the nesting count as the critical section is being
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354 ulCriticalNesting--;
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356 /* If the nesting level has reached zero then all interrupt
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357 priorities must be re-enabled. */
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358 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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360 /* Critical nesting has reached zero so all interrupt priorities
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361 should be unmasked. */
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362 portCLEAR_INTERRUPT_MASK();
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366 /*-----------------------------------------------------------*/
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368 void FreeRTOS_Tick_Handler( void )
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370 /* Set interrupt mask before altering scheduler structures. The tick
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371 handler runs at the lowest priority, so interrupts cannot already be masked,
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372 so there is no need to save and restore the current mask value. */
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374 portICCPMR_PRIORITY_MASK_REGISTER = ulPortAPIPriorityMask;
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379 /* Increment the RTOS tick. */
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380 if( xTaskIncrementTick() != pdFALSE )
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382 ulPortYieldRequired = pdTRUE;
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385 /* Ensure all interrupt priorities are active again. */
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386 portCLEAR_INTERRUPT_MASK();
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388 /*-----------------------------------------------------------*/
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390 void vPortTaskUsesFPU( void )
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392 unsigned long ulInitialFPSCR = 0;
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394 /* A task is registering the fact that it needs an FPU context. Set the
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395 FPU flag (which is saved as part of the task context). */
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396 ulPortTaskHasFPUContext = pdTRUE;
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398 /* Initialise the floating point status register. */
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399 __asm( "FMXR FPSCR, ulInitialFPSCR" );
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401 /*-----------------------------------------------------------*/
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403 void vPortClearInterruptMask( unsigned long ulNewMaskValue )
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405 if( ulNewMaskValue == pdFALSE )
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407 portCLEAR_INTERRUPT_MASK();
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410 /*-----------------------------------------------------------*/
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412 unsigned long ulPortSetInterruptMask( void )
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414 unsigned long ulReturn;
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417 if( portICCPMR_PRIORITY_MASK_REGISTER == ulPortAPIPriorityMask )
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419 /* Interrupts were already masked. */
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424 ulReturn = pdFALSE;
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425 portICCPMR_PRIORITY_MASK_REGISTER = ulPortAPIPriorityMask;
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