2 FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS provides completely free yet professionally developed, *
\r
10 * robust, strictly quality controlled, supported, and cross *
\r
11 * platform software that has become a de facto standard. *
\r
13 * Help yourself get started quickly and support the FreeRTOS *
\r
14 * project by purchasing a FreeRTOS tutorial book, reference *
\r
15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
19 ***************************************************************************
\r
21 This file is part of the FreeRTOS distribution.
\r
23 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
24 the terms of the GNU General Public License (version 2) as published by the
\r
25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
27 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
28 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
29 >>! the source code for proprietary components outside of the FreeRTOS
\r
32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
35 link: http://www.freertos.org/a00114.html
\r
39 ***************************************************************************
\r
41 * Having a problem? Start by reading the FAQ "My application does *
\r
42 * not run, what could be wrong?" *
\r
44 * http://www.FreeRTOS.org/FAQHelp.html *
\r
46 ***************************************************************************
\r
48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
49 license and Real Time Engineers Ltd. contact details.
\r
51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
57 licenses offer ticketed support, indemnification and middleware.
\r
59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
60 engineered and independently SIL3 certified version for use in safety and
\r
61 mission critical applications that require provable dependability.
\r
66 /* Standard includes. */
\r
69 /* Scheduler includes. */
\r
70 #include "FreeRTOS.h"
\r
73 #ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
\r
74 #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
77 #ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
\r
78 #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
81 #ifndef configUNIQUE_INTERRUPT_PRIORITIES
\r
82 #error configUNIQUE_INTERRUPT_PRIORITIES must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
85 #ifndef configSETUP_TICK_INTERRUPT
\r
86 #error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
87 #endif /* configSETUP_TICK_INTERRUPT */
\r
89 #ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
\r
90 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
\r
93 #if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
\r
94 #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
\r
97 #if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
\r
98 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
\r
101 #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
\r
102 /* Check the configuration. */
\r
103 #if( configMAX_PRIORITIES > 32 )
\r
104 #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
\r
106 #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
\r
108 /* In case security extensions are implemented. */
\r
109 #if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
110 #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
\r
113 /* The number of bits to shift for an interrupt priority is dependent on the
\r
114 number of bits implemented by the interrupt controller. */
\r
115 #if configUNIQUE_INTERRUPT_PRIORITIES == 16
\r
116 #define portPRIORITY_SHIFT 4
\r
117 #define portMAX_BINARY_POINT_VALUE 3
\r
118 #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
\r
119 #define portPRIORITY_SHIFT 3
\r
120 #define portMAX_BINARY_POINT_VALUE 2
\r
121 #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
\r
122 #define portPRIORITY_SHIFT 2
\r
123 #define portMAX_BINARY_POINT_VALUE 1
\r
124 #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
\r
125 #define portPRIORITY_SHIFT 1
\r
126 #define portMAX_BINARY_POINT_VALUE 0
\r
127 #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
\r
128 #define portPRIORITY_SHIFT 0
\r
129 #define portMAX_BINARY_POINT_VALUE 0
\r
131 #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting. configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
\r
134 /* A critical section is exited when the critical section nesting count reaches
\r
136 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
138 /* In all GICs 255 can be written to the priority mask register to unmask all
\r
139 (but the lowest) interrupt priority. */
\r
140 #define portUNMASK_VALUE ( 0xFF )
\r
142 /* Tasks are not created with a floating point context, but can be given a
\r
143 floating point context after they have been created. A variable is stored as
\r
144 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
\r
145 does not have an FPU context, or any other value if the task does have an FPU
\r
147 #define portNO_FLOATING_POINT_CONTEXT ( ( portSTACK_TYPE ) 0 )
\r
149 /* Interrupt controller access addresses. */
\r
150 #define portICCPMR_PRIORITY_MASK_OFFSET ( 0x04 )
\r
151 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
\r
152 #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
\r
153 #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
\r
154 #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
\r
155 #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
\r
156 #define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
\r
157 #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
\r
158 #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
\r
159 #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
\r
160 #define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile unsigned long * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
\r
161 #define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile unsigned char * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
\r
163 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
\r
165 #define portBINARY_POINT_BITS ( ( unsigned char ) 0x03 )
\r
167 /* Constants required to setup the initial task context. */
\r
168 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
\r
169 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
\r
170 #define portINTERRUPT_ENABLE_BIT ( 0x80UL )
\r
171 #define portTHUMB_MODE_ADDRESS ( 0x01UL )
\r
173 /* Masks all bits in the APSR other than the mode bits. */
\r
174 #define portAPSR_MODE_BITS_MASK ( 0x1F )
\r
176 /* The value of the mode bits in the APSR when the CPU is executing in user
\r
178 #define portAPSR_USER_MODE ( 0x10 )
\r
180 /* Macro to unmask all interrupt priorities. */
\r
181 #define portCLEAR_INTERRUPT_MASK() \
\r
184 portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
\r
190 /*-----------------------------------------------------------*/
\r
193 * Starts the first task executing. This function is necessarily written in
\r
194 * assembly code so is implemented in portASM.s.
\r
196 extern void vPortRestoreTaskContext( void );
\r
198 /*-----------------------------------------------------------*/
\r
200 /* A variable is used to keep track of the critical section nesting. This
\r
201 variable has to be stored as part of the task context and must be initialised to
\r
202 a non zero value to ensure interrupts don't inadvertently become unmasked before
\r
203 the scheduler starts. As it is stored as part of the task context it will
\r
204 automatically be set to 0 when the first task is started. */
\r
205 volatile unsigned long ulCriticalNesting = 9999UL;
\r
207 /* Used to pass constants into the ASM code. The address at which variables are
\r
208 placed is the constant value so indirect loads in the asm code are not
\r
210 unsigned long ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
\r
211 unsigned long ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
\r
212 unsigned long ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
\r
213 unsigned long ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
\r
215 /* Saved as part of the task context. If ulPortTaskHasFPUContext is non-zero then
\r
216 a floating point context must be saved and restored for the task. */
\r
217 unsigned long ulPortTaskHasFPUContext = pdFALSE;
\r
219 /* Set to 1 to pend a context switch from an ISR. */
\r
220 unsigned long ulPortYieldRequired = pdFALSE;
\r
222 /* Counts the interrupt nesting depth. A context switch is only performed if
\r
223 if the nesting depth is 0. */
\r
224 unsigned long ulPortInterruptNesting = 0UL;
\r
226 /*-----------------------------------------------------------*/
\r
229 * See header file for description.
\r
231 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
233 /* Setup the initial stack of the task. The stack is set exactly as
\r
234 expected by the portRESTORE_CONTEXT() macro.
\r
236 The fist real value on the stack is the status register, which is set for
\r
237 system mode, with interrupts enabled. A few NULLs are added first to ensure
\r
238 GDB does not try decoding a non-existent return address. */
\r
239 *pxTopOfStack = NULL;
\r
241 *pxTopOfStack = NULL;
\r
243 *pxTopOfStack = NULL;
\r
245 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
247 if( ( ( unsigned long ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
\r
249 /* The task will start in THUMB mode. */
\r
250 *pxTopOfStack |= portTHUMB_MODE_BIT;
\r
255 /* Next the return address, which in this case is the start of the task. */
\r
256 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
\r
259 /* Next all the registers other than the stack pointer. */
\r
260 *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000; /* R14 */
\r
262 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
264 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
266 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
268 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
270 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
272 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
274 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
276 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
278 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
280 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
282 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
284 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
286 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
289 /* The task will start with a critical nesting count of 0 as interrupts are
\r
291 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
294 /* The task will start without a floating point context. A task that uses
\r
295 the floating point hardware must call vPortTaskUsesFPU() before executing
\r
296 any floating point instructions. */
\r
297 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
\r
299 return pxTopOfStack;
\r
301 /*-----------------------------------------------------------*/
\r
303 portBASE_TYPE xPortStartScheduler( void )
\r
305 unsigned long ulAPSR;
\r
307 /* Only continue if the CPU is not in User mode. The CPU must be in a
\r
308 Privileged mode for the scheduler to start. */
\r
309 __asm( "MRS ulAPSR, APSR" );
\r
310 ulAPSR &= portAPSR_MODE_BITS_MASK;
\r
311 configASSERT( ulAPSR != portAPSR_USER_MODE );
\r
313 if( ulAPSR != portAPSR_USER_MODE )
\r
315 /* Only continue if the binary point value is set to its lowest possible
\r
316 setting. See the comments in vPortValidateInterruptPriority() below for
\r
317 more information. */
\r
318 configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
\r
320 if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
\r
322 /* Start the timer that generates the tick ISR. */
\r
323 configSETUP_TICK_INTERRUPT();
\r
326 vPortRestoreTaskContext();
\r
330 /* Will only get here if xTaskStartScheduler() was called with the CPU in
\r
331 a non-privileged mode or the binary point register was not set to its lowest
\r
335 /*-----------------------------------------------------------*/
\r
337 void vPortEndScheduler( void )
\r
339 /* Not implemented in ports where there is nothing to return to.
\r
340 Artificially force an assert. */
\r
341 configASSERT( ulCriticalNesting == 1000UL );
\r
343 /*-----------------------------------------------------------*/
\r
345 void vPortEnterCritical( void )
\r
347 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
\r
348 ulPortSetInterruptMask();
\r
350 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
351 directly. Increment ulCriticalNesting to keep a count of how many times
\r
352 portENTER_CRITICAL() has been called. */
\r
353 ulCriticalNesting++;
\r
355 /*-----------------------------------------------------------*/
\r
357 void vPortExitCritical( void )
\r
359 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
361 /* Decrement the nesting count as the critical section is being
\r
363 ulCriticalNesting--;
\r
365 /* If the nesting level has reached zero then all interrupt
\r
366 priorities must be re-enabled. */
\r
367 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
369 /* Critical nesting has reached zero so all interrupt priorities
\r
370 should be unmasked. */
\r
371 portCLEAR_INTERRUPT_MASK();
\r
375 /*-----------------------------------------------------------*/
\r
377 void FreeRTOS_Tick_Handler( void )
\r
379 /* Set interrupt mask before altering scheduler structures. The tick
\r
380 handler runs at the lowest priority, so interrupts cannot already be masked,
\r
381 so there is no need to save and restore the current mask value. */
\r
383 portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
388 /* Increment the RTOS tick. */
\r
389 if( xTaskIncrementTick() != pdFALSE )
\r
391 ulPortYieldRequired = pdTRUE;
\r
394 /* Ensure all interrupt priorities are active again. */
\r
395 portCLEAR_INTERRUPT_MASK();
\r
397 /*-----------------------------------------------------------*/
\r
399 void vPortTaskUsesFPU( void )
\r
401 unsigned long ulInitialFPSCR = 0;
\r
403 /* A task is registering the fact that it needs an FPU context. Set the
\r
404 FPU flag (which is saved as part of the task context). */
\r
405 ulPortTaskHasFPUContext = pdTRUE;
\r
407 /* Initialise the floating point status register. */
\r
408 __asm( "FMXR FPSCR, ulInitialFPSCR" );
\r
410 /*-----------------------------------------------------------*/
\r
412 void vPortClearInterruptMask( unsigned long ulNewMaskValue )
\r
414 if( ulNewMaskValue == pdFALSE )
\r
416 portCLEAR_INTERRUPT_MASK();
\r
419 /*-----------------------------------------------------------*/
\r
421 unsigned long ulPortSetInterruptMask( void )
\r
423 unsigned long ulReturn;
\r
426 if( portICCPMR_PRIORITY_MASK_REGISTER == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
\r
428 /* Interrupts were already masked. */
\r
433 ulReturn = pdFALSE;
\r
434 portICCPMR_PRIORITY_MASK_REGISTER = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
\r
442 /*-----------------------------------------------------------*/
\r
444 #if( configASSERT_DEFINED == 1 )
\r
446 void vPortValidateInterruptPriority( void )
\r
448 /* The following assertion will fail if a service routine (ISR) for
\r
449 an interrupt that has been assigned a priority above
\r
450 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
451 function. ISR safe FreeRTOS API functions must *only* be called
\r
452 from interrupts that have been assigned a priority at or below
\r
453 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
455 Numerically low interrupt priority numbers represent logically high
\r
456 interrupt priorities, therefore the priority of the interrupt must
\r
457 be set to a value equal to or numerically *higher* than
\r
458 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
460 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
461 interrupt entry is as fast and simple as possible.
\r
463 The following links provide detailed information:
\r
464 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
465 http://www.freertos.org/FAQHelp.html */
\r
466 configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
\r
468 /* Priority grouping: The interrupt controller (GIC) allows the bits
\r
469 that define each interrupt's priority to be split between bits that
\r
470 define the interrupt's pre-emption priority bits and bits that define
\r
471 the interrupt's sub-priority. For simplicity all bits must be defined
\r
472 to be pre-emption priority bits. The following assertion will fail if
\r
473 this is not the case (if some bits represent a sub-priority).
\r
475 The priority grouping is configured by the GIC's binary point register
\r
476 (ICCBPR). Writting 0 to ICCBPR will ensure it is set to its lowest
\r
477 possible value (which may be above 0). */
\r
478 configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
\r
481 #endif /* configASSERT_DEFINED */
\r