2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /*-----------------------------------------------------------
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66 * Implementation of functions defined in portable.h for the ARM CM0 port.
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67 *----------------------------------------------------------*/
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69 /* Scheduler includes. */
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70 #include "FreeRTOS.h"
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73 /* Constants required to manipulate the NVIC. */
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74 #define portNVIC_SYSTICK_CTRL ( ( volatile unsigned long *) 0xe000e010 )
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75 #define portNVIC_SYSTICK_LOAD ( ( volatile unsigned long *) 0xe000e014 )
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76 #define portNVIC_INT_CTRL ( ( volatile unsigned long *) 0xe000ed04 )
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77 #define portNVIC_SYSPRI2 ( ( volatile unsigned long *) 0xe000ed20 )
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78 #define portNVIC_SYSTICK_CLK 0x00000004
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79 #define portNVIC_SYSTICK_INT 0x00000002
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80 #define portNVIC_SYSTICK_ENABLE 0x00000001
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81 #define portNVIC_PENDSVSET 0x10000000
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82 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
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83 #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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84 #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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86 /* Constants required to set up the initial stack. */
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87 #define portINITIAL_XPSR ( 0x01000000 )
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89 /* Constants used with memory barrier intrinsics. */
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90 #define portSY_FULL_READ_WRITE ( 15 )
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92 /* Each task maintains its own interrupt status in the critical nesting
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94 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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97 * Setup the timer to generate the tick interrupts.
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99 static void prvSetupTimerInterrupt( void );
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102 * Exception handlers.
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104 void xPortPendSVHandler( void );
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105 void xPortSysTickHandler( void );
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106 void vPortSVCHandler( void );
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109 * Start first task is a separate function so it can be tested in isolation.
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111 static void prvPortStartFirstTask( void );
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113 /*-----------------------------------------------------------*/
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116 * See header file for description.
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118 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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120 /* Simulate the stack frame as it would be created by a context switch
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122 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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123 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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125 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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126 pxTopOfStack -= 6; /* LR, R12, R3..R1 */
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127 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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128 pxTopOfStack -= 8; /* R11..R4. */
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130 return pxTopOfStack;
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132 /*-----------------------------------------------------------*/
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134 __asm void vPortSVCHandler( void )
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136 extern pxCurrentTCB;
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140 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
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142 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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143 adds r0, #16 /* Pop the high registers. */
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144 ldmia r0!, {r4-r7}
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150 msr psp, r0 /* Remember the new top of stack for the task. */
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152 subs r0, #32 /* Go back for the low registers that are not automatically restored. */
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153 ldmia r0!, {r4-r7} /* Pop low registers. */
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154 mov r1, r14 /* OR R14 with 0x0d. */
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160 /*-----------------------------------------------------------*/
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162 __asm void prvPortStartFirstTask( void )
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166 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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167 table offset register that can be used to locate the initial stack value.
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168 Not all M0 parts have the application vector table at address 0. */
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169 cpsie i /* Globally enable interrupts. */
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170 svc 0 /* System call to start first task. */
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173 /*-----------------------------------------------------------*/
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176 * See header file for description.
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178 portBASE_TYPE xPortStartScheduler( void )
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180 /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
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181 *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
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182 *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
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184 /* Start the timer that generates the tick ISR. Interrupts are disabled
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186 prvSetupTimerInterrupt();
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188 /* Initialise the critical nesting count ready for the first task. */
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189 uxCriticalNesting = 0;
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191 /* Start the first task. */
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192 prvPortStartFirstTask();
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194 /* Should not get here! */
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197 /*-----------------------------------------------------------*/
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199 void vPortEndScheduler( void )
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201 /* It is unlikely that the CM0 port will require this function as there
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202 is nothing to return to. */
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204 /*-----------------------------------------------------------*/
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206 void vPortYield( void )
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208 /* Set a PendSV to request a context switch. */
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209 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
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211 /* Barriers are normally not required but do ensure the code is completely
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212 within the specified behaviour for the architecture. */
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213 __dsb( portSY_FULL_READ_WRITE );
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214 __isb( portSY_FULL_READ_WRITE );
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216 /*-----------------------------------------------------------*/
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218 void vPortEnterCritical( void )
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220 portDISABLE_INTERRUPTS();
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221 uxCriticalNesting++;
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222 __dsb( portSY_FULL_READ_WRITE );
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223 __isb( portSY_FULL_READ_WRITE );
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225 /*-----------------------------------------------------------*/
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227 void vPortExitCritical( void )
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229 uxCriticalNesting--;
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230 if( uxCriticalNesting == 0 )
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232 portENABLE_INTERRUPTS();
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235 /*-----------------------------------------------------------*/
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237 __asm unsigned long ulSetInterruptMaskFromISR( void )
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243 /*-----------------------------------------------------------*/
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245 __asm void vClearInterruptMaskFromISR( unsigned long ulMask )
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250 /*-----------------------------------------------------------*/
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252 __asm void xPortPendSVHandler( void )
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254 extern vTaskSwitchContext
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255 extern pxCurrentTCB
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261 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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264 subs r0, #32 /* Make space for the remaining low registers. */
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265 str r0, [r2] /* Save the new top of stack. */
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266 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
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267 mov r4, r8 /* Store the high registers. */
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275 bl vTaskSwitchContext
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277 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
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280 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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281 adds r0, #16 /* Move to the high registers. */
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282 ldmia r0!, {r4-r7} /* Pop the high registers. */
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288 msr psp, r0 /* Remember the new top of stack for the task. */
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290 subs r0, #32 /* Go back for the low registers that are not automatically restored. */
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291 ldmia r0!, {r4-r7} /* Pop low registers. */
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296 /*-----------------------------------------------------------*/
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298 void xPortSysTickHandler( void )
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300 unsigned long ulPreviousMask;
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302 ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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304 /* Increment the RTOS tick. */
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305 if( xTaskIncrementTick() != pdFALSE )
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307 /* Pend a context switch. */
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308 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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311 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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313 /*-----------------------------------------------------------*/
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316 * Setup the systick timer to generate the tick interrupts at the required
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319 void prvSetupTimerInterrupt( void )
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321 /* Configure SysTick to interrupt at the requested rate. */
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322 *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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323 *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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325 /*-----------------------------------------------------------*/
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