2 FreeRTOS V8.1.0 - Copyright (C) 2014 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 ***************************************************************************
\r
9 * FreeRTOS provides completely free yet professionally developed, *
\r
10 * robust, strictly quality controlled, supported, and cross *
\r
11 * platform software that has become a de facto standard. *
\r
13 * Help yourself get started quickly and support the FreeRTOS *
\r
14 * project by purchasing a FreeRTOS tutorial book, reference *
\r
15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
19 ***************************************************************************
\r
21 This file is part of the FreeRTOS distribution.
\r
23 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
24 the terms of the GNU General Public License (version 2) as published by the
\r
25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
27 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
28 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
29 >>! obliged to provide the source code for proprietary components !<<
\r
30 >>! outside of the FreeRTOS kernel. !<<
\r
32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
35 link: http://www.freertos.org/a00114.html
\r
39 ***************************************************************************
\r
41 * Having a problem? Start by reading the FAQ "My application does *
\r
42 * not run, what could be wrong?" *
\r
44 * http://www.FreeRTOS.org/FAQHelp.html *
\r
46 ***************************************************************************
\r
48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
49 license and Real Time Engineers Ltd. contact details.
\r
51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
57 licenses offer ticketed support, indemnification and middleware.
\r
59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
60 engineered and independently SIL3 certified version for use in safety and
\r
61 mission critical applications that require provable dependability.
\r
66 /*-----------------------------------------------------------
\r
67 * Implementation of functions defined in portable.h for the ARM CM0 port.
\r
68 *----------------------------------------------------------*/
\r
70 /* Scheduler includes. */
\r
71 #include "FreeRTOS.h"
\r
74 /* Constants required to manipulate the NVIC. */
\r
75 #define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t *) 0xe000e010 )
\r
76 #define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t *) 0xe000e014 )
\r
77 #define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
\r
78 #define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )
\r
79 #define portNVIC_SYSTICK_CLK 0x00000004
\r
80 #define portNVIC_SYSTICK_INT 0x00000002
\r
81 #define portNVIC_SYSTICK_ENABLE 0x00000001
\r
82 #define portNVIC_PENDSVSET 0x10000000
\r
83 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
\r
84 #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
\r
85 #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
\r
87 /* Constants required to set up the initial stack. */
\r
88 #define portINITIAL_XPSR ( 0x01000000 )
\r
90 /* Constants used with memory barrier intrinsics. */
\r
91 #define portSY_FULL_READ_WRITE ( 15 )
\r
93 /* Each task maintains its own interrupt status in the critical nesting
\r
95 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
98 * Setup the timer to generate the tick interrupts.
\r
100 static void prvSetupTimerInterrupt( void );
\r
103 * Exception handlers.
\r
105 void xPortPendSVHandler( void );
\r
106 void xPortSysTickHandler( void );
\r
107 void vPortSVCHandler( void );
\r
110 * Start first task is a separate function so it can be tested in isolation.
\r
112 static void prvPortStartFirstTask( void );
\r
115 * Used to catch tasks that attempt to return from their implementing function.
\r
117 static void prvTaskExitError( void );
\r
119 /*-----------------------------------------------------------*/
\r
122 * See header file for description.
\r
124 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
126 /* Simulate the stack frame as it would be created by a context switch
\r
128 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
129 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
131 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
133 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
\r
134 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
135 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
136 pxTopOfStack -= 8; /* R11..R4. */
\r
138 return pxTopOfStack;
\r
140 /*-----------------------------------------------------------*/
\r
142 static void prvTaskExitError( void )
\r
144 /* A function that implements a task must not exit or attempt to return to
\r
145 its caller as there is nothing to return to. If a task wants to exit it
\r
146 should instead call vTaskDelete( NULL ).
\r
148 Artificially force an assert() to be triggered if configASSERT() is
\r
149 defined, then stop here so application writers can catch the error. */
\r
150 configASSERT( uxCriticalNesting == ~0UL );
\r
151 portDISABLE_INTERRUPTS();
\r
154 /*-----------------------------------------------------------*/
\r
156 void vPortSVCHandler( void )
\r
158 /* This function is no longer used, but retained for backward
\r
161 /*-----------------------------------------------------------*/
\r
163 __asm void prvPortStartFirstTask( void )
\r
165 extern pxCurrentTCB;
\r
169 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
\r
170 table offset register that can be used to locate the initial stack value.
\r
171 Not all M0 parts have the application vector table at address 0. */
\r
173 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
\r
175 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
176 adds r0, #32 /* Discard everything up to r0. */
\r
177 msr psp, r0 /* This is now the new top of stack to use in the task. */
\r
178 movs r0, #2 /* Switch to the psp stack. */
\r
180 pop {r0-r5} /* Pop the registers that are saved automatically. */
\r
181 mov lr, r5 /* lr is now in r5. */
\r
182 cpsie i /* The first task has its context and interrupts can be enabled. */
\r
183 pop {pc} /* Finally, pop the PC to jump to the user defined task code. */
\r
187 /*-----------------------------------------------------------*/
\r
190 * See header file for description.
\r
192 BaseType_t xPortStartScheduler( void )
\r
194 /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
\r
195 *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
\r
196 *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
\r
198 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
200 prvSetupTimerInterrupt();
\r
202 /* Initialise the critical nesting count ready for the first task. */
\r
203 uxCriticalNesting = 0;
\r
205 /* Start the first task. */
\r
206 prvPortStartFirstTask();
\r
208 /* Should not get here! */
\r
211 /*-----------------------------------------------------------*/
\r
213 void vPortEndScheduler( void )
\r
215 /* Not implemented in ports where there is nothing to return to.
\r
216 Artificially force an assert. */
\r
217 configASSERT( uxCriticalNesting == 1000UL );
\r
219 /*-----------------------------------------------------------*/
\r
221 void vPortYield( void )
\r
223 /* Set a PendSV to request a context switch. */
\r
224 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
\r
226 /* Barriers are normally not required but do ensure the code is completely
\r
227 within the specified behaviour for the architecture. */
\r
228 __dsb( portSY_FULL_READ_WRITE );
\r
229 __isb( portSY_FULL_READ_WRITE );
\r
231 /*-----------------------------------------------------------*/
\r
233 void vPortEnterCritical( void )
\r
235 portDISABLE_INTERRUPTS();
\r
236 uxCriticalNesting++;
\r
237 __dsb( portSY_FULL_READ_WRITE );
\r
238 __isb( portSY_FULL_READ_WRITE );
\r
240 /*-----------------------------------------------------------*/
\r
242 void vPortExitCritical( void )
\r
244 configASSERT( uxCriticalNesting );
\r
245 uxCriticalNesting--;
\r
246 if( uxCriticalNesting == 0 )
\r
248 portENABLE_INTERRUPTS();
\r
251 /*-----------------------------------------------------------*/
\r
253 __asm uint32_t ulSetInterruptMaskFromISR( void )
\r
259 /*-----------------------------------------------------------*/
\r
261 __asm void vClearInterruptMaskFromISR( uint32_t ulMask )
\r
266 /*-----------------------------------------------------------*/
\r
268 __asm void xPortPendSVHandler( void )
\r
270 extern vTaskSwitchContext
\r
271 extern pxCurrentTCB
\r
277 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
\r
280 subs r0, #32 /* Make space for the remaining low registers. */
\r
281 str r0, [r2] /* Save the new top of stack. */
\r
282 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
\r
283 mov r4, r8 /* Store the high registers. */
\r
291 bl vTaskSwitchContext
\r
293 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
\r
296 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
297 adds r0, #16 /* Move to the high registers. */
\r
298 ldmia r0!, {r4-r7} /* Pop the high registers. */
\r
304 msr psp, r0 /* Remember the new top of stack for the task. */
\r
306 subs r0, #32 /* Go back for the low registers that are not automatically restored. */
\r
307 ldmia r0!, {r4-r7} /* Pop low registers. */
\r
312 /*-----------------------------------------------------------*/
\r
314 void xPortSysTickHandler( void )
\r
316 uint32_t ulPreviousMask;
\r
318 ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
\r
320 /* Increment the RTOS tick. */
\r
321 if( xTaskIncrementTick() != pdFALSE )
\r
323 /* Pend a context switch. */
\r
324 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
\r
327 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
\r
329 /*-----------------------------------------------------------*/
\r
332 * Setup the systick timer to generate the tick interrupts at the required
\r
335 void prvSetupTimerInterrupt( void )
\r
337 /* Configure SysTick to interrupt at the requested rate. */
\r
338 *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
339 *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
\r
341 /*-----------------------------------------------------------*/
\r