2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM0 port.
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30 *----------------------------------------------------------*/
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 /* Constants required to manipulate the NVIC. */
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37 #define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
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38 #define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
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39 #define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
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40 #define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
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41 #define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )
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42 #define portNVIC_SYSTICK_CLK 0x00000004
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43 #define portNVIC_SYSTICK_INT 0x00000002
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44 #define portNVIC_SYSTICK_ENABLE 0x00000001
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45 #define portNVIC_PENDSVSET 0x10000000
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46 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
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47 #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
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48 #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
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50 /* Constants required to set up the initial stack. */
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51 #define portINITIAL_XPSR ( 0x01000000 )
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53 /* Constants used with memory barrier intrinsics. */
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54 #define portSY_FULL_READ_WRITE ( 15 )
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56 /* Each task maintains its own interrupt status in the critical nesting
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58 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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61 * Setup the timer to generate the tick interrupts.
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63 static void prvSetupTimerInterrupt( void );
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66 * Exception handlers.
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68 void xPortPendSVHandler( void );
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69 void xPortSysTickHandler( void );
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70 void vPortSVCHandler( void );
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73 * Start first task is a separate function so it can be tested in isolation.
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75 static void prvPortStartFirstTask( void );
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78 * Used to catch tasks that attempt to return from their implementing function.
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80 static void prvTaskExitError( void );
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82 /*-----------------------------------------------------------*/
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85 * See header file for description.
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87 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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89 /* Simulate the stack frame as it would be created by a context switch
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91 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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92 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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94 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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96 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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97 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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98 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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99 pxTopOfStack -= 8; /* R11..R4. */
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101 return pxTopOfStack;
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103 /*-----------------------------------------------------------*/
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105 static void prvTaskExitError( void )
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107 /* A function that implements a task must not exit or attempt to return to
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108 its caller as there is nothing to return to. If a task wants to exit it
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109 should instead call vTaskDelete( NULL ).
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111 Artificially force an assert() to be triggered if configASSERT() is
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112 defined, then stop here so application writers can catch the error. */
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113 configASSERT( uxCriticalNesting == ~0UL );
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114 portDISABLE_INTERRUPTS();
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117 /*-----------------------------------------------------------*/
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119 void vPortSVCHandler( void )
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121 /* This function is no longer used, but retained for backward
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124 /*-----------------------------------------------------------*/
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126 __asm void prvPortStartFirstTask( void )
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128 extern pxCurrentTCB;
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132 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
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133 table offset register that can be used to locate the initial stack value.
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134 Not all M0 parts have the application vector table at address 0. */
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136 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
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138 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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139 adds r0, #32 /* Discard everything up to r0. */
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140 msr psp, r0 /* This is now the new top of stack to use in the task. */
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141 movs r0, #2 /* Switch to the psp stack. */
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144 pop {r0-r5} /* Pop the registers that are saved automatically. */
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145 mov lr, r5 /* lr is now in r5. */
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146 pop {r3} /* The return address is now in r3. */
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147 pop {r2} /* Pop and discard the XPSR. */
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148 cpsie i /* The first task has its context and interrupts can be enabled. */
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149 bx r3 /* Finally, jump to the user defined task code. */
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153 /*-----------------------------------------------------------*/
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156 * See header file for description.
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158 BaseType_t xPortStartScheduler( void )
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160 /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
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161 *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
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162 *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
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164 /* Start the timer that generates the tick ISR. Interrupts are disabled
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166 prvSetupTimerInterrupt();
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168 /* Initialise the critical nesting count ready for the first task. */
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169 uxCriticalNesting = 0;
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171 /* Start the first task. */
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172 prvPortStartFirstTask();
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174 /* Should not get here! */
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177 /*-----------------------------------------------------------*/
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179 void vPortEndScheduler( void )
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181 /* Not implemented in ports where there is nothing to return to.
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182 Artificially force an assert. */
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183 configASSERT( uxCriticalNesting == 1000UL );
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185 /*-----------------------------------------------------------*/
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187 void vPortYield( void )
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189 /* Set a PendSV to request a context switch. */
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190 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
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192 /* Barriers are normally not required but do ensure the code is completely
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193 within the specified behaviour for the architecture. */
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194 __dsb( portSY_FULL_READ_WRITE );
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195 __isb( portSY_FULL_READ_WRITE );
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197 /*-----------------------------------------------------------*/
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199 void vPortEnterCritical( void )
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201 portDISABLE_INTERRUPTS();
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202 uxCriticalNesting++;
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203 __dsb( portSY_FULL_READ_WRITE );
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204 __isb( portSY_FULL_READ_WRITE );
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206 /*-----------------------------------------------------------*/
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208 void vPortExitCritical( void )
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210 configASSERT( uxCriticalNesting );
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211 uxCriticalNesting--;
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212 if( uxCriticalNesting == 0 )
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214 portENABLE_INTERRUPTS();
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217 /*-----------------------------------------------------------*/
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219 __asm uint32_t ulSetInterruptMaskFromISR( void )
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225 /*-----------------------------------------------------------*/
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227 __asm void vClearInterruptMaskFromISR( uint32_t ulMask )
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232 /*-----------------------------------------------------------*/
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234 __asm void xPortPendSVHandler( void )
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236 extern vTaskSwitchContext
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237 extern pxCurrentTCB
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243 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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246 subs r0, #32 /* Make space for the remaining low registers. */
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247 str r0, [r2] /* Save the new top of stack. */
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248 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
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249 mov r4, r8 /* Store the high registers. */
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257 bl vTaskSwitchContext
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259 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
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262 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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263 adds r0, #16 /* Move to the high registers. */
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264 ldmia r0!, {r4-r7} /* Pop the high registers. */
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270 msr psp, r0 /* Remember the new top of stack for the task. */
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272 subs r0, #32 /* Go back for the low registers that are not automatically restored. */
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273 ldmia r0!, {r4-r7} /* Pop low registers. */
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278 /*-----------------------------------------------------------*/
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280 void xPortSysTickHandler( void )
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282 uint32_t ulPreviousMask;
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284 ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
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286 /* Increment the RTOS tick. */
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287 if( xTaskIncrementTick() != pdFALSE )
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289 /* Pend a context switch. */
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290 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
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293 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
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295 /*-----------------------------------------------------------*/
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298 * Setup the systick timer to generate the tick interrupts at the required
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301 void prvSetupTimerInterrupt( void )
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303 /* Stop and reset the SysTick. */
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304 *(portNVIC_SYSTICK_CTRL) = 0UL;
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305 *(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
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307 /* Configure SysTick to interrupt at the requested rate. */
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308 *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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309 *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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311 /*-----------------------------------------------------------*/
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