2 FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /*-----------------------------------------------------------
\r
71 * Implementation of functions defined in portable.h for the ARM CM0 port.
\r
72 *----------------------------------------------------------*/
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
78 /* Constants required to manipulate the NVIC. */
\r
79 #define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t *) 0xe000e010 )
\r
80 #define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t *) 0xe000e014 )
\r
81 #define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
\r
82 #define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )
\r
83 #define portNVIC_SYSTICK_CLK 0x00000004
\r
84 #define portNVIC_SYSTICK_INT 0x00000002
\r
85 #define portNVIC_SYSTICK_ENABLE 0x00000001
\r
86 #define portNVIC_PENDSVSET 0x10000000
\r
87 #define portMIN_INTERRUPT_PRIORITY ( 255UL )
\r
88 #define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
\r
89 #define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
\r
91 /* Constants required to set up the initial stack. */
\r
92 #define portINITIAL_XPSR ( 0x01000000 )
\r
94 /* Constants used with memory barrier intrinsics. */
\r
95 #define portSY_FULL_READ_WRITE ( 15 )
\r
97 /* Each task maintains its own interrupt status in the critical nesting
\r
99 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
102 * Setup the timer to generate the tick interrupts.
\r
104 static void prvSetupTimerInterrupt( void );
\r
107 * Exception handlers.
\r
109 void xPortPendSVHandler( void );
\r
110 void xPortSysTickHandler( void );
\r
111 void vPortSVCHandler( void );
\r
114 * Start first task is a separate function so it can be tested in isolation.
\r
116 static void prvPortStartFirstTask( void );
\r
119 * Used to catch tasks that attempt to return from their implementing function.
\r
121 static void prvTaskExitError( void );
\r
123 /*-----------------------------------------------------------*/
\r
126 * See header file for description.
\r
128 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
130 /* Simulate the stack frame as it would be created by a context switch
\r
132 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
133 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
135 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
137 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
\r
138 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
139 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
140 pxTopOfStack -= 8; /* R11..R4. */
\r
142 return pxTopOfStack;
\r
144 /*-----------------------------------------------------------*/
\r
146 static void prvTaskExitError( void )
\r
148 /* A function that implements a task must not exit or attempt to return to
\r
149 its caller as there is nothing to return to. If a task wants to exit it
\r
150 should instead call vTaskDelete( NULL ).
\r
152 Artificially force an assert() to be triggered if configASSERT() is
\r
153 defined, then stop here so application writers can catch the error. */
\r
154 configASSERT( uxCriticalNesting == ~0UL );
\r
155 portDISABLE_INTERRUPTS();
\r
158 /*-----------------------------------------------------------*/
\r
160 void vPortSVCHandler( void )
\r
162 /* This function is no longer used, but retained for backward
\r
165 /*-----------------------------------------------------------*/
\r
167 __asm void prvPortStartFirstTask( void )
\r
169 extern pxCurrentTCB;
\r
173 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
\r
174 table offset register that can be used to locate the initial stack value.
\r
175 Not all M0 parts have the application vector table at address 0. */
\r
177 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
\r
179 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
180 adds r0, #32 /* Discard everything up to r0. */
\r
181 msr psp, r0 /* This is now the new top of stack to use in the task. */
\r
182 movs r0, #2 /* Switch to the psp stack. */
\r
185 pop {r0-r5} /* Pop the registers that are saved automatically. */
\r
186 mov lr, r5 /* lr is now in r5. */
\r
187 cpsie i /* The first task has its context and interrupts can be enabled. */
\r
188 pop {pc} /* Finally, pop the PC to jump to the user defined task code. */
\r
192 /*-----------------------------------------------------------*/
\r
195 * See header file for description.
\r
197 BaseType_t xPortStartScheduler( void )
\r
199 /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */
\r
200 *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
\r
201 *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
\r
203 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
205 prvSetupTimerInterrupt();
\r
207 /* Initialise the critical nesting count ready for the first task. */
\r
208 uxCriticalNesting = 0;
\r
210 /* Start the first task. */
\r
211 prvPortStartFirstTask();
\r
213 /* Should not get here! */
\r
216 /*-----------------------------------------------------------*/
\r
218 void vPortEndScheduler( void )
\r
220 /* Not implemented in ports where there is nothing to return to.
\r
221 Artificially force an assert. */
\r
222 configASSERT( uxCriticalNesting == 1000UL );
\r
224 /*-----------------------------------------------------------*/
\r
226 void vPortYield( void )
\r
228 /* Set a PendSV to request a context switch. */
\r
229 *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
\r
231 /* Barriers are normally not required but do ensure the code is completely
\r
232 within the specified behaviour for the architecture. */
\r
233 __dsb( portSY_FULL_READ_WRITE );
\r
234 __isb( portSY_FULL_READ_WRITE );
\r
236 /*-----------------------------------------------------------*/
\r
238 void vPortEnterCritical( void )
\r
240 portDISABLE_INTERRUPTS();
\r
241 uxCriticalNesting++;
\r
242 __dsb( portSY_FULL_READ_WRITE );
\r
243 __isb( portSY_FULL_READ_WRITE );
\r
245 /*-----------------------------------------------------------*/
\r
247 void vPortExitCritical( void )
\r
249 configASSERT( uxCriticalNesting );
\r
250 uxCriticalNesting--;
\r
251 if( uxCriticalNesting == 0 )
\r
253 portENABLE_INTERRUPTS();
\r
256 /*-----------------------------------------------------------*/
\r
258 __asm uint32_t ulSetInterruptMaskFromISR( void )
\r
264 /*-----------------------------------------------------------*/
\r
266 __asm void vClearInterruptMaskFromISR( uint32_t ulMask )
\r
271 /*-----------------------------------------------------------*/
\r
273 __asm void xPortPendSVHandler( void )
\r
275 extern vTaskSwitchContext
\r
276 extern pxCurrentTCB
\r
282 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
\r
285 subs r0, #32 /* Make space for the remaining low registers. */
\r
286 str r0, [r2] /* Save the new top of stack. */
\r
287 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
\r
288 mov r4, r8 /* Store the high registers. */
\r
296 bl vTaskSwitchContext
\r
298 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
\r
301 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
302 adds r0, #16 /* Move to the high registers. */
\r
303 ldmia r0!, {r4-r7} /* Pop the high registers. */
\r
309 msr psp, r0 /* Remember the new top of stack for the task. */
\r
311 subs r0, #32 /* Go back for the low registers that are not automatically restored. */
\r
312 ldmia r0!, {r4-r7} /* Pop low registers. */
\r
317 /*-----------------------------------------------------------*/
\r
319 void xPortSysTickHandler( void )
\r
321 uint32_t ulPreviousMask;
\r
323 ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
\r
325 /* Increment the RTOS tick. */
\r
326 if( xTaskIncrementTick() != pdFALSE )
\r
328 /* Pend a context switch. */
\r
329 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
\r
332 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
\r
334 /*-----------------------------------------------------------*/
\r
337 * Setup the systick timer to generate the tick interrupts at the required
\r
340 void prvSetupTimerInterrupt( void )
\r
342 /* Configure SysTick to interrupt at the requested rate. */
\r
343 *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
344 *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
\r
346 /*-----------------------------------------------------------*/
\r