2 FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /*-----------------------------------------------------------
\r
71 * Implementation of functions defined in portable.h for the ARM CM3 port.
\r
72 *----------------------------------------------------------*/
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
78 #ifndef configKERNEL_INTERRUPT_PRIORITY
\r
79 #define configKERNEL_INTERRUPT_PRIORITY 255
\r
82 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
\r
83 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
\r
86 #ifndef configSYSTICK_CLOCK_HZ
\r
87 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
88 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
89 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
91 /* The way the SysTick is clocked is not modified in case it is not the same
\r
93 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
96 /* The __weak attribute does not work as you might expect with the Keil tools
\r
97 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
\r
98 the application writer wants to provide their own implementation of
\r
99 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
101 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
102 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
\r
105 /* Constants required to manipulate the core. Registers first... */
\r
106 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
107 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
108 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
109 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
110 /* ...then bits in the registers. */
\r
111 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
112 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
113 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
114 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
115 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
117 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
118 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
120 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
121 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
123 /* Constants required to check the validity of an interrupt priority. */
\r
124 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
125 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
126 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
127 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
128 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
129 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
130 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
131 #define portPRIGROUP_SHIFT ( 8UL )
\r
133 /* Constants required to set up the initial stack. */
\r
134 #define portINITIAL_XPSR ( 0x01000000 )
\r
136 /* Constants used with memory barrier intrinsics. */
\r
137 #define portSY_FULL_READ_WRITE ( 15 )
\r
139 /* The systick is a 24-bit counter. */
\r
140 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
142 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
143 occurred while the SysTick counter is stopped during tickless idle
\r
145 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
147 /* Each task maintains its own interrupt status in the critical nesting
\r
149 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
152 * Setup the timer to generate the tick interrupts. The implementation in this
\r
153 * file is weak to allow application writers to change the timer used to
\r
154 * generate the tick interrupt.
\r
156 void vPortSetupTimerInterrupt( void );
\r
159 * Exception handlers.
\r
161 void xPortPendSVHandler( void );
\r
162 void xPortSysTickHandler( void );
\r
163 void vPortSVCHandler( void );
\r
166 * Start first task is a separate function so it can be tested in isolation.
\r
168 static void prvStartFirstTask( void );
\r
171 * Used to catch tasks that attempt to return from their implementing function.
\r
173 static void prvTaskExitError( void );
\r
175 /*-----------------------------------------------------------*/
\r
178 * The number of SysTick increments that make up one tick period.
\r
180 #if configUSE_TICKLESS_IDLE == 1
\r
181 static uint32_t ulTimerCountsForOneTick = 0;
\r
182 #endif /* configUSE_TICKLESS_IDLE */
\r
185 * The maximum number of tick periods that can be suppressed is limited by the
\r
186 * 24 bit resolution of the SysTick timer.
\r
188 #if configUSE_TICKLESS_IDLE == 1
\r
189 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
190 #endif /* configUSE_TICKLESS_IDLE */
\r
193 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
194 * power functionality only.
\r
196 #if configUSE_TICKLESS_IDLE == 1
\r
197 static uint32_t ulStoppedTimerCompensation = 0;
\r
198 #endif /* configUSE_TICKLESS_IDLE */
\r
201 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
202 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
203 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
205 #if ( configASSERT_DEFINED == 1 )
\r
206 static uint8_t ucMaxSysCallPriority = 0;
\r
207 static uint32_t ulMaxPRIGROUPValue = 0;
\r
208 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
209 #endif /* configASSERT_DEFINED */
\r
211 /*-----------------------------------------------------------*/
\r
214 * See header file for description.
\r
216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
218 /* Simulate the stack frame as it would be created by a context switch
\r
220 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
\r
221 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
223 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
\r
225 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
\r
227 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
228 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
229 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
231 return pxTopOfStack;
\r
233 /*-----------------------------------------------------------*/
\r
235 static void prvTaskExitError( void )
\r
237 /* A function that implements a task must not exit or attempt to return to
\r
238 its caller as there is nothing to return to. If a task wants to exit it
\r
239 should instead call vTaskDelete( NULL ).
\r
241 Artificially force an assert() to be triggered if configASSERT() is
\r
242 defined, then stop here so application writers can catch the error. */
\r
243 configASSERT( uxCriticalNesting == ~0UL );
\r
244 portDISABLE_INTERRUPTS();
\r
247 /*-----------------------------------------------------------*/
\r
249 __asm void vPortSVCHandler( void )
\r
253 ldr r3, =pxCurrentTCB /* Restore the context. */
\r
254 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
255 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
256 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
257 msr psp, r0 /* Restore the task stack pointer. */
\r
264 /*-----------------------------------------------------------*/
\r
266 __asm void prvStartFirstTask( void )
\r
270 /* Use the NVIC offset register to locate the stack. */
\r
271 ldr r0, =0xE000ED08
\r
274 /* Set the msp back to the start of the stack. */
\r
276 /* Globally enable interrupts. */
\r
281 /* Call SVC to start the first task. */
\r
286 /*-----------------------------------------------------------*/
\r
289 * See header file for description.
\r
291 BaseType_t xPortStartScheduler( void )
\r
293 #if( configASSERT_DEFINED == 1 )
\r
295 volatile uint32_t ulOriginalPriority;
\r
296 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
297 volatile uint8_t ucMaxPriorityValue;
\r
299 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
300 functions can be called. ISR safe functions are those that end in
\r
301 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
302 ensure interrupt entry is as fast and simple as possible.
\r
304 Save the interrupt priority value that is about to be clobbered. */
\r
305 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
307 /* Determine the number of priority bits available. First write to all
\r
309 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
311 /* Read the value back to see how many bits stuck. */
\r
312 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
314 /* Use the same mask on the maximum system call priority. */
\r
315 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
317 /* Calculate the maximum acceptable priority group value for the number
\r
318 of bits read back. */
\r
319 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
320 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
322 ulMaxPRIGROUPValue--;
\r
323 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
326 /* Shift the priority group value back to its position within the AIRCR
\r
328 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
329 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
331 /* Restore the clobbered interrupt priority register to its original
\r
333 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
335 #endif /* conifgASSERT_DEFINED */
\r
337 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
338 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
339 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
341 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
343 vPortSetupTimerInterrupt();
\r
345 /* Initialise the critical nesting count ready for the first task. */
\r
346 uxCriticalNesting = 0;
\r
348 /* Start the first task. */
\r
349 prvStartFirstTask();
\r
351 /* Should not get here! */
\r
354 /*-----------------------------------------------------------*/
\r
356 void vPortEndScheduler( void )
\r
358 /* Not implemented in ports where there is nothing to return to.
\r
359 Artificially force an assert. */
\r
360 configASSERT( uxCriticalNesting == 1000UL );
\r
362 /*-----------------------------------------------------------*/
\r
364 void vPortYield( void )
\r
366 /* Set a PendSV to request a context switch. */
\r
367 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
369 /* Barriers are normally not required but do ensure the code is completely
\r
370 within the specified behaviour for the architecture. */
\r
371 __dsb( portSY_FULL_READ_WRITE );
\r
372 __isb( portSY_FULL_READ_WRITE );
\r
374 /*-----------------------------------------------------------*/
\r
376 void vPortEnterCritical( void )
\r
378 portDISABLE_INTERRUPTS();
\r
379 uxCriticalNesting++;
\r
380 __dsb( portSY_FULL_READ_WRITE );
\r
381 __isb( portSY_FULL_READ_WRITE );
\r
383 /* This is not the interrupt safe version of the enter critical function so
\r
384 assert() if it is being called from an interrupt context. Only API
\r
385 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
386 the critical nesting count is 1 to protect against recursive calls if the
\r
387 assert function also uses a critical section. */
\r
388 if( uxCriticalNesting == 1 )
\r
390 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
393 /*-----------------------------------------------------------*/
\r
395 void vPortExitCritical( void )
\r
397 configASSERT( uxCriticalNesting );
\r
398 uxCriticalNesting--;
\r
399 if( uxCriticalNesting == 0 )
\r
401 portENABLE_INTERRUPTS();
\r
404 /*-----------------------------------------------------------*/
\r
406 __asm void xPortPendSVHandler( void )
\r
408 extern uxCriticalNesting;
\r
409 extern pxCurrentTCB;
\r
410 extern vTaskSwitchContext;
\r
417 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
\r
420 stmdb r0!, {r4-r11} /* Save the remaining registers. */
\r
421 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
\r
423 stmdb sp!, {r3, r14}
\r
424 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
426 bl vTaskSwitchContext
\r
429 ldmia sp!, {r3, r14}
\r
432 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
433 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
\r
439 /*-----------------------------------------------------------*/
\r
441 void xPortSysTickHandler( void )
\r
443 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
444 executes all interrupts must be unmasked. There is therefore no need to
\r
445 save and then restore the interrupt mask value as its value is already
\r
447 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
\r
449 /* Increment the RTOS tick. */
\r
450 if( xTaskIncrementTick() != pdFALSE )
\r
452 /* A context switch is required. Context switching is performed in
\r
453 the PendSV interrupt. Pend the PendSV interrupt. */
\r
454 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
457 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
\r
459 /*-----------------------------------------------------------*/
\r
461 #if configUSE_TICKLESS_IDLE == 1
\r
463 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
465 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
\r
466 TickType_t xModifiableIdleTime;
\r
468 /* Make sure the SysTick reload value does not overflow the counter. */
\r
469 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
471 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
474 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
475 is accounted for as best it can be, but using the tickless mode will
\r
476 inevitably result in some tiny drift of the time maintained by the
\r
477 kernel with respect to calendar time. */
\r
478 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
480 /* Calculate the reload value required to wait xExpectedIdleTime
\r
481 tick periods. -1 is used because this code will execute part way
\r
482 through one of the tick periods. */
\r
483 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
484 if( ulReloadValue > ulStoppedTimerCompensation )
\r
486 ulReloadValue -= ulStoppedTimerCompensation;
\r
489 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
490 method as that will mask interrupts that should exit sleep mode. */
\r
493 /* If a context switch is pending or a task is waiting for the scheduler
\r
494 to be unsuspended then abandon the low power entry. */
\r
495 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
497 /* Restart from whatever is left in the count register to complete
\r
498 this tick period. */
\r
499 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
501 /* Restart SysTick. */
\r
502 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
504 /* Reset the reload register to the value required for normal tick
\r
506 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
508 /* Re-enable interrupts - see comments above __disable_irq() call
\r
514 /* Set the new reload value. */
\r
515 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
517 /* Clear the SysTick count flag and set the count value back to
\r
519 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
521 /* Restart SysTick. */
\r
522 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
524 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
525 set its parameter to 0 to indicate that its implementation contains
\r
526 its own wait for interrupt or wait for event instruction, and so wfi
\r
527 should not be executed again. However, the original expected idle
\r
528 time variable must remain unmodified, so a copy is taken. */
\r
529 xModifiableIdleTime = xExpectedIdleTime;
\r
530 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
531 if( xModifiableIdleTime > 0 )
\r
533 __dsb( portSY_FULL_READ_WRITE );
\r
535 __isb( portSY_FULL_READ_WRITE );
\r
537 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
539 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
540 accounted for as best it can be, but using the tickless mode will
\r
541 inevitably result in some tiny drift of the time maintained by the
\r
542 kernel with respect to calendar time. */
\r
543 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
544 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
\r
546 /* Re-enable interrupts - see comments above __disable_irq() call
\r
550 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
552 uint32_t ulCalculatedLoadValue;
\r
554 /* The tick interrupt has already executed, and the SysTick
\r
555 count reloaded with ulReloadValue. Reset the
\r
556 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
558 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
560 /* Don't allow a tiny value, or values that have somehow
\r
561 underflowed because the post sleep hook did something
\r
562 that took too long. */
\r
563 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
565 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
568 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
570 /* The tick interrupt handler will already have pended the tick
\r
571 processing in the kernel. As the pending tick will be
\r
572 processed as soon as this function exits, the tick value
\r
573 maintained by the tick is stepped forward by one less than the
\r
574 time spent waiting. */
\r
575 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
579 /* Something other than the tick interrupt ended the sleep.
\r
580 Work out how long the sleep lasted rounded to complete tick
\r
581 periods (not the ulReload value which accounted for part
\r
583 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
585 /* How many complete tick periods passed while the processor
\r
587 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
589 /* The reload value is set to whatever fraction of a single tick
\r
591 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
594 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
595 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
596 value. The critical section is used to ensure the tick interrupt
\r
597 can only execute once in the case that the reload register is near
\r
599 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
600 portENTER_CRITICAL();
\r
602 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
603 vTaskStepTick( ulCompleteTickPeriods );
\r
604 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
606 portEXIT_CRITICAL();
\r
610 #endif /* #if configUSE_TICKLESS_IDLE */
\r
612 /*-----------------------------------------------------------*/
\r
615 * Setup the SysTick timer to generate the tick interrupts at the required
\r
618 #if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
\r
620 void vPortSetupTimerInterrupt( void )
\r
622 /* Calculate the constants required to configure the tick interrupt. */
\r
623 #if configUSE_TICKLESS_IDLE == 1
\r
625 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
626 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
627 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
629 #endif /* configUSE_TICKLESS_IDLE */
\r
631 /* Configure SysTick to interrupt at the requested rate. */
\r
632 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
633 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
636 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
637 /*-----------------------------------------------------------*/
\r
639 __asm uint32_t ulPortSetInterruptMask( void )
\r
644 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
648 /*-----------------------------------------------------------*/
\r
650 __asm void vPortClearInterruptMask( uint32_t ulNewMask )
\r
657 /*-----------------------------------------------------------*/
\r
659 __asm uint32_t vPortGetIPSR( void )
\r
666 /*-----------------------------------------------------------*/
\r
668 #if( configASSERT_DEFINED == 1 )
\r
670 void vPortValidateInterruptPriority( void )
\r
672 uint32_t ulCurrentInterrupt;
\r
673 uint8_t ucCurrentPriority;
\r
675 /* Obtain the number of the currently executing interrupt. */
\r
676 ulCurrentInterrupt = vPortGetIPSR();
\r
678 /* Is the interrupt number a user defined interrupt? */
\r
679 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
681 /* Look up the interrupt's priority. */
\r
682 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
684 /* The following assertion will fail if a service routine (ISR) for
\r
685 an interrupt that has been assigned a priority above
\r
686 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
687 function. ISR safe FreeRTOS API functions must *only* be called
\r
688 from interrupts that have been assigned a priority at or below
\r
689 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
691 Numerically low interrupt priority numbers represent logically high
\r
692 interrupt priorities, therefore the priority of the interrupt must
\r
693 be set to a value equal to or numerically *higher* than
\r
694 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
696 Interrupts that use the FreeRTOS API must not be left at their
\r
697 default priority of zero as that is the highest possible priority,
\r
698 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
699 and therefore also guaranteed to be invalid.
\r
701 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
702 interrupt entry is as fast and simple as possible.
\r
704 The following links provide detailed information:
\r
705 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
706 http://www.freertos.org/FAQHelp.html */
\r
707 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
710 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
711 that define each interrupt's priority to be split between bits that
\r
712 define the interrupt's pre-emption priority bits and bits that define
\r
713 the interrupt's sub-priority. For simplicity all bits must be defined
\r
714 to be pre-emption priority bits. The following assertion will fail if
\r
715 this is not the case (if some bits represent a sub-priority).
\r
717 If the application only uses CMSIS libraries for interrupt
\r
718 configuration then the correct setting can be achieved on all Cortex-M
\r
719 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
720 scheduler. Note however that some vendor specific peripheral libraries
\r
721 assume a non-zero priority group setting, in which cases using a value
\r
722 of zero will result in unpredicable behaviour. */
\r
723 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
726 #endif /* configASSERT_DEFINED */
\r