2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the ARM CM3 port.
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98 *----------------------------------------------------------*/
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100 /* Scheduler includes. */
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101 #include "FreeRTOS.h"
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104 #ifndef configKERNEL_INTERRUPT_PRIORITY
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105 #define configKERNEL_INTERRUPT_PRIORITY 255
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108 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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109 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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112 #ifndef configSYSTICK_CLOCK_HZ
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113 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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114 /* Ensure the SysTick is clocked at the same frequency as the core. */
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115 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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117 /* The way the SysTick is clocked is not modified in case it is not the same
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119 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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122 /* The __weak attribute does not work as you might expect with the Keil tools
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123 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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124 the application writer wants to provide their own implementation of
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125 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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127 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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128 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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131 /* Constants required to manipulate the core. Registers first... */
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132 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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133 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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134 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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135 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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136 /* ...then bits in the registers. */
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137 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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138 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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139 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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140 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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141 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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143 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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144 #define portVECTACTIVE_MASK ( 0xFFUL )
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146 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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147 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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149 /* Constants required to check the validity of an interrupt priority. */
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150 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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151 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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152 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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153 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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154 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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155 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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156 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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157 #define portPRIGROUP_SHIFT ( 8UL )
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159 /* Constants required to set up the initial stack. */
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160 #define portINITIAL_XPSR ( 0x01000000 )
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162 /* Constants used with memory barrier intrinsics. */
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163 #define portSY_FULL_READ_WRITE ( 15 )
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165 /* The systick is a 24-bit counter. */
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166 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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168 /* A fiddle factor to estimate the number of SysTick counts that would have
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169 occurred while the SysTick counter is stopped during tickless idle
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171 #define portMISSED_COUNTS_FACTOR ( 45UL )
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173 /* Each task maintains its own interrupt status in the critical nesting
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175 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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178 * Setup the timer to generate the tick interrupts. The implementation in this
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179 * file is weak to allow application writers to change the timer used to
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180 * generate the tick interrupt.
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182 void vPortSetupTimerInterrupt( void );
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185 * Exception handlers.
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187 void xPortPendSVHandler( void );
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188 void xPortSysTickHandler( void );
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189 void vPortSVCHandler( void );
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192 * Start first task is a separate function so it can be tested in isolation.
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194 static void prvStartFirstTask( void );
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197 * Used to catch tasks that attempt to return from their implementing function.
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199 static void prvTaskExitError( void );
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201 /*-----------------------------------------------------------*/
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204 * The number of SysTick increments that make up one tick period.
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206 #if configUSE_TICKLESS_IDLE == 1
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207 static uint32_t ulTimerCountsForOneTick = 0;
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208 #endif /* configUSE_TICKLESS_IDLE */
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211 * The maximum number of tick periods that can be suppressed is limited by the
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212 * 24 bit resolution of the SysTick timer.
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214 #if configUSE_TICKLESS_IDLE == 1
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215 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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216 #endif /* configUSE_TICKLESS_IDLE */
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219 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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220 * power functionality only.
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222 #if configUSE_TICKLESS_IDLE == 1
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223 static uint32_t ulStoppedTimerCompensation = 0;
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224 #endif /* configUSE_TICKLESS_IDLE */
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227 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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228 * FreeRTOS API functions are not called from interrupts that have been assigned
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229 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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231 #if ( configASSERT_DEFINED == 1 )
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232 static uint8_t ucMaxSysCallPriority = 0;
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233 static uint32_t ulMaxPRIGROUPValue = 0;
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234 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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235 #endif /* configASSERT_DEFINED */
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237 /*-----------------------------------------------------------*/
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240 * See header file for description.
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242 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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244 /* Simulate the stack frame as it would be created by a context switch
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246 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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247 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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249 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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251 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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253 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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254 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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255 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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257 return pxTopOfStack;
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259 /*-----------------------------------------------------------*/
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261 static void prvTaskExitError( void )
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263 /* A function that implements a task must not exit or attempt to return to
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264 its caller as there is nothing to return to. If a task wants to exit it
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265 should instead call vTaskDelete( NULL ).
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267 Artificially force an assert() to be triggered if configASSERT() is
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268 defined, then stop here so application writers can catch the error. */
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269 configASSERT( uxCriticalNesting == ~0UL );
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270 portDISABLE_INTERRUPTS();
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273 /*-----------------------------------------------------------*/
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275 __asm void vPortSVCHandler( void )
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279 ldr r3, =pxCurrentTCB /* Restore the context. */
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280 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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281 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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282 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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283 msr psp, r0 /* Restore the task stack pointer. */
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290 /*-----------------------------------------------------------*/
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292 __asm void prvStartFirstTask( void )
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296 /* Use the NVIC offset register to locate the stack. */
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297 ldr r0, =0xE000ED08
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300 /* Set the msp back to the start of the stack. */
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302 /* Globally enable interrupts. */
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307 /* Call SVC to start the first task. */
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312 /*-----------------------------------------------------------*/
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315 * See header file for description.
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317 BaseType_t xPortStartScheduler( void )
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319 #if( configASSERT_DEFINED == 1 )
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321 volatile uint32_t ulOriginalPriority;
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322 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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323 volatile uint8_t ucMaxPriorityValue;
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325 /* Determine the maximum priority from which ISR safe FreeRTOS API
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326 functions can be called. ISR safe functions are those that end in
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327 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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328 ensure interrupt entry is as fast and simple as possible.
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330 Save the interrupt priority value that is about to be clobbered. */
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331 ulOriginalPriority = *pucFirstUserPriorityRegister;
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333 /* Determine the number of priority bits available. First write to all
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335 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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337 /* Read the value back to see how many bits stuck. */
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338 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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340 /* Use the same mask on the maximum system call priority. */
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341 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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343 /* Calculate the maximum acceptable priority group value for the number
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344 of bits read back. */
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345 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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346 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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348 ulMaxPRIGROUPValue--;
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349 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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352 /* Shift the priority group value back to its position within the AIRCR
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354 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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355 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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357 /* Restore the clobbered interrupt priority register to its original
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359 *pucFirstUserPriorityRegister = ulOriginalPriority;
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361 #endif /* conifgASSERT_DEFINED */
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363 /* Make PendSV and SysTick the lowest priority interrupts. */
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364 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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365 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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367 /* Start the timer that generates the tick ISR. Interrupts are disabled
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369 vPortSetupTimerInterrupt();
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371 /* Initialise the critical nesting count ready for the first task. */
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372 uxCriticalNesting = 0;
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374 /* Start the first task. */
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375 prvStartFirstTask();
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377 /* Should not get here! */
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380 /*-----------------------------------------------------------*/
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382 void vPortEndScheduler( void )
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384 /* Not implemented in ports where there is nothing to return to.
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385 Artificially force an assert. */
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386 configASSERT( uxCriticalNesting == 1000UL );
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388 /*-----------------------------------------------------------*/
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390 void vPortYield( void )
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392 /* Set a PendSV to request a context switch. */
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393 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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395 /* Barriers are normally not required but do ensure the code is completely
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396 within the specified behaviour for the architecture. */
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397 __dsb( portSY_FULL_READ_WRITE );
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398 __isb( portSY_FULL_READ_WRITE );
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400 /*-----------------------------------------------------------*/
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402 void vPortEnterCritical( void )
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404 portDISABLE_INTERRUPTS();
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405 uxCriticalNesting++;
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406 __dsb( portSY_FULL_READ_WRITE );
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407 __isb( portSY_FULL_READ_WRITE );
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409 /* This is not the interrupt safe version of the enter critical function so
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410 assert() if it is being called from an interrupt context. Only API
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411 functions that end in "FromISR" can be used in an interrupt. Only assert if
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412 the critical nesting count is 1 to protect against recursive calls if the
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413 assert function also uses a critical section. */
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414 if( uxCriticalNesting == 1 )
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416 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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419 /*-----------------------------------------------------------*/
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421 void vPortExitCritical( void )
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423 configASSERT( uxCriticalNesting );
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424 uxCriticalNesting--;
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425 if( uxCriticalNesting == 0 )
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427 portENABLE_INTERRUPTS();
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430 /*-----------------------------------------------------------*/
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432 __asm void xPortPendSVHandler( void )
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434 extern uxCriticalNesting;
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435 extern pxCurrentTCB;
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436 extern vTaskSwitchContext;
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443 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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446 stmdb r0!, {r4-r11} /* Save the remaining registers. */
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447 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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449 stmdb sp!, {r3, r14}
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450 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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452 bl vTaskSwitchContext
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455 ldmia sp!, {r3, r14}
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458 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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459 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
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465 /*-----------------------------------------------------------*/
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467 void xPortSysTickHandler( void )
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469 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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470 executes all interrupts must be unmasked. There is therefore no need to
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471 save and then restore the interrupt mask value as its value is already
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473 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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475 /* Increment the RTOS tick. */
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476 if( xTaskIncrementTick() != pdFALSE )
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478 /* A context switch is required. Context switching is performed in
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479 the PendSV interrupt. Pend the PendSV interrupt. */
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480 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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483 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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485 /*-----------------------------------------------------------*/
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487 #if configUSE_TICKLESS_IDLE == 1
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489 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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491 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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492 TickType_t xModifiableIdleTime;
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494 /* Make sure the SysTick reload value does not overflow the counter. */
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495 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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497 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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500 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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501 is accounted for as best it can be, but using the tickless mode will
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502 inevitably result in some tiny drift of the time maintained by the
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503 kernel with respect to calendar time. */
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504 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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506 /* Calculate the reload value required to wait xExpectedIdleTime
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507 tick periods. -1 is used because this code will execute part way
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508 through one of the tick periods. */
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509 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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510 if( ulReloadValue > ulStoppedTimerCompensation )
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512 ulReloadValue -= ulStoppedTimerCompensation;
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515 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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516 method as that will mask interrupts that should exit sleep mode. */
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519 /* If a context switch is pending or a task is waiting for the scheduler
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520 to be unsuspended then abandon the low power entry. */
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521 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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523 /* Restart from whatever is left in the count register to complete
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524 this tick period. */
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525 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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527 /* Restart SysTick. */
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528 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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530 /* Reset the reload register to the value required for normal tick
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532 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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534 /* Re-enable interrupts - see comments above __disable_irq() call
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540 /* Set the new reload value. */
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541 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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543 /* Clear the SysTick count flag and set the count value back to
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545 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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547 /* Restart SysTick. */
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548 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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550 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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551 set its parameter to 0 to indicate that its implementation contains
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552 its own wait for interrupt or wait for event instruction, and so wfi
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553 should not be executed again. However, the original expected idle
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554 time variable must remain unmodified, so a copy is taken. */
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555 xModifiableIdleTime = xExpectedIdleTime;
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556 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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557 if( xModifiableIdleTime > 0 )
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559 __dsb( portSY_FULL_READ_WRITE );
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561 __isb( portSY_FULL_READ_WRITE );
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563 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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565 /* Stop SysTick. Again, the time the SysTick is stopped for is
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566 accounted for as best it can be, but using the tickless mode will
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567 inevitably result in some tiny drift of the time maintained by the
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568 kernel with respect to calendar time. */
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569 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
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570 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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572 /* Re-enable interrupts - see comments above __disable_irq() call
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576 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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578 uint32_t ulCalculatedLoadValue;
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580 /* The tick interrupt has already executed, and the SysTick
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581 count reloaded with ulReloadValue. Reset the
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582 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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584 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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586 /* Don't allow a tiny value, or values that have somehow
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587 underflowed because the post sleep hook did something
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588 that took too long. */
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589 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
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591 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
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594 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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596 /* The tick interrupt handler will already have pended the tick
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597 processing in the kernel. As the pending tick will be
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598 processed as soon as this function exits, the tick value
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599 maintained by the tick is stepped forward by one less than the
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600 time spent waiting. */
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601 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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605 /* Something other than the tick interrupt ended the sleep.
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606 Work out how long the sleep lasted rounded to complete tick
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607 periods (not the ulReload value which accounted for part
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609 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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611 /* How many complete tick periods passed while the processor
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613 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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615 /* The reload value is set to whatever fraction of a single tick
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617 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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620 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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621 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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622 value. The critical section is used to ensure the tick interrupt
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623 can only execute once in the case that the reload register is near
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625 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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626 portENTER_CRITICAL();
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628 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
629 vTaskStepTick( ulCompleteTickPeriods );
\r
630 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
632 portEXIT_CRITICAL();
\r
636 #endif /* #if configUSE_TICKLESS_IDLE */
\r
638 /*-----------------------------------------------------------*/
\r
641 * Setup the SysTick timer to generate the tick interrupts at the required
\r
644 #if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
\r
646 void vPortSetupTimerInterrupt( void )
\r
648 /* Calculate the constants required to configure the tick interrupt. */
\r
649 #if configUSE_TICKLESS_IDLE == 1
\r
651 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
652 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
653 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
655 #endif /* configUSE_TICKLESS_IDLE */
\r
657 /* Configure SysTick to interrupt at the requested rate. */
\r
658 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
659 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
662 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
663 /*-----------------------------------------------------------*/
\r
665 __asm uint32_t ulPortSetInterruptMask( void )
\r
670 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
674 /*-----------------------------------------------------------*/
\r
676 __asm void vPortClearInterruptMask( uint32_t ulNewMask )
\r
683 /*-----------------------------------------------------------*/
\r
685 __asm uint32_t vPortGetIPSR( void )
\r
692 /*-----------------------------------------------------------*/
\r
694 #if( configASSERT_DEFINED == 1 )
\r
696 void vPortValidateInterruptPriority( void )
\r
698 uint32_t ulCurrentInterrupt;
\r
699 uint8_t ucCurrentPriority;
\r
701 /* Obtain the number of the currently executing interrupt. */
\r
702 ulCurrentInterrupt = vPortGetIPSR();
\r
704 /* Is the interrupt number a user defined interrupt? */
\r
705 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
707 /* Look up the interrupt's priority. */
\r
708 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
710 /* The following assertion will fail if a service routine (ISR) for
\r
711 an interrupt that has been assigned a priority above
\r
712 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
713 function. ISR safe FreeRTOS API functions must *only* be called
\r
714 from interrupts that have been assigned a priority at or below
\r
715 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
717 Numerically low interrupt priority numbers represent logically high
\r
718 interrupt priorities, therefore the priority of the interrupt must
\r
719 be set to a value equal to or numerically *higher* than
\r
720 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
722 Interrupts that use the FreeRTOS API must not be left at their
\r
723 default priority of zero as that is the highest possible priority,
\r
724 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
725 and therefore also guaranteed to be invalid.
\r
727 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
728 interrupt entry is as fast and simple as possible.
\r
730 The following links provide detailed information:
\r
731 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
732 http://www.freertos.org/FAQHelp.html */
\r
733 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
736 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
737 that define each interrupt's priority to be split between bits that
\r
738 define the interrupt's pre-emption priority bits and bits that define
\r
739 the interrupt's sub-priority. For simplicity all bits must be defined
\r
740 to be pre-emption priority bits. The following assertion will fail if
\r
741 this is not the case (if some bits represent a sub-priority).
\r
743 If the application only uses CMSIS libraries for interrupt
\r
744 configuration then the correct setting can be achieved on all Cortex-M
\r
745 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
746 scheduler. Note however that some vendor specific peripheral libraries
\r
747 assume a non-zero priority group setting, in which cases using a value
\r
748 of zero will result in unpredicable behaviour. */
\r
749 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
752 #endif /* configASSERT_DEFINED */
\r