2 * FreeRTOS Kernel V10.2.1
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM3 port.
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30 *----------------------------------------------------------*/
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 #ifndef configKERNEL_INTERRUPT_PRIORITY
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37 #define configKERNEL_INTERRUPT_PRIORITY 255
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40 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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41 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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44 #ifndef configSYSTICK_CLOCK_HZ
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45 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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46 /* Ensure the SysTick is clocked at the same frequency as the core. */
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47 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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49 /* The way the SysTick is clocked is not modified in case it is not the same
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51 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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54 /* The __weak attribute does not work as you might expect with the Keil tools
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55 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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56 the application writer wants to provide their own implementation of
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57 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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59 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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60 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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63 /* Constants required to manipulate the core. Registers first... */
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64 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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65 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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66 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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67 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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68 /* ...then bits in the registers. */
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69 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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70 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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71 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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72 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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73 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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75 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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76 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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78 /* Constants required to check the validity of an interrupt priority. */
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79 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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80 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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81 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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82 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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83 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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84 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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85 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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86 #define portPRIGROUP_SHIFT ( 8UL )
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88 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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89 #define portVECTACTIVE_MASK ( 0xFFUL )
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91 /* Constants required to set up the initial stack. */
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92 #define portINITIAL_XPSR ( 0x01000000 )
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94 /* The systick is a 24-bit counter. */
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95 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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97 /* A fiddle factor to estimate the number of SysTick counts that would have
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98 occurred while the SysTick counter is stopped during tickless idle
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100 #define portMISSED_COUNTS_FACTOR ( 45UL )
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102 /* For strict compliance with the Cortex-M spec the task start address should
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103 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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104 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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107 * Setup the timer to generate the tick interrupts. The implementation in this
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108 * file is weak to allow application writers to change the timer used to
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109 * generate the tick interrupt.
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111 void vPortSetupTimerInterrupt( void );
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114 * Exception handlers.
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116 void xPortPendSVHandler( void );
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117 void xPortSysTickHandler( void );
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118 void vPortSVCHandler( void );
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121 * Start first task is a separate function so it can be tested in isolation.
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123 static void prvStartFirstTask( void );
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126 * Used to catch tasks that attempt to return from their implementing function.
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128 static void prvTaskExitError( void );
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130 /*-----------------------------------------------------------*/
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132 /* Each task maintains its own interrupt status in the critical nesting
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134 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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137 * The number of SysTick increments that make up one tick period.
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139 #if( configUSE_TICKLESS_IDLE == 1 )
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140 static uint32_t ulTimerCountsForOneTick = 0;
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141 #endif /* configUSE_TICKLESS_IDLE */
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144 * The maximum number of tick periods that can be suppressed is limited by the
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145 * 24 bit resolution of the SysTick timer.
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147 #if( configUSE_TICKLESS_IDLE == 1 )
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148 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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149 #endif /* configUSE_TICKLESS_IDLE */
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152 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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153 * power functionality only.
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155 #if( configUSE_TICKLESS_IDLE == 1 )
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156 static uint32_t ulStoppedTimerCompensation = 0;
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157 #endif /* configUSE_TICKLESS_IDLE */
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160 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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161 * FreeRTOS API functions are not called from interrupts that have been assigned
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162 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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164 #if ( configASSERT_DEFINED == 1 )
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165 static uint8_t ucMaxSysCallPriority = 0;
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166 static uint32_t ulMaxPRIGROUPValue = 0;
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167 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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168 #endif /* configASSERT_DEFINED */
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170 /*-----------------------------------------------------------*/
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173 * See header file for description.
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175 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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177 /* Simulate the stack frame as it would be created by a context switch
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179 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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180 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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182 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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184 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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186 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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187 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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188 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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190 return pxTopOfStack;
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192 /*-----------------------------------------------------------*/
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194 static void prvTaskExitError( void )
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196 /* A function that implements a task must not exit or attempt to return to
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197 its caller as there is nothing to return to. If a task wants to exit it
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198 should instead call vTaskDelete( NULL ).
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200 Artificially force an assert() to be triggered if configASSERT() is
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201 defined, then stop here so application writers can catch the error. */
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202 configASSERT( uxCriticalNesting == ~0UL );
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203 portDISABLE_INTERRUPTS();
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206 /*-----------------------------------------------------------*/
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208 __asm void vPortSVCHandler( void )
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212 ldr r3, =pxCurrentTCB /* Restore the context. */
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213 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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214 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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215 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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216 msr psp, r0 /* Restore the task stack pointer. */
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223 /*-----------------------------------------------------------*/
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225 __asm void prvStartFirstTask( void )
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229 /* Use the NVIC offset register to locate the stack. */
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230 ldr r0, =0xE000ED08
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234 /* Set the msp back to the start of the stack. */
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236 /* Globally enable interrupts. */
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241 /* Call SVC to start the first task. */
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246 /*-----------------------------------------------------------*/
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249 * See header file for description.
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251 BaseType_t xPortStartScheduler( void )
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253 #if( configASSERT_DEFINED == 1 )
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255 volatile uint32_t ulOriginalPriority;
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256 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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257 volatile uint8_t ucMaxPriorityValue;
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259 /* Determine the maximum priority from which ISR safe FreeRTOS API
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260 functions can be called. ISR safe functions are those that end in
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261 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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262 ensure interrupt entry is as fast and simple as possible.
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264 Save the interrupt priority value that is about to be clobbered. */
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265 ulOriginalPriority = *pucFirstUserPriorityRegister;
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267 /* Determine the number of priority bits available. First write to all
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269 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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271 /* Read the value back to see how many bits stuck. */
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272 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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274 /* The kernel interrupt priority should be set to the lowest
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276 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
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278 /* Use the same mask on the maximum system call priority. */
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279 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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281 /* Calculate the maximum acceptable priority group value for the number
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282 of bits read back. */
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283 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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284 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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286 ulMaxPRIGROUPValue--;
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287 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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290 #ifdef __NVIC_PRIO_BITS
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292 /* Check the CMSIS configuration that defines the number of
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293 priority bits matches the number of priority bits actually queried
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294 from the hardware. */
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295 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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299 #ifdef configPRIO_BITS
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301 /* Check the FreeRTOS configuration that defines the number of
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302 priority bits matches the number of priority bits actually queried
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303 from the hardware. */
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304 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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308 /* Shift the priority group value back to its position within the AIRCR
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310 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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311 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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313 /* Restore the clobbered interrupt priority register to its original
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315 *pucFirstUserPriorityRegister = ulOriginalPriority;
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317 #endif /* conifgASSERT_DEFINED */
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319 /* Make PendSV and SysTick the lowest priority interrupts. */
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320 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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321 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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323 /* Start the timer that generates the tick ISR. Interrupts are disabled
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325 vPortSetupTimerInterrupt();
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327 /* Initialise the critical nesting count ready for the first task. */
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328 uxCriticalNesting = 0;
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330 /* Start the first task. */
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331 prvStartFirstTask();
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333 /* Should not get here! */
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336 /*-----------------------------------------------------------*/
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338 void vPortEndScheduler( void )
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340 /* Not implemented in ports where there is nothing to return to.
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341 Artificially force an assert. */
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342 configASSERT( uxCriticalNesting == 1000UL );
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344 /*-----------------------------------------------------------*/
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346 void vPortEnterCritical( void )
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348 portDISABLE_INTERRUPTS();
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349 uxCriticalNesting++;
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351 /* This is not the interrupt safe version of the enter critical function so
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352 assert() if it is being called from an interrupt context. Only API
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353 functions that end in "FromISR" can be used in an interrupt. Only assert if
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354 the critical nesting count is 1 to protect against recursive calls if the
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355 assert function also uses a critical section. */
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356 if( uxCriticalNesting == 1 )
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358 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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361 /*-----------------------------------------------------------*/
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363 void vPortExitCritical( void )
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365 configASSERT( uxCriticalNesting );
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366 uxCriticalNesting--;
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367 if( uxCriticalNesting == 0 )
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369 portENABLE_INTERRUPTS();
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372 /*-----------------------------------------------------------*/
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374 __asm void xPortPendSVHandler( void )
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376 extern uxCriticalNesting;
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377 extern pxCurrentTCB;
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378 extern vTaskSwitchContext;
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385 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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388 stmdb r0!, {r4-r11} /* Save the remaining registers. */
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389 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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391 stmdb sp!, {r3, r14}
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392 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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396 bl vTaskSwitchContext
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399 ldmia sp!, {r3, r14}
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402 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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403 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
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409 /*-----------------------------------------------------------*/
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411 void xPortSysTickHandler( void )
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413 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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414 executes all interrupts must be unmasked. There is therefore no need to
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415 save and then restore the interrupt mask value as its value is already
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416 known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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417 in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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418 vPortRaiseBASEPRI();
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420 /* Increment the RTOS tick. */
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421 if( xTaskIncrementTick() != pdFALSE )
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423 /* A context switch is required. Context switching is performed in
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424 the PendSV interrupt. Pend the PendSV interrupt. */
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425 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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428 vPortClearBASEPRIFromISR();
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430 /*-----------------------------------------------------------*/
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432 #if( configUSE_TICKLESS_IDLE == 1 )
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434 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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436 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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437 TickType_t xModifiableIdleTime;
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439 /* Make sure the SysTick reload value does not overflow the counter. */
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440 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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442 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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445 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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446 is accounted for as best it can be, but using the tickless mode will
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447 inevitably result in some tiny drift of the time maintained by the
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448 kernel with respect to calendar time. */
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449 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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451 /* Calculate the reload value required to wait xExpectedIdleTime
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452 tick periods. -1 is used because this code will execute part way
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453 through one of the tick periods. */
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454 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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455 if( ulReloadValue > ulStoppedTimerCompensation )
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457 ulReloadValue -= ulStoppedTimerCompensation;
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460 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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461 method as that will mask interrupts that should exit sleep mode. */
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463 __dsb( portSY_FULL_READ_WRITE );
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464 __isb( portSY_FULL_READ_WRITE );
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466 /* If a context switch is pending or a task is waiting for the scheduler
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467 to be unsuspended then abandon the low power entry. */
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468 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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470 /* Restart from whatever is left in the count register to complete
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471 this tick period. */
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472 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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474 /* Restart SysTick. */
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475 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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477 /* Reset the reload register to the value required for normal tick
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479 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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481 /* Re-enable interrupts - see comments above __disable_irq() call
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487 /* Set the new reload value. */
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488 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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490 /* Clear the SysTick count flag and set the count value back to
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492 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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494 /* Restart SysTick. */
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495 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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497 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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498 set its parameter to 0 to indicate that its implementation contains
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499 its own wait for interrupt or wait for event instruction, and so wfi
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500 should not be executed again. However, the original expected idle
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501 time variable must remain unmodified, so a copy is taken. */
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502 xModifiableIdleTime = xExpectedIdleTime;
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503 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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504 if( xModifiableIdleTime > 0 )
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506 __dsb( portSY_FULL_READ_WRITE );
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508 __isb( portSY_FULL_READ_WRITE );
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510 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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512 /* Re-enable interrupts to allow the interrupt that brought the MCU
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513 out of sleep mode to execute immediately. see comments above
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514 __disable_interrupt() call above. */
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516 __dsb( portSY_FULL_READ_WRITE );
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517 __isb( portSY_FULL_READ_WRITE );
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519 /* Disable interrupts again because the clock is about to be stopped
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520 and interrupts that execute while the clock is stopped will increase
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521 any slippage between the time maintained by the RTOS and calendar
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524 __dsb( portSY_FULL_READ_WRITE );
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525 __isb( portSY_FULL_READ_WRITE );
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527 /* Disable the SysTick clock without reading the
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528 portNVIC_SYSTICK_CTRL_REG register to ensure the
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529 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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530 the time the SysTick is stopped for is accounted for as best it can
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531 be, but using the tickless mode will inevitably result in some tiny
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532 drift of the time maintained by the kernel with respect to calendar
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534 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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536 /* Determine if the SysTick clock has already counted to zero and
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537 been set back to the current reload value (the reload back being
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538 correct for the entire expected idle time) or if the SysTick is yet
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539 to count to zero (in which case an interrupt other than the SysTick
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540 must have brought the system out of sleep mode). */
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541 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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543 uint32_t ulCalculatedLoadValue;
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545 /* The tick interrupt is already pending, and the SysTick count
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546 reloaded with ulReloadValue. Reset the
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547 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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549 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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551 /* Don't allow a tiny value, or values that have somehow
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552 underflowed because the post sleep hook did something
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553 that took too long. */
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554 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
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556 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
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559 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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561 /* As the pending tick will be processed as soon as this
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562 function exits, the tick value maintained by the tick is stepped
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563 forward by one less than the time spent waiting. */
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564 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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568 /* Something other than the tick interrupt ended the sleep.
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569 Work out how long the sleep lasted rounded to complete tick
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570 periods (not the ulReload value which accounted for part
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572 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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574 /* How many complete tick periods passed while the processor
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576 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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578 /* The reload value is set to whatever fraction of a single tick
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580 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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583 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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584 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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586 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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587 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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588 vTaskStepTick( ulCompleteTickPeriods );
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589 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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591 /* Exit with interrpts enabled. */
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596 #endif /* #if configUSE_TICKLESS_IDLE */
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598 /*-----------------------------------------------------------*/
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601 * Setup the SysTick timer to generate the tick interrupts at the required
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604 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
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606 void vPortSetupTimerInterrupt( void )
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608 /* Calculate the constants required to configure the tick interrupt. */
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609 #if( configUSE_TICKLESS_IDLE == 1 )
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611 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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612 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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613 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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615 #endif /* configUSE_TICKLESS_IDLE */
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617 /* Stop and clear the SysTick. */
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618 portNVIC_SYSTICK_CTRL_REG = 0UL;
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619 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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621 /* Configure SysTick to interrupt at the requested rate. */
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622 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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623 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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626 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
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627 /*-----------------------------------------------------------*/
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629 __asm uint32_t vPortGetIPSR( void )
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636 /*-----------------------------------------------------------*/
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638 #if( configASSERT_DEFINED == 1 )
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640 void vPortValidateInterruptPriority( void )
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642 uint32_t ulCurrentInterrupt;
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643 uint8_t ucCurrentPriority;
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645 /* Obtain the number of the currently executing interrupt. */
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646 ulCurrentInterrupt = vPortGetIPSR();
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648 /* Is the interrupt number a user defined interrupt? */
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649 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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651 /* Look up the interrupt's priority. */
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652 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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654 /* The following assertion will fail if a service routine (ISR) for
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655 an interrupt that has been assigned a priority above
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656 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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657 function. ISR safe FreeRTOS API functions must *only* be called
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658 from interrupts that have been assigned a priority at or below
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659 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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661 Numerically low interrupt priority numbers represent logically high
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662 interrupt priorities, therefore the priority of the interrupt must
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663 be set to a value equal to or numerically *higher* than
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664 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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666 Interrupts that use the FreeRTOS API must not be left at their
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667 default priority of zero as that is the highest possible priority,
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668 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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669 and therefore also guaranteed to be invalid.
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671 FreeRTOS maintains separate thread and ISR API functions to ensure
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672 interrupt entry is as fast and simple as possible.
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674 The following links provide detailed information:
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675 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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676 http://www.freertos.org/FAQHelp.html */
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677 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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680 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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681 that define each interrupt's priority to be split between bits that
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682 define the interrupt's pre-emption priority bits and bits that define
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683 the interrupt's sub-priority. For simplicity all bits must be defined
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684 to be pre-emption priority bits. The following assertion will fail if
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685 this is not the case (if some bits represent a sub-priority).
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687 If the application only uses CMSIS libraries for interrupt
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688 configuration then the correct setting can be achieved on all Cortex-M
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689 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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690 scheduler. Note however that some vendor specific peripheral libraries
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691 assume a non-zero priority group setting, in which cases using a value
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692 of zero will result in unpredictable behaviour. */
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693 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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696 #endif /* configASSERT_DEFINED */
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