2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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78 #ifndef configKERNEL_INTERRUPT_PRIORITY
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79 #define configKERNEL_INTERRUPT_PRIORITY 255
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82 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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83 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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86 #ifndef configSYSTICK_CLOCK_HZ
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87 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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88 /* Ensure the SysTick is clocked at the same frequency as the core. */
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89 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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91 /* The way the SysTick is clocked is not modified in case it is not the same
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93 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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96 /* The __weak attribute does not work as you might expect with the Keil tools
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97 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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98 the application writer wants to provide their own implementation of
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99 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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101 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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102 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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105 /* Constants required to manipulate the core. Registers first... */
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106 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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107 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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108 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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109 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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110 /* ...then bits in the registers. */
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111 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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112 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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113 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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114 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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115 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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117 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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118 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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120 /* Constants required to check the validity of an interrupt priority. */
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121 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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122 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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123 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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124 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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125 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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126 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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127 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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128 #define portPRIGROUP_SHIFT ( 8UL )
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130 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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131 #define portVECTACTIVE_MASK ( 0xFFUL )
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133 /* Constants required to set up the initial stack. */
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134 #define portINITIAL_XPSR ( 0x01000000 )
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136 /* The systick is a 24-bit counter. */
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137 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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139 /* A fiddle factor to estimate the number of SysTick counts that would have
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140 occurred while the SysTick counter is stopped during tickless idle
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142 #define portMISSED_COUNTS_FACTOR ( 45UL )
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144 /* For strict compliance with the Cortex-M spec the task start address should
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145 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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146 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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149 * Setup the timer to generate the tick interrupts. The implementation in this
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150 * file is weak to allow application writers to change the timer used to
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151 * generate the tick interrupt.
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153 void vPortSetupTimerInterrupt( void );
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156 * Exception handlers.
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158 void xPortPendSVHandler( void );
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159 void xPortSysTickHandler( void );
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160 void vPortSVCHandler( void );
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163 * Start first task is a separate function so it can be tested in isolation.
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165 static void prvStartFirstTask( void );
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168 * Used to catch tasks that attempt to return from their implementing function.
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170 static void prvTaskExitError( void );
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172 /*-----------------------------------------------------------*/
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174 /* Each task maintains its own interrupt status in the critical nesting
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176 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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179 * The number of SysTick increments that make up one tick period.
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181 #if( configUSE_TICKLESS_IDLE == 1 )
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182 static uint32_t ulTimerCountsForOneTick = 0;
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183 #endif /* configUSE_TICKLESS_IDLE */
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186 * The maximum number of tick periods that can be suppressed is limited by the
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187 * 24 bit resolution of the SysTick timer.
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189 #if( configUSE_TICKLESS_IDLE == 1 )
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190 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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191 #endif /* configUSE_TICKLESS_IDLE */
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194 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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195 * power functionality only.
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197 #if( configUSE_TICKLESS_IDLE == 1 )
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198 static uint32_t ulStoppedTimerCompensation = 0;
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199 #endif /* configUSE_TICKLESS_IDLE */
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202 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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203 * FreeRTOS API functions are not called from interrupts that have been assigned
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204 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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206 #if ( configASSERT_DEFINED == 1 )
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207 static uint8_t ucMaxSysCallPriority = 0;
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208 static uint32_t ulMaxPRIGROUPValue = 0;
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209 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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210 #endif /* configASSERT_DEFINED */
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212 /*-----------------------------------------------------------*/
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215 * See header file for description.
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217 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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219 /* Simulate the stack frame as it would be created by a context switch
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221 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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222 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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224 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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226 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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228 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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229 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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230 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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232 return pxTopOfStack;
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234 /*-----------------------------------------------------------*/
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236 static void prvTaskExitError( void )
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238 /* A function that implements a task must not exit or attempt to return to
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239 its caller as there is nothing to return to. If a task wants to exit it
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240 should instead call vTaskDelete( NULL ).
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242 Artificially force an assert() to be triggered if configASSERT() is
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243 defined, then stop here so application writers can catch the error. */
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244 configASSERT( uxCriticalNesting == ~0UL );
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245 portDISABLE_INTERRUPTS();
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248 /*-----------------------------------------------------------*/
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250 __asm void vPortSVCHandler( void )
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254 ldr r3, =pxCurrentTCB /* Restore the context. */
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255 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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256 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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257 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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258 msr psp, r0 /* Restore the task stack pointer. */
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265 /*-----------------------------------------------------------*/
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267 __asm void prvStartFirstTask( void )
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271 /* Use the NVIC offset register to locate the stack. */
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272 ldr r0, =0xE000ED08
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276 /* Set the msp back to the start of the stack. */
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278 /* Globally enable interrupts. */
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283 /* Call SVC to start the first task. */
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288 /*-----------------------------------------------------------*/
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291 * See header file for description.
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293 BaseType_t xPortStartScheduler( void )
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295 #if( configASSERT_DEFINED == 1 )
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297 volatile uint32_t ulOriginalPriority;
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298 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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299 volatile uint8_t ucMaxPriorityValue;
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301 /* Determine the maximum priority from which ISR safe FreeRTOS API
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302 functions can be called. ISR safe functions are those that end in
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303 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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304 ensure interrupt entry is as fast and simple as possible.
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306 Save the interrupt priority value that is about to be clobbered. */
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307 ulOriginalPriority = *pucFirstUserPriorityRegister;
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309 /* Determine the number of priority bits available. First write to all
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311 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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313 /* Read the value back to see how many bits stuck. */
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314 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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316 /* The kernel interrupt priority should be set to the lowest
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318 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
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320 /* Use the same mask on the maximum system call priority. */
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321 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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323 /* Calculate the maximum acceptable priority group value for the number
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324 of bits read back. */
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325 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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326 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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328 ulMaxPRIGROUPValue--;
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329 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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332 #ifdef __NVIC_PRIO_BITS
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334 /* Check the CMSIS configuration that defines the number of
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335 priority bits matches the number of priority bits actually queried
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336 from the hardware. */
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337 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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341 #ifdef configPRIO_BITS
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343 /* Check the FreeRTOS configuration that defines the number of
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344 priority bits matches the number of priority bits actually queried
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345 from the hardware. */
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346 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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350 /* Shift the priority group value back to its position within the AIRCR
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352 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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353 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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355 /* Restore the clobbered interrupt priority register to its original
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357 *pucFirstUserPriorityRegister = ulOriginalPriority;
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359 #endif /* conifgASSERT_DEFINED */
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361 /* Make PendSV and SysTick the lowest priority interrupts. */
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362 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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363 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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365 /* Start the timer that generates the tick ISR. Interrupts are disabled
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367 vPortSetupTimerInterrupt();
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369 /* Initialise the critical nesting count ready for the first task. */
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370 uxCriticalNesting = 0;
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372 /* Start the first task. */
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373 prvStartFirstTask();
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375 /* Should not get here! */
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378 /*-----------------------------------------------------------*/
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380 void vPortEndScheduler( void )
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382 /* Not implemented in ports where there is nothing to return to.
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383 Artificially force an assert. */
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384 configASSERT( uxCriticalNesting == 1000UL );
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386 /*-----------------------------------------------------------*/
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388 void vPortEnterCritical( void )
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390 portDISABLE_INTERRUPTS();
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391 uxCriticalNesting++;
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393 /* This is not the interrupt safe version of the enter critical function so
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394 assert() if it is being called from an interrupt context. Only API
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395 functions that end in "FromISR" can be used in an interrupt. Only assert if
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396 the critical nesting count is 1 to protect against recursive calls if the
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397 assert function also uses a critical section. */
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398 if( uxCriticalNesting == 1 )
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400 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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403 /*-----------------------------------------------------------*/
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405 void vPortExitCritical( void )
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407 configASSERT( uxCriticalNesting );
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408 uxCriticalNesting--;
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409 if( uxCriticalNesting == 0 )
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411 portENABLE_INTERRUPTS();
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414 /*-----------------------------------------------------------*/
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416 __asm void xPortPendSVHandler( void )
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418 extern uxCriticalNesting;
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419 extern pxCurrentTCB;
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420 extern vTaskSwitchContext;
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427 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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430 stmdb r0!, {r4-r11} /* Save the remaining registers. */
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431 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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433 stmdb sp!, {r3, r14}
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434 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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438 bl vTaskSwitchContext
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441 ldmia sp!, {r3, r14}
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444 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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445 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
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451 /*-----------------------------------------------------------*/
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453 void xPortSysTickHandler( void )
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455 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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456 executes all interrupts must be unmasked. There is therefore no need to
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457 save and then restore the interrupt mask value as its value is already
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458 known - therefore the slightly faster vPortRaiseBASEPRI() function is used
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459 in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
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460 vPortRaiseBASEPRI();
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462 /* Increment the RTOS tick. */
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463 if( xTaskIncrementTick() != pdFALSE )
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465 /* A context switch is required. Context switching is performed in
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466 the PendSV interrupt. Pend the PendSV interrupt. */
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467 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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470 vPortClearBASEPRIFromISR();
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472 /*-----------------------------------------------------------*/
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474 #if( configUSE_TICKLESS_IDLE == 1 )
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476 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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478 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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479 TickType_t xModifiableIdleTime;
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481 /* Make sure the SysTick reload value does not overflow the counter. */
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482 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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484 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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487 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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488 is accounted for as best it can be, but using the tickless mode will
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489 inevitably result in some tiny drift of the time maintained by the
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490 kernel with respect to calendar time. */
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491 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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493 /* Calculate the reload value required to wait xExpectedIdleTime
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494 tick periods. -1 is used because this code will execute part way
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495 through one of the tick periods. */
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496 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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497 if( ulReloadValue > ulStoppedTimerCompensation )
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499 ulReloadValue -= ulStoppedTimerCompensation;
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502 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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503 method as that will mask interrupts that should exit sleep mode. */
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505 __dsb( portSY_FULL_READ_WRITE );
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506 __isb( portSY_FULL_READ_WRITE );
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508 /* If a context switch is pending or a task is waiting for the scheduler
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509 to be unsuspended then abandon the low power entry. */
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510 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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512 /* Restart from whatever is left in the count register to complete
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513 this tick period. */
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514 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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516 /* Restart SysTick. */
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517 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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519 /* Reset the reload register to the value required for normal tick
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521 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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523 /* Re-enable interrupts - see comments above __disable_irq() call
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529 /* Set the new reload value. */
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530 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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532 /* Clear the SysTick count flag and set the count value back to
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534 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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536 /* Restart SysTick. */
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537 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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539 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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540 set its parameter to 0 to indicate that its implementation contains
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541 its own wait for interrupt or wait for event instruction, and so wfi
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542 should not be executed again. However, the original expected idle
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543 time variable must remain unmodified, so a copy is taken. */
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544 xModifiableIdleTime = xExpectedIdleTime;
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545 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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546 if( xModifiableIdleTime > 0 )
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548 __dsb( portSY_FULL_READ_WRITE );
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550 __isb( portSY_FULL_READ_WRITE );
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552 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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554 /* Re-enable interrupts to allow the interrupt that brought the MCU
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555 out of sleep mode to execute immediately. see comments above
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556 __disable_interrupt() call above. */
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558 __dsb( portSY_FULL_READ_WRITE );
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559 __isb( portSY_FULL_READ_WRITE );
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561 /* Disable interrupts again because the clock is about to be stopped
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562 and interrupts that execute while the clock is stopped will increase
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563 any slippage between the time maintained by the RTOS and calendar
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566 __dsb( portSY_FULL_READ_WRITE );
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567 __isb( portSY_FULL_READ_WRITE );
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569 /* Disable the SysTick clock without reading the
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570 portNVIC_SYSTICK_CTRL_REG register to ensure the
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571 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
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572 the time the SysTick is stopped for is accounted for as best it can
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573 be, but using the tickless mode will inevitably result in some tiny
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574 drift of the time maintained by the kernel with respect to calendar
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576 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
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578 /* Determine if the SysTick clock has already counted to zero and
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579 been set back to the current reload value (the reload back being
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580 correct for the entire expected idle time) or if the SysTick is yet
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581 to count to zero (in which case an interrupt other than the SysTick
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582 must have brought the system out of sleep mode). */
\r
583 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
585 uint32_t ulCalculatedLoadValue;
\r
587 /* The tick interrupt is already pending, and the SysTick count
\r
588 reloaded with ulReloadValue. Reset the
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589 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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591 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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593 /* Don't allow a tiny value, or values that have somehow
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594 underflowed because the post sleep hook did something
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595 that took too long. */
\r
596 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
598 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
601 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
603 /* As the pending tick will be processed as soon as this
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604 function exits, the tick value maintained by the tick is stepped
\r
605 forward by one less than the time spent waiting. */
\r
606 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
610 /* Something other than the tick interrupt ended the sleep.
\r
611 Work out how long the sleep lasted rounded to complete tick
\r
612 periods (not the ulReload value which accounted for part
\r
614 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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616 /* How many complete tick periods passed while the processor
\r
618 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
620 /* The reload value is set to whatever fraction of a single tick
\r
622 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
625 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
626 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
628 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
629 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
630 vTaskStepTick( ulCompleteTickPeriods );
\r
631 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
633 /* Exit with interrpts enabled. */
\r
638 #endif /* #if configUSE_TICKLESS_IDLE */
\r
640 /*-----------------------------------------------------------*/
\r
643 * Setup the SysTick timer to generate the tick interrupts at the required
\r
646 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
648 void vPortSetupTimerInterrupt( void )
\r
650 /* Calculate the constants required to configure the tick interrupt. */
\r
651 #if( configUSE_TICKLESS_IDLE == 1 )
\r
653 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
654 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
655 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
657 #endif /* configUSE_TICKLESS_IDLE */
\r
659 /* Stop and clear the SysTick. */
\r
660 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
661 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
663 /* Configure SysTick to interrupt at the requested rate. */
\r
664 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
665 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
668 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
669 /*-----------------------------------------------------------*/
\r
671 __asm uint32_t vPortGetIPSR( void )
\r
678 /*-----------------------------------------------------------*/
\r
680 #if( configASSERT_DEFINED == 1 )
\r
682 void vPortValidateInterruptPriority( void )
\r
684 uint32_t ulCurrentInterrupt;
\r
685 uint8_t ucCurrentPriority;
\r
687 /* Obtain the number of the currently executing interrupt. */
\r
688 ulCurrentInterrupt = vPortGetIPSR();
\r
690 /* Is the interrupt number a user defined interrupt? */
\r
691 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
693 /* Look up the interrupt's priority. */
\r
694 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
696 /* The following assertion will fail if a service routine (ISR) for
\r
697 an interrupt that has been assigned a priority above
\r
698 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
699 function. ISR safe FreeRTOS API functions must *only* be called
\r
700 from interrupts that have been assigned a priority at or below
\r
701 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
703 Numerically low interrupt priority numbers represent logically high
\r
704 interrupt priorities, therefore the priority of the interrupt must
\r
705 be set to a value equal to or numerically *higher* than
\r
706 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
708 Interrupts that use the FreeRTOS API must not be left at their
\r
709 default priority of zero as that is the highest possible priority,
\r
710 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
711 and therefore also guaranteed to be invalid.
\r
713 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
714 interrupt entry is as fast and simple as possible.
\r
716 The following links provide detailed information:
\r
717 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
718 http://www.freertos.org/FAQHelp.html */
\r
719 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
722 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
723 that define each interrupt's priority to be split between bits that
\r
724 define the interrupt's pre-emption priority bits and bits that define
\r
725 the interrupt's sub-priority. For simplicity all bits must be defined
\r
726 to be pre-emption priority bits. The following assertion will fail if
\r
727 this is not the case (if some bits represent a sub-priority).
\r
729 If the application only uses CMSIS libraries for interrupt
\r
730 configuration then the correct setting can be achieved on all Cortex-M
\r
731 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
732 scheduler. Note however that some vendor specific peripheral libraries
\r
733 assume a non-zero priority group setting, in which cases using a value
\r
734 of zero will result in unpredictable behaviour. */
\r
735 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
738 #endif /* configASSERT_DEFINED */
\r