2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the ARM CM3 port.
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77 *----------------------------------------------------------*/
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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83 #ifndef configKERNEL_INTERRUPT_PRIORITY
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84 #define configKERNEL_INTERRUPT_PRIORITY 255
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87 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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88 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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91 #ifndef configSYSTICK_CLOCK_HZ
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92 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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95 /* The __weak attribute does not work as you might expect with the Keil tools
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96 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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97 the application writer wants to provide their own implementation of
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98 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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100 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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101 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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104 /* Constants required to manipulate the core. Registers first... */
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105 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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106 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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107 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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108 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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109 /* ...then bits in the registers. */
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110 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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111 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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112 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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113 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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114 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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115 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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117 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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118 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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120 /* Constants required to set up the initial stack. */
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121 #define portINITIAL_XPSR ( 0x01000000 )
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123 /* Constants used with memory barrier intrinsics. */
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124 #define portSY_FULL_READ_WRITE ( 15 )
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126 /* The systick is a 24-bit counter. */
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127 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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129 /* A fiddle factor to estimate the number of SysTick counts that would have
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130 occurred while the SysTick counter is stopped during tickless idle
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132 #define portMISSED_COUNTS_FACTOR ( 45UL )
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134 /* Each task maintains its own interrupt status in the critical nesting
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136 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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139 * Setup the timer to generate the tick interrupts. The implementation in this
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140 * file is weak to allow application writers to change the timer used to
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141 * generate the tick interrupt.
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143 void vPortSetupTimerInterrupt( void );
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146 * Exception handlers.
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148 void xPortPendSVHandler( void );
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149 void xPortSysTickHandler( void );
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150 void vPortSVCHandler( void );
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153 * Start first task is a separate function so it can be tested in isolation.
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155 static void prvStartFirstTask( void );
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157 /*-----------------------------------------------------------*/
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160 * The number of SysTick increments that make up one tick period.
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162 #if configUSE_TICKLESS_IDLE == 1
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163 static unsigned long ulTimerCountsForOneTick = 0;
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164 #endif /* configUSE_TICKLESS_IDLE */
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167 * The maximum number of tick periods that can be suppressed is limited by the
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168 * 24 bit resolution of the SysTick timer.
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170 #if configUSE_TICKLESS_IDLE == 1
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171 static unsigned long xMaximumPossibleSuppressedTicks = 0;
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172 #endif /* configUSE_TICKLESS_IDLE */
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175 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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176 * power functionality only.
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178 #if configUSE_TICKLESS_IDLE == 1
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179 static unsigned long ulStoppedTimerCompensation = 0;
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180 #endif /* configUSE_TICKLESS_IDLE */
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182 /*-----------------------------------------------------------*/
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185 * See header file for description.
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187 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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189 /* Simulate the stack frame as it would be created by a context switch
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191 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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192 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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194 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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196 *pxTopOfStack = 0; /* LR */
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197 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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198 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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199 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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201 return pxTopOfStack;
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203 /*-----------------------------------------------------------*/
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205 __asm void vPortSVCHandler( void )
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209 ldr r3, =pxCurrentTCB /* Restore the context. */
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210 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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211 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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212 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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213 msr psp, r0 /* Restore the task stack pointer. */
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219 /*-----------------------------------------------------------*/
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221 __asm void prvStartFirstTask( void )
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225 /* Use the NVIC offset register to locate the stack. */
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226 ldr r0, =0xE000ED08
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229 /* Set the msp back to the start of the stack. */
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231 /* Globally enable interrupts. */
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233 /* Call SVC to start the first task. */
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237 /*-----------------------------------------------------------*/
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240 * See header file for description.
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242 portBASE_TYPE xPortStartScheduler( void )
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244 /* Make PendSV and SysTick the lowest priority interrupts. */
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245 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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246 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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248 /* Start the timer that generates the tick ISR. Interrupts are disabled
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250 vPortSetupTimerInterrupt();
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252 /* Initialise the critical nesting count ready for the first task. */
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253 uxCriticalNesting = 0;
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255 /* Start the first task. */
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256 prvStartFirstTask();
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258 /* Should not get here! */
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261 /*-----------------------------------------------------------*/
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263 void vPortEndScheduler( void )
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265 /* It is unlikely that the CM3 port will require this function as there
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266 is nothing to return to. */
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268 /*-----------------------------------------------------------*/
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270 void vPortYield( void )
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272 /* Set a PendSV to request a context switch. */
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273 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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275 /* Barriers are normally not required but do ensure the code is completely
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276 within the specified behaviour for the architecture. */
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277 __dsb( portSY_FULL_READ_WRITE );
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278 __isb( portSY_FULL_READ_WRITE );
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280 /*-----------------------------------------------------------*/
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282 void vPortEnterCritical( void )
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284 portDISABLE_INTERRUPTS();
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285 uxCriticalNesting++;
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286 __dsb( portSY_FULL_READ_WRITE );
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287 __isb( portSY_FULL_READ_WRITE );
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289 /*-----------------------------------------------------------*/
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291 void vPortExitCritical( void )
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293 uxCriticalNesting--;
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294 if( uxCriticalNesting == 0 )
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296 portENABLE_INTERRUPTS();
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299 /*-----------------------------------------------------------*/
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301 __asm void xPortPendSVHandler( void )
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303 extern uxCriticalNesting;
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304 extern pxCurrentTCB;
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305 extern vTaskSwitchContext;
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311 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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314 stmdb r0!, {r4-r11} /* Save the remaining registers. */
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315 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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317 stmdb sp!, {r3, r14}
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318 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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320 bl vTaskSwitchContext
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323 ldmia sp!, {r3, r14}
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326 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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327 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
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332 /*-----------------------------------------------------------*/
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334 void xPortSysTickHandler( void )
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336 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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337 executes all interrupts must be unmasked. There is therefore no need to
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338 save and then restore the interrupt mask value as its value is already
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340 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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342 /* Increment the RTOS tick. */
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343 if( xTaskIncrementTick() != pdFALSE )
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345 /* A context switch is required. Context switching is performed in
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346 the PendSV interrupt. Pend the PendSV interrupt. */
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347 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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350 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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352 /*-----------------------------------------------------------*/
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354 #if configUSE_TICKLESS_IDLE == 1
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356 __weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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358 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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359 portTickType xModifiableIdleTime;
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361 /* Make sure the SysTick reload value does not overflow the counter. */
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362 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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364 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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367 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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368 is accounted for as best it can be, but using the tickless mode will
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369 inevitably result in some tiny drift of the time maintained by the
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370 kernel with respect to calendar time. */
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371 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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373 /* Calculate the reload value required to wait xExpectedIdleTime
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374 tick periods. -1 is used because this code will execute part way
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375 through one of the tick periods. */
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376 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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377 if( ulReloadValue > ulStoppedTimerCompensation )
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379 ulReloadValue -= ulStoppedTimerCompensation;
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382 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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383 method as that will mask interrupts that should exit sleep mode. */
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386 /* If a context switch is pending or a task is waiting for the scheduler
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387 to be unsuspended then abandon the low power entry. */
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388 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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390 /* Restart SysTick. */
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391 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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393 /* Re-enable interrupts - see comments above __disable_irq() call
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399 /* Set the new reload value. */
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400 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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402 /* Clear the SysTick count flag and set the count value back to
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404 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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406 /* Restart SysTick. */
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407 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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409 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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410 set its parameter to 0 to indicate that its implementation contains
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411 its own wait for interrupt or wait for event instruction, and so wfi
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412 should not be executed again. However, the original expected idle
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413 time variable must remain unmodified, so a copy is taken. */
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414 xModifiableIdleTime = xExpectedIdleTime;
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415 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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416 if( xModifiableIdleTime > 0 )
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418 __dsb( portSY_FULL_READ_WRITE );
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420 __isb( portSY_FULL_READ_WRITE );
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422 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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424 /* Stop SysTick. Again, the time the SysTick is stopped for is
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425 accounted for as best it can be, but using the tickless mode will
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426 inevitably result in some tiny drift of the time maintained by the
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427 kernel with respect to calendar time. */
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428 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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430 /* Re-enable interrupts - see comments above __disable_irq() call
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434 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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436 /* The tick interrupt has already executed, and the SysTick
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437 count reloaded with ulReloadValue. Reset the
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438 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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440 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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442 /* The tick interrupt handler will already have pended the tick
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443 processing in the kernel. As the pending tick will be
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444 processed as soon as this function exits, the tick value
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445 maintained by the tick is stepped forward by one less than the
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446 time spent waiting. */
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447 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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451 /* Something other than the tick interrupt ended the sleep.
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452 Work out how long the sleep lasted rounded to complete tick
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453 periods (not the ulReload value which accounted for part
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455 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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457 /* How many complete tick periods passed while the processor
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459 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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461 /* The reload value is set to whatever fraction of a single tick
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463 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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466 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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467 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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469 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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470 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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472 vTaskStepTick( ulCompleteTickPeriods );
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474 /* The counter must start by the time the reload value is reset. */
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475 configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );
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476 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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480 #endif /* #if configUSE_TICKLESS_IDLE */
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482 /*-----------------------------------------------------------*/
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485 * Setup the SysTick timer to generate the tick interrupts at the required
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488 #if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
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490 void vPortSetupTimerInterrupt( void )
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492 /* Calculate the constants required to configure the tick interrupt. */
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493 #if configUSE_TICKLESS_IDLE == 1
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495 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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496 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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497 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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499 #endif /* configUSE_TICKLESS_IDLE */
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501 /* Configure SysTick to interrupt at the requested rate. */
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502 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
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503 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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506 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
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507 /*-----------------------------------------------------------*/
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509 __asm unsigned long ulPortSetInterruptMask( void )
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514 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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518 /*-----------------------------------------------------------*/
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520 __asm void vPortClearInterruptMask( unsigned long ulNewMask )
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