2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /*-----------------------------------------------------------
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66 * Implementation of functions defined in portable.h for the ARM CM3 port.
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67 *----------------------------------------------------------*/
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69 /* Scheduler includes. */
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70 #include "FreeRTOS.h"
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73 #ifndef configKERNEL_INTERRUPT_PRIORITY
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74 #define configKERNEL_INTERRUPT_PRIORITY 255
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77 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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78 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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81 #ifndef configSYSTICK_CLOCK_HZ
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82 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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85 /* The __weak attribute does not work as you might expect with the Keil tools
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86 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
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87 the application writer wants to provide their own implementation of
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88 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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90 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
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91 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
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94 /* Constants required to manipulate the core. Registers first... */
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95 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
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96 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
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97 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
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98 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
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99 /* ...then bits in the registers. */
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100 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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101 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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102 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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103 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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104 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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105 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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107 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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108 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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110 /* Constants required to check the validity of an interrupt priority. */
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111 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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112 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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113 #define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )
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114 #define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )
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115 #define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )
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116 #define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )
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117 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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118 #define portPRIGROUP_SHIFT ( 8UL )
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120 /* Constants required to set up the initial stack. */
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121 #define portINITIAL_XPSR ( 0x01000000 )
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123 /* Constants used with memory barrier intrinsics. */
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124 #define portSY_FULL_READ_WRITE ( 15 )
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126 /* The systick is a 24-bit counter. */
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127 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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129 /* A fiddle factor to estimate the number of SysTick counts that would have
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130 occurred while the SysTick counter is stopped during tickless idle
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132 #define portMISSED_COUNTS_FACTOR ( 45UL )
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134 /* Each task maintains its own interrupt status in the critical nesting
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136 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
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139 * Setup the timer to generate the tick interrupts. The implementation in this
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140 * file is weak to allow application writers to change the timer used to
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141 * generate the tick interrupt.
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143 void vPortSetupTimerInterrupt( void );
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146 * Exception handlers.
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148 void xPortPendSVHandler( void );
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149 void xPortSysTickHandler( void );
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150 void vPortSVCHandler( void );
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153 * Start first task is a separate function so it can be tested in isolation.
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155 static void prvStartFirstTask( void );
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157 /*-----------------------------------------------------------*/
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160 * The number of SysTick increments that make up one tick period.
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162 #if configUSE_TICKLESS_IDLE == 1
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163 static unsigned long ulTimerCountsForOneTick = 0;
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164 #endif /* configUSE_TICKLESS_IDLE */
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167 * The maximum number of tick periods that can be suppressed is limited by the
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168 * 24 bit resolution of the SysTick timer.
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170 #if configUSE_TICKLESS_IDLE == 1
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171 static unsigned long xMaximumPossibleSuppressedTicks = 0;
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172 #endif /* configUSE_TICKLESS_IDLE */
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175 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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176 * power functionality only.
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178 #if configUSE_TICKLESS_IDLE == 1
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179 static unsigned long ulStoppedTimerCompensation = 0;
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180 #endif /* configUSE_TICKLESS_IDLE */
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183 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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184 * FreeRTOS API functions are not called from interrupts that have been assigned
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185 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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187 #if ( configASSERT_DEFINED == 1 )
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188 static unsigned char ucMaxSysCallPriority = 0;
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189 static unsigned long ulMaxPRIGROUPValue = 0;
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190 static const volatile unsigned char * const pcInterruptPriorityRegisters = ( unsigned char * ) portNVIC_IP_REGISTERS_OFFSET_16;
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191 #endif /* configASSERT_DEFINED */
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193 /*-----------------------------------------------------------*/
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196 * See header file for description.
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198 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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200 /* Simulate the stack frame as it would be created by a context switch
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202 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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203 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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205 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
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207 *pxTopOfStack = 0; /* LR */
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208 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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209 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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210 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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212 return pxTopOfStack;
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214 /*-----------------------------------------------------------*/
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216 __asm void vPortSVCHandler( void )
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220 ldr r3, =pxCurrentTCB /* Restore the context. */
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221 ldr r1, [r3] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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222 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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223 ldmia r0!, {r4-r11} /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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224 msr psp, r0 /* Restore the task stack pointer. */
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230 /*-----------------------------------------------------------*/
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232 __asm void prvStartFirstTask( void )
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236 /* Use the NVIC offset register to locate the stack. */
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237 ldr r0, =0xE000ED08
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240 /* Set the msp back to the start of the stack. */
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242 /* Globally enable interrupts. */
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244 /* Call SVC to start the first task. */
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248 /*-----------------------------------------------------------*/
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251 * See header file for description.
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253 portBASE_TYPE xPortStartScheduler( void )
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255 #if( configASSERT_DEFINED == 1 )
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257 volatile unsigned long ulOriginalPriority;
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258 volatile char * const pcFirstUserPriorityRegister = ( char * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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259 volatile unsigned char ucMaxPriorityValue;
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261 /* Determine the maximum priority from which ISR safe FreeRTOS API
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262 functions can be called. ISR safe functions are those that end in
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263 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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264 ensure interrupt entry is as fast and simple as possible.
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266 Save the interrupt priority value that is about to be clobbered. */
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267 ulOriginalPriority = *pcFirstUserPriorityRegister;
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269 /* Determine the number of priority bits available. First write to all
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271 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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273 /* Read the value back to see how many bits stuck. */
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274 ucMaxPriorityValue = *pcFirstUserPriorityRegister;
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276 /* Use the same mask on the maximum system call priority. */
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277 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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279 /* Calculate the maximum acceptable priority group value for the number
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280 of bits read back. */
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281 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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282 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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284 ulMaxPRIGROUPValue--;
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285 ucMaxPriorityValue <<= ( unsigned char ) 0x01;
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288 /* Shift the priority group value back to its position within the AIRCR
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290 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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291 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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293 /* Restore the clobbered interrupt priority register to its original
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295 *pcFirstUserPriorityRegister = ulOriginalPriority;
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297 #endif /* conifgASSERT_DEFINED */
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299 /* Make PendSV and SysTick the lowest priority interrupts. */
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300 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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301 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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303 /* Start the timer that generates the tick ISR. Interrupts are disabled
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305 vPortSetupTimerInterrupt();
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307 /* Initialise the critical nesting count ready for the first task. */
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308 uxCriticalNesting = 0;
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310 /* Start the first task. */
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311 prvStartFirstTask();
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313 /* Should not get here! */
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316 /*-----------------------------------------------------------*/
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318 void vPortEndScheduler( void )
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320 /* It is unlikely that the CM3 port will require this function as there
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321 is nothing to return to. */
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323 /*-----------------------------------------------------------*/
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325 void vPortYield( void )
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327 /* Set a PendSV to request a context switch. */
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328 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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330 /* Barriers are normally not required but do ensure the code is completely
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331 within the specified behaviour for the architecture. */
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332 __dsb( portSY_FULL_READ_WRITE );
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333 __isb( portSY_FULL_READ_WRITE );
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335 /*-----------------------------------------------------------*/
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337 void vPortEnterCritical( void )
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339 portDISABLE_INTERRUPTS();
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340 uxCriticalNesting++;
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341 __dsb( portSY_FULL_READ_WRITE );
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342 __isb( portSY_FULL_READ_WRITE );
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344 /*-----------------------------------------------------------*/
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346 void vPortExitCritical( void )
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348 uxCriticalNesting--;
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349 if( uxCriticalNesting == 0 )
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351 portENABLE_INTERRUPTS();
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354 /*-----------------------------------------------------------*/
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356 __asm void xPortPendSVHandler( void )
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358 extern uxCriticalNesting;
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359 extern pxCurrentTCB;
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360 extern vTaskSwitchContext;
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366 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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369 stmdb r0!, {r4-r11} /* Save the remaining registers. */
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370 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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372 stmdb sp!, {r3, r14}
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373 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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375 bl vTaskSwitchContext
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378 ldmia sp!, {r3, r14}
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381 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
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382 ldmia r0!, {r4-r11} /* Pop the registers and the critical nesting count. */
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387 /*-----------------------------------------------------------*/
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389 void xPortSysTickHandler( void )
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391 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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392 executes all interrupts must be unmasked. There is therefore no need to
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393 save and then restore the interrupt mask value as its value is already
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395 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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397 /* Increment the RTOS tick. */
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398 if( xTaskIncrementTick() != pdFALSE )
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400 /* A context switch is required. Context switching is performed in
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401 the PendSV interrupt. Pend the PendSV interrupt. */
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402 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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405 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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407 /*-----------------------------------------------------------*/
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409 #if configUSE_TICKLESS_IDLE == 1
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411 __weak void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
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413 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
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414 portTickType xModifiableIdleTime;
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416 /* Make sure the SysTick reload value does not overflow the counter. */
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417 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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419 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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422 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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423 is accounted for as best it can be, but using the tickless mode will
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424 inevitably result in some tiny drift of the time maintained by the
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425 kernel with respect to calendar time. */
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426 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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428 /* Calculate the reload value required to wait xExpectedIdleTime
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429 tick periods. -1 is used because this code will execute part way
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430 through one of the tick periods. */
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431 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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432 if( ulReloadValue > ulStoppedTimerCompensation )
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434 ulReloadValue -= ulStoppedTimerCompensation;
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437 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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438 method as that will mask interrupts that should exit sleep mode. */
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441 /* If a context switch is pending or a task is waiting for the scheduler
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442 to be unsuspended then abandon the low power entry. */
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443 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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445 /* Restart SysTick. */
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446 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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448 /* Re-enable interrupts - see comments above __disable_irq() call
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454 /* Set the new reload value. */
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455 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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457 /* Clear the SysTick count flag and set the count value back to
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459 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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461 /* Restart SysTick. */
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462 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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464 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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465 set its parameter to 0 to indicate that its implementation contains
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466 its own wait for interrupt or wait for event instruction, and so wfi
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467 should not be executed again. However, the original expected idle
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468 time variable must remain unmodified, so a copy is taken. */
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469 xModifiableIdleTime = xExpectedIdleTime;
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470 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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471 if( xModifiableIdleTime > 0 )
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473 __dsb( portSY_FULL_READ_WRITE );
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475 __isb( portSY_FULL_READ_WRITE );
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477 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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479 /* Stop SysTick. Again, the time the SysTick is stopped for is
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480 accounted for as best it can be, but using the tickless mode will
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481 inevitably result in some tiny drift of the time maintained by the
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482 kernel with respect to calendar time. */
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483 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
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485 /* Re-enable interrupts - see comments above __disable_irq() call
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489 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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491 /* The tick interrupt has already executed, and the SysTick
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492 count reloaded with ulReloadValue. Reset the
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493 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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495 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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497 /* The tick interrupt handler will already have pended the tick
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498 processing in the kernel. As the pending tick will be
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499 processed as soon as this function exits, the tick value
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500 maintained by the tick is stepped forward by one less than the
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501 time spent waiting. */
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502 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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506 /* Something other than the tick interrupt ended the sleep.
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507 Work out how long the sleep lasted rounded to complete tick
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508 periods (not the ulReload value which accounted for part
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510 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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512 /* How many complete tick periods passed while the processor
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514 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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516 /* The reload value is set to whatever fraction of a single tick
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518 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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521 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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522 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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523 value. The critical section is used to ensure the tick interrupt
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524 can only execute once in the case that the reload register is near
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526 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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527 portENTER_CRITICAL();
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529 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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530 vTaskStepTick( ulCompleteTickPeriods );
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531 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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533 portEXIT_CRITICAL();
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537 #endif /* #if configUSE_TICKLESS_IDLE */
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539 /*-----------------------------------------------------------*/
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542 * Setup the SysTick timer to generate the tick interrupts at the required
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545 #if configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0
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547 void vPortSetupTimerInterrupt( void )
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549 /* Calculate the constants required to configure the tick interrupt. */
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550 #if configUSE_TICKLESS_IDLE == 1
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552 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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553 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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554 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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556 #endif /* configUSE_TICKLESS_IDLE */
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558 /* Configure SysTick to interrupt at the requested rate. */
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559 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
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560 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
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563 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
564 /*-----------------------------------------------------------*/
\r
566 __asm unsigned long ulPortSetInterruptMask( void )
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571 mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
575 /*-----------------------------------------------------------*/
\r
577 __asm void vPortClearInterruptMask( unsigned long ulNewMask )
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584 /*-----------------------------------------------------------*/
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586 __asm unsigned long vPortGetIPSR( void )
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593 /*-----------------------------------------------------------*/
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595 #if( configASSERT_DEFINED == 1 )
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597 void vPortValidateInterruptPriority( void )
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599 unsigned long ulCurrentInterrupt;
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600 unsigned char ucCurrentPriority;
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602 /* Obtain the number of the currently executing interrupt. */
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603 ulCurrentInterrupt = vPortGetIPSR();
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605 /* Is the interrupt number a user defined interrupt? */
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606 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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608 /* Look up the interrupt's priority. */
\r
609 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
611 /* The following assertion will fail if a service routine (ISR) for
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612 an interrupt that has been assigned a priority above
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613 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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614 function. ISR safe FreeRTOS API functions must *only* be called
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615 from interrupts that have been assigned a priority at or below
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616 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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618 Numerically low interrupt priority numbers represent logically high
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619 interrupt priorities, therefore the priority of the interrupt must
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620 be set to a value equal to or numerically *higher* than
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621 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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623 Interrupts that use the FreeRTOS API must not be left at their
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624 default priority of zero as that is the highest possible priority,
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625 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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626 and therefore also guaranteed to be invalid.
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628 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
629 interrupt entry is as fast and simple as possible.
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631 The following links provide detailed information:
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632 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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633 http://www.freertos.org/FAQHelp.html */
\r
634 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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637 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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638 that define each interrupt's priority to be split between bits that
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639 define the interrupt's pre-emption priority bits and bits that define
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640 the interrupt's sub-priority. For simplicity all bits must be defined
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641 to be pre-emption priority bits. The following assertion will fail if
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642 this is not the case (if some bits represent a sub-priority).
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644 If the application only uses CMSIS libraries for interrupt
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645 configuration then the correct setting can be achieved on all Cortex-M
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646 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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647 scheduler. Note however that some vendor specific peripheral libraries
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648 assume a non-zero priority group setting, in which cases using a value
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649 of zero will result in unpredicable behaviour. */
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650 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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653 #endif /* configASSERT_DEFINED */
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