2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM3 port.
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30 *----------------------------------------------------------*/
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32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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33 all the API functions to use the MPU wrappers. That should only be done when
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34 task.h is included from an application file. */
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35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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37 /* Scheduler includes. */
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38 #include "FreeRTOS.h"
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41 #ifndef __TARGET_FPU_VFP
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42 #error This port can only be used when the project options are configured to enable hardware floating point support.
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45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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47 /* Constants required to access and manipulate the NVIC. */
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48 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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49 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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50 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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51 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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52 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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53 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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54 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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56 /* Constants required to access and manipulate the MPU. */
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57 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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58 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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59 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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60 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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61 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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62 #define portMPU_ENABLE ( 0x01UL )
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63 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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64 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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65 #define portMPU_REGION_VALID ( 0x10UL )
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66 #define portMPU_REGION_ENABLE ( 0x01UL )
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67 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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68 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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70 /* Constants required to access and manipulate the SysTick. */
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71 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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72 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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73 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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74 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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75 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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76 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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78 /* Constants required to manipulate the VFP. */
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79 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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80 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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82 /* Constants required to set up the initial stack. */
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83 #define portINITIAL_XPSR ( 0x01000000UL )
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84 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
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85 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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86 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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88 /* Constants required to check the validity of an interrupt priority. */
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89 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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90 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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91 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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92 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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93 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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94 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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95 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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96 #define portPRIGROUP_SHIFT ( 8UL )
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98 /* Offsets in the stack to the parameters when inside the SVC handler. */
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99 #define portOFFSET_TO_PC ( 6 )
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101 /* For strict compliance with the Cortex-M spec the task start address should
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102 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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103 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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105 /* Each task maintains its own interrupt status in the critical nesting
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106 variable. Note this is not saved as part of the task context as context
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107 switches can only occur when uxCriticalNesting is zero. */
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108 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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111 * Setup the timer to generate the tick interrupts.
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113 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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116 * Configure a number of standard MPU regions that are used by all tasks.
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118 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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121 * Start first task is a separate function so it can be tested in isolation.
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123 static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
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126 * Return the smallest MPU region size that a given number of bytes will fit
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127 * into. The region size is returned as the value that should be programmed
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128 * into the region attribute register for that region.
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130 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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133 * Checks to see if being called from the context of an unprivileged task, and
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134 * if so raises the privilege level and returns false - otherwise does nothing
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135 * other than return true.
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137 BaseType_t xPortRaisePrivilege( void );
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140 * Standard FreeRTOS exception handlers.
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142 void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
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143 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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144 void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
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147 * Starts the scheduler by restoring the context of the first task to run.
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149 static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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152 * C portion of the SVC handler. The SVC handler is split between an asm entry
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153 * and a C wrapper for simplicity of coding and maintenance.
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155 void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;
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158 * Function to enable the VFP.
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160 static void vPortEnableVFP( void );
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163 * Utility function.
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165 static uint32_t prvPortGetIPSR( void );
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168 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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169 * FreeRTOS API functions are not called from interrupts that have been assigned
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170 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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172 #if ( configASSERT_DEFINED == 1 )
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173 static uint8_t ucMaxSysCallPriority = 0;
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174 static uint32_t ulMaxPRIGROUPValue = 0;
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175 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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176 #endif /* configASSERT_DEFINED */
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178 /*-----------------------------------------------------------*/
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181 * See header file for description.
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183 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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185 /* Simulate the stack frame as it would be created by a context switch
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187 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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188 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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190 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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192 *pxTopOfStack = 0; /* LR */
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193 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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194 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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196 /* A save method is being used that requires each task to maintain its
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197 own exec return value. */
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199 *pxTopOfStack = portINITIAL_EXC_RETURN;
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201 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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203 if( xRunPrivileged == pdTRUE )
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205 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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209 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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212 return pxTopOfStack;
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214 /*-----------------------------------------------------------*/
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216 void prvSVCHandler( uint32_t *pulParam )
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218 uint8_t ucSVCNumber;
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221 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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222 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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223 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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224 switch( ucSVCNumber )
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226 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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227 prvRestoreContextOfFirstTask();
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230 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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231 /* Barriers are normally not required
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232 but do ensure the code is completely
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233 within the specified behaviour for the
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235 __asm volatile( "dsb" );
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236 __asm volatile( "isb" );
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240 case portSVC_RAISE_PRIVILEGE : __asm
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242 mrs ulReg, control /* Obtain current control value. */
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243 bic ulReg, #1 /* Set privilege bit. */
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244 msr control, ulReg /* Write back new control value. */
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248 default : /* Unknown SVC call. */
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252 /*-----------------------------------------------------------*/
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254 __asm void vPortSVCHandler( void )
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256 extern prvSVCHandler
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260 /* Assumes psp was in use. */
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261 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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271 /*-----------------------------------------------------------*/
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273 __asm void prvRestoreContextOfFirstTask( void )
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277 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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280 msr msp, r0 /* Set the msp back to the start of the stack. */
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281 ldr r3, =pxCurrentTCB /* Restore the context. */
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283 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
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284 add r1, r1, #4 /* Move onto the second item in the TCB... */
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285 ldr r2, =0xe000ed9c /* Region Base Address register. */
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286 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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287 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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288 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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290 msr psp, r0 /* Restore the task stack pointer. */
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296 /*-----------------------------------------------------------*/
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299 * See header file for description.
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301 BaseType_t xPortStartScheduler( void )
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303 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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304 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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305 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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307 #if( configASSERT_DEFINED == 1 )
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309 volatile uint32_t ulOriginalPriority;
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310 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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311 volatile uint8_t ucMaxPriorityValue;
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313 /* Determine the maximum priority from which ISR safe FreeRTOS API
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314 functions can be called. ISR safe functions are those that end in
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315 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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316 ensure interrupt entry is as fast and simple as possible.
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318 Save the interrupt priority value that is about to be clobbered. */
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319 ulOriginalPriority = *pucFirstUserPriorityRegister;
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321 /* Determine the number of priority bits available. First write to all
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323 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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325 /* Read the value back to see how many bits stuck. */
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326 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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328 /* Use the same mask on the maximum system call priority. */
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329 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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331 /* Calculate the maximum acceptable priority group value for the number
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332 of bits read back. */
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333 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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334 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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336 ulMaxPRIGROUPValue--;
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337 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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340 #ifdef __NVIC_PRIO_BITS
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342 /* Check the CMSIS configuration that defines the number of
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343 priority bits matches the number of priority bits actually queried
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344 from the hardware. */
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345 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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349 #ifdef configPRIO_BITS
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351 /* Check the FreeRTOS configuration that defines the number of
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352 priority bits matches the number of priority bits actually queried
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353 from the hardware. */
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354 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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358 /* Shift the priority group value back to its position within the AIRCR
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360 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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361 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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363 /* Restore the clobbered interrupt priority register to its original
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365 *pucFirstUserPriorityRegister = ulOriginalPriority;
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367 #endif /* conifgASSERT_DEFINED */
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369 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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370 handler higher priority so it can be used to exit a critical section (where
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371 lower priorities are masked). */
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372 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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373 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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375 /* Configure the regions in the MPU that are common to all tasks. */
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378 /* Start the timer that generates the tick ISR. Interrupts are disabled
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380 prvSetupTimerInterrupt();
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382 /* Initialise the critical nesting count ready for the first task. */
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383 uxCriticalNesting = 0;
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385 /* Ensure the VFP is enabled - it should be anyway. */
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388 /* Lazy save always. */
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389 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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391 /* Start the first task. */
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392 prvStartFirstTask();
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394 /* Should not get here! */
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397 /*-----------------------------------------------------------*/
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399 __asm void prvStartFirstTask( void )
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403 /* Use the NVIC offset register to locate the stack. */
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404 ldr r0, =0xE000ED08
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407 /* Set the msp back to the start of the stack. */
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409 /* Clear the bit that indicates the FPU is in use in case the FPU was used
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410 before the scheduler was started - which would otherwise result in the
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411 unnecessary leaving of space in the SVC stack for lazy saving of FPU
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415 /* Globally enable interrupts. */
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420 svc portSVC_START_SCHEDULER /* System call to start first task. */
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425 void vPortEndScheduler( void )
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427 /* Not implemented in ports where there is nothing to return to.
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428 Artificially force an assert. */
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429 configASSERT( uxCriticalNesting == 1000UL );
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431 /*-----------------------------------------------------------*/
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433 void vPortEnterCritical( void )
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435 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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437 portDISABLE_INTERRUPTS();
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438 uxCriticalNesting++;
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440 vPortResetPrivilege( xRunningPrivileged );
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442 /*-----------------------------------------------------------*/
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444 void vPortExitCritical( void )
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446 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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448 configASSERT( uxCriticalNesting );
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449 uxCriticalNesting--;
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450 if( uxCriticalNesting == 0 )
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452 portENABLE_INTERRUPTS();
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454 vPortResetPrivilege( xRunningPrivileged );
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456 /*-----------------------------------------------------------*/
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458 __asm void xPortPendSVHandler( void )
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460 extern uxCriticalNesting;
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461 extern pxCurrentTCB;
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462 extern vTaskSwitchContext;
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468 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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471 tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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473 vstmdbeq r0!, {s16-s31}
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476 stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
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477 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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479 stmdb sp!, {r0, r3}
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480 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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484 bl vTaskSwitchContext
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487 ldmia sp!, {r0, r3}
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488 /* Restore the context. */
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490 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
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491 add r1, r1, #4 /* Move onto the second item in the TCB... */
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492 ldr r2, =0xe000ed9c /* Region Base Address register. */
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493 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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494 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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495 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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498 tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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500 vldmiaeq r0!, {s16-s31}
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506 /*-----------------------------------------------------------*/
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508 void xPortSysTickHandler( void )
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512 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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514 /* Increment the RTOS tick. */
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515 if( xTaskIncrementTick() != pdFALSE )
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517 /* Pend a context switch. */
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518 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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521 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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523 /*-----------------------------------------------------------*/
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526 * Setup the systick timer to generate the tick interrupts at the required
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529 static void prvSetupTimerInterrupt( void )
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531 /* Reset the SysTick. */
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532 portNVIC_SYSTICK_CTRL_REG = 0UL;
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533 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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535 /* Configure SysTick to interrupt at the requested rate. */
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536 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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537 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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539 /*-----------------------------------------------------------*/
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541 __asm void vPortSwitchToUserMode( void )
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550 /*-----------------------------------------------------------*/
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552 __asm void vPortEnableVFP( void )
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556 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
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559 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
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565 /*-----------------------------------------------------------*/
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567 static void prvSetupMPU( void )
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569 extern uint32_t __privileged_functions_end__;
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570 extern uint32_t __FLASH_segment_start__;
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571 extern uint32_t __FLASH_segment_end__;
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572 extern uint32_t __privileged_data_start__;
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573 extern uint32_t __privileged_data_end__;
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575 /* Check the expected MPU is present. */
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576 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
\r
578 /* First setup the entire flash for unprivileged read only access. */
\r
579 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
580 ( portMPU_REGION_VALID ) |
\r
581 ( portUNPRIVILEGED_FLASH_REGION );
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583 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
\r
584 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
585 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
586 ( portMPU_REGION_ENABLE );
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588 /* Setup the first 16K for privileged only access (even though less
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589 than 10K is actually being used). This is where the kernel code is
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591 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
592 ( portMPU_REGION_VALID ) |
\r
593 ( portPRIVILEGED_FLASH_REGION );
\r
595 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
596 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
597 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
598 ( portMPU_REGION_ENABLE );
\r
600 /* Setup the privileged data RAM region. This is where the kernel data
\r
602 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
603 ( portMPU_REGION_VALID ) |
\r
604 ( portPRIVILEGED_RAM_REGION );
\r
606 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
607 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
608 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
609 ( portMPU_REGION_ENABLE );
\r
611 /* By default allow everything to access the general peripherals. The
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612 system peripherals and registers are protected. */
\r
613 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
614 ( portMPU_REGION_VALID ) |
\r
615 ( portGENERAL_PERIPHERALS_REGION );
\r
617 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
618 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
619 ( portMPU_REGION_ENABLE );
\r
621 /* Enable the memory fault exception. */
\r
622 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
624 /* Enable the MPU with the background region configured. */
\r
625 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
628 /*-----------------------------------------------------------*/
\r
630 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
632 uint32_t ulRegionSize, ulReturnValue = 4;
\r
634 /* 32 is the smallest region size, 31 is the largest valid value for
\r
636 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
638 if( ulActualSizeInBytes <= ulRegionSize )
\r
648 /* Shift the code by one before returning so it can be written directly
\r
649 into the the correct bit position of the attribute register. */
\r
650 return ( ulReturnValue << 1UL );
\r
652 /*-----------------------------------------------------------*/
\r
654 __asm BaseType_t xPortRaisePrivilege( void )
\r
657 tst r0, #1 /* Is the task running privileged? */
\r
659 movne r0, #0 /* CONTROL[0]!=0, return false. */
\r
660 svcne portSVC_RAISE_PRIVILEGE /* Switch to privileged. */
\r
661 moveq r0, #1 /* CONTROL[0]==0, return true. */
\r
664 /*-----------------------------------------------------------*/
\r
666 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
668 extern uint32_t __SRAM_segment_start__;
\r
669 extern uint32_t __SRAM_segment_end__;
\r
670 extern uint32_t __privileged_data_start__;
\r
671 extern uint32_t __privileged_data_end__;
\r
677 if( xRegions == NULL )
\r
679 /* No MPU regions are specified so allow access to all RAM. */
\r
680 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
681 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
682 ( portMPU_REGION_VALID ) |
\r
683 ( portSTACK_REGION );
\r
685 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
686 ( portMPU_REGION_READ_WRITE ) |
\r
687 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
688 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
689 ( portMPU_REGION_ENABLE );
\r
691 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
692 just removed the privileged only parameters. */
\r
693 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
694 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
695 ( portMPU_REGION_VALID ) |
\r
696 ( portSTACK_REGION + 1 );
\r
698 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
699 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
700 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
701 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
702 ( portMPU_REGION_ENABLE );
\r
704 /* Invalidate all other regions. */
\r
705 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
707 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
708 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
713 /* This function is called automatically when the task is created - in
\r
714 which case the stack region parameters will be valid. At all other
\r
715 times the stack parameters will not be valid and it is assumed that the
\r
716 stack region has already been configured. */
\r
717 if( ulStackDepth > 0 )
\r
719 /* Define the region that allows access to the stack. */
\r
720 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
721 ( ( uint32_t ) pxBottomOfStack ) |
\r
722 ( portMPU_REGION_VALID ) |
\r
723 ( portSTACK_REGION ); /* Region number. */
\r
725 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
726 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
727 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
728 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
729 ( portMPU_REGION_ENABLE );
\r
734 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
736 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
738 /* Translate the generic region definition contained in
\r
739 xRegions into the CM3 specific MPU settings that are then
\r
740 stored in xMPUSettings. */
\r
741 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
742 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
743 ( portMPU_REGION_VALID ) |
\r
744 ( portSTACK_REGION + ul ); /* Region number. */
\r
746 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
747 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
748 ( xRegions[ lIndex ].ulParameters ) |
\r
749 ( portMPU_REGION_ENABLE );
\r
753 /* Invalidate the region. */
\r
754 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
755 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
762 /*-----------------------------------------------------------*/
\r
764 __asm uint32_t prvPortGetIPSR( void )
\r
771 /*-----------------------------------------------------------*/
\r
773 #if( configASSERT_DEFINED == 1 )
\r
775 void vPortValidateInterruptPriority( void )
\r
777 uint32_t ulCurrentInterrupt;
\r
778 uint8_t ucCurrentPriority;
\r
780 /* Obtain the number of the currently executing interrupt. */
\r
781 ulCurrentInterrupt = prvPortGetIPSR();
\r
783 /* Is the interrupt number a user defined interrupt? */
\r
784 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
786 /* Look up the interrupt's priority. */
\r
787 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
789 /* The following assertion will fail if a service routine (ISR) for
\r
790 an interrupt that has been assigned a priority above
\r
791 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
792 function. ISR safe FreeRTOS API functions must *only* be called
\r
793 from interrupts that have been assigned a priority at or below
\r
794 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
796 Numerically low interrupt priority numbers represent logically high
\r
797 interrupt priorities, therefore the priority of the interrupt must
\r
798 be set to a value equal to or numerically *higher* than
\r
799 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
801 Interrupts that use the FreeRTOS API must not be left at their
\r
802 default priority of zero as that is the highest possible priority,
\r
803 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
804 and therefore also guaranteed to be invalid.
\r
806 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
807 interrupt entry is as fast and simple as possible.
\r
809 The following links provide detailed information:
\r
810 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
811 http://www.freertos.org/FAQHelp.html */
\r
812 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
815 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
816 that define each interrupt's priority to be split between bits that
\r
817 define the interrupt's pre-emption priority bits and bits that define
\r
818 the interrupt's sub-priority. For simplicity all bits must be defined
\r
819 to be pre-emption priority bits. The following assertion will fail if
\r
820 this is not the case (if some bits represent a sub-priority).
\r
822 If the application only uses CMSIS libraries for interrupt
\r
823 configuration then the correct setting can be achieved on all Cortex-M
\r
824 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
825 scheduler. Note however that some vendor specific peripheral libraries
\r
826 assume a non-zero priority group setting, in which cases using a value
\r
827 of zero will result in unpredicable behaviour. */
\r
828 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
831 #endif /* configASSERT_DEFINED */
\r