2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM3 port.
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30 *----------------------------------------------------------*/
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32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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33 all the API functions to use the MPU wrappers. That should only be done when
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34 task.h is included from an application file. */
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35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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37 /* Scheduler includes. */
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38 #include "FreeRTOS.h"
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41 #ifndef __TARGET_FPU_VFP
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42 #error This port can only be used when the project options are configured to enable hardware floating point support.
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45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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47 /* Constants required to access and manipulate the NVIC. */
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48 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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49 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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50 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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51 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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52 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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53 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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54 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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56 /* Constants required to access and manipulate the MPU. */
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57 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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58 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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59 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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60 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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61 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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62 #define portMPU_ENABLE ( 0x01UL )
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63 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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64 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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65 #define portMPU_REGION_VALID ( 0x10UL )
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66 #define portMPU_REGION_ENABLE ( 0x01UL )
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67 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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68 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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70 /* Constants required to access and manipulate the SysTick. */
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71 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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72 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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73 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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74 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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75 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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76 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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78 /* Constants required to manipulate the VFP. */
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79 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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80 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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82 /* Constants required to set up the initial stack. */
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83 #define portINITIAL_XPSR ( 0x01000000UL )
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84 #define portINITIAL_EXC_RETURN ( 0xfffffffdUL )
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85 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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86 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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88 /* Constants required to check the validity of an interrupt priority. */
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89 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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90 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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91 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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92 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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93 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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94 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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95 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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96 #define portPRIGROUP_SHIFT ( 8UL )
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98 /* Offsets in the stack to the parameters when inside the SVC handler. */
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99 #define portOFFSET_TO_PC ( 6 )
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101 /* For strict compliance with the Cortex-M spec the task start address should
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102 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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103 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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105 /* Each task maintains its own interrupt status in the critical nesting
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106 variable. Note this is not saved as part of the task context as context
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107 switches can only occur when uxCriticalNesting is zero. */
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108 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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111 * Setup the timer to generate the tick interrupts.
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113 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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116 * Configure a number of standard MPU regions that are used by all tasks.
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118 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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121 * Start first task is a separate function so it can be tested in isolation.
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123 static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
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126 * Return the smallest MPU region size that a given number of bytes will fit
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127 * into. The region size is returned as the value that should be programmed
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128 * into the region attribute register for that region.
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130 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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133 * Standard FreeRTOS exception handlers.
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135 void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
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136 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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137 void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
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140 * Starts the scheduler by restoring the context of the first task to run.
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142 static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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145 * C portion of the SVC handler. The SVC handler is split between an asm entry
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146 * and a C wrapper for simplicity of coding and maintenance.
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148 void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;
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151 * Function to enable the VFP.
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153 static void vPortEnableVFP( void );
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156 * Utility function.
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158 static uint32_t prvPortGetIPSR( void );
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161 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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162 * FreeRTOS API functions are not called from interrupts that have been assigned
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163 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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165 #if ( configASSERT_DEFINED == 1 )
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166 static uint8_t ucMaxSysCallPriority = 0;
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167 static uint32_t ulMaxPRIGROUPValue = 0;
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168 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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169 #endif /* configASSERT_DEFINED */
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172 * @brief Checks whether or not the processor is privileged.
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174 * @return 1 if the processor is already privileged, 0 otherwise.
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176 BaseType_t xIsPrivileged( void );
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179 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
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182 * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
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183 * Bit[0] = 0 --> The processor is running privileged
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184 * Bit[0] = 1 --> The processor is running unprivileged.
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186 void vResetPrivilege( void );
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189 * @brief Calls the port specific code to raise the privilege.
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191 * @return pdFALSE if privilege was raised, pdTRUE otherwise.
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193 extern BaseType_t xPortRaisePrivilege( void );
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196 * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
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197 * code to reset the privilege, otherwise does nothing.
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199 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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200 /*-----------------------------------------------------------*/
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203 * See header file for description.
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205 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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207 /* Simulate the stack frame as it would be created by a context switch
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209 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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210 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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212 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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214 *pxTopOfStack = 0; /* LR */
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215 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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216 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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218 /* A save method is being used that requires each task to maintain its
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219 own exec return value. */
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221 *pxTopOfStack = portINITIAL_EXC_RETURN;
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223 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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225 if( xRunPrivileged == pdTRUE )
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227 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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231 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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234 return pxTopOfStack;
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236 /*-----------------------------------------------------------*/
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238 void prvSVCHandler( uint32_t *pulParam )
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240 uint8_t ucSVCNumber;
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243 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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244 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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245 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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246 switch( ucSVCNumber )
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248 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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249 prvRestoreContextOfFirstTask();
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252 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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253 /* Barriers are normally not required
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254 but do ensure the code is completely
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255 within the specified behaviour for the
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257 __asm volatile( "dsb" );
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258 __asm volatile( "isb" );
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262 case portSVC_RAISE_PRIVILEGE : __asm
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264 mrs ulReg, control /* Obtain current control value. */
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265 bic ulReg, #1 /* Set privilege bit. */
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266 msr control, ulReg /* Write back new control value. */
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270 default : /* Unknown SVC call. */
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274 /*-----------------------------------------------------------*/
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276 __asm void vPortSVCHandler( void )
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278 extern prvSVCHandler
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282 /* Assumes psp was in use. */
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283 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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293 /*-----------------------------------------------------------*/
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295 __asm void prvRestoreContextOfFirstTask( void )
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299 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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302 msr msp, r0 /* Set the msp back to the start of the stack. */
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303 ldr r3, =pxCurrentTCB /* Restore the context. */
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305 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
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306 add r1, r1, #4 /* Move onto the second item in the TCB... */
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307 ldr r2, =0xe000ed9c /* Region Base Address register. */
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308 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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309 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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310 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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312 msr psp, r0 /* Restore the task stack pointer. */
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318 /*-----------------------------------------------------------*/
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321 * See header file for description.
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323 BaseType_t xPortStartScheduler( void )
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325 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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326 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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327 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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329 #if( configASSERT_DEFINED == 1 )
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331 volatile uint32_t ulOriginalPriority;
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332 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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333 volatile uint8_t ucMaxPriorityValue;
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335 /* Determine the maximum priority from which ISR safe FreeRTOS API
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336 functions can be called. ISR safe functions are those that end in
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337 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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338 ensure interrupt entry is as fast and simple as possible.
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340 Save the interrupt priority value that is about to be clobbered. */
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341 ulOriginalPriority = *pucFirstUserPriorityRegister;
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343 /* Determine the number of priority bits available. First write to all
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345 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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347 /* Read the value back to see how many bits stuck. */
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348 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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350 /* Use the same mask on the maximum system call priority. */
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351 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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353 /* Calculate the maximum acceptable priority group value for the number
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354 of bits read back. */
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355 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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356 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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358 ulMaxPRIGROUPValue--;
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359 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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362 #ifdef __NVIC_PRIO_BITS
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364 /* Check the CMSIS configuration that defines the number of
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365 priority bits matches the number of priority bits actually queried
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366 from the hardware. */
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367 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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371 #ifdef configPRIO_BITS
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373 /* Check the FreeRTOS configuration that defines the number of
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374 priority bits matches the number of priority bits actually queried
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375 from the hardware. */
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376 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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380 /* Shift the priority group value back to its position within the AIRCR
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382 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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383 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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385 /* Restore the clobbered interrupt priority register to its original
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387 *pucFirstUserPriorityRegister = ulOriginalPriority;
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389 #endif /* conifgASSERT_DEFINED */
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391 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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392 handler higher priority so it can be used to exit a critical section (where
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393 lower priorities are masked). */
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394 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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395 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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397 /* Configure the regions in the MPU that are common to all tasks. */
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400 /* Start the timer that generates the tick ISR. Interrupts are disabled
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402 prvSetupTimerInterrupt();
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404 /* Initialise the critical nesting count ready for the first task. */
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405 uxCriticalNesting = 0;
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407 /* Ensure the VFP is enabled - it should be anyway. */
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410 /* Lazy save always. */
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411 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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413 /* Start the first task. */
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414 prvStartFirstTask();
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416 /* Should not get here! */
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419 /*-----------------------------------------------------------*/
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421 __asm void prvStartFirstTask( void )
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425 /* Use the NVIC offset register to locate the stack. */
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426 ldr r0, =0xE000ED08
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429 /* Set the msp back to the start of the stack. */
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431 /* Clear the bit that indicates the FPU is in use in case the FPU was used
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432 before the scheduler was started - which would otherwise result in the
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433 unnecessary leaving of space in the SVC stack for lazy saving of FPU
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437 /* Globally enable interrupts. */
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442 svc portSVC_START_SCHEDULER /* System call to start first task. */
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447 void vPortEndScheduler( void )
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449 /* Not implemented in ports where there is nothing to return to.
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450 Artificially force an assert. */
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451 configASSERT( uxCriticalNesting == 1000UL );
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453 /*-----------------------------------------------------------*/
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455 void vPortEnterCritical( void )
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457 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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459 portDISABLE_INTERRUPTS();
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460 uxCriticalNesting++;
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462 vPortResetPrivilege( xRunningPrivileged );
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464 /*-----------------------------------------------------------*/
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466 void vPortExitCritical( void )
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468 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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470 configASSERT( uxCriticalNesting );
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471 uxCriticalNesting--;
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472 if( uxCriticalNesting == 0 )
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474 portENABLE_INTERRUPTS();
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476 vPortResetPrivilege( xRunningPrivileged );
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478 /*-----------------------------------------------------------*/
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480 __asm void xPortPendSVHandler( void )
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482 extern uxCriticalNesting;
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483 extern pxCurrentTCB;
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484 extern vTaskSwitchContext;
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490 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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493 tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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495 vstmdbeq r0!, {s16-s31}
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498 stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
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499 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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501 stmdb sp!, {r0, r3}
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502 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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506 bl vTaskSwitchContext
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509 ldmia sp!, {r0, r3}
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510 /* Restore the context. */
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512 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
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513 add r1, r1, #4 /* Move onto the second item in the TCB... */
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514 ldr r2, =0xe000ed9c /* Region Base Address register. */
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515 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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516 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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517 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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520 tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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522 vldmiaeq r0!, {s16-s31}
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528 /*-----------------------------------------------------------*/
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530 void xPortSysTickHandler( void )
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534 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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536 /* Increment the RTOS tick. */
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537 if( xTaskIncrementTick() != pdFALSE )
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539 /* Pend a context switch. */
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540 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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543 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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545 /*-----------------------------------------------------------*/
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548 * Setup the systick timer to generate the tick interrupts at the required
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551 static void prvSetupTimerInterrupt( void )
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553 /* Reset the SysTick. */
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554 portNVIC_SYSTICK_CTRL_REG = 0UL;
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555 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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557 /* Configure SysTick to interrupt at the requested rate. */
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558 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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559 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
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561 /*-----------------------------------------------------------*/
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563 __asm void vPortSwitchToUserMode( void )
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572 /*-----------------------------------------------------------*/
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574 __asm void vPortEnableVFP( void )
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578 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
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581 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
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587 /*-----------------------------------------------------------*/
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589 static void prvSetupMPU( void )
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591 extern uint32_t __privileged_functions_end__;
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592 extern uint32_t __FLASH_segment_start__;
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593 extern uint32_t __FLASH_segment_end__;
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594 extern uint32_t __privileged_data_start__;
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595 extern uint32_t __privileged_data_end__;
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597 /* Check the expected MPU is present. */
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598 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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600 /* First setup the entire flash for unprivileged read only access. */
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601 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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602 ( portMPU_REGION_VALID ) |
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603 ( portUNPRIVILEGED_FLASH_REGION );
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605 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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606 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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607 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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608 ( portMPU_REGION_ENABLE );
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610 /* Setup the first 16K for privileged only access (even though less
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611 than 10K is actually being used). This is where the kernel code is
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613 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
614 ( portMPU_REGION_VALID ) |
\r
615 ( portPRIVILEGED_FLASH_REGION );
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617 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
618 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
619 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
620 ( portMPU_REGION_ENABLE );
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622 /* Setup the privileged data RAM region. This is where the kernel data
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624 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
625 ( portMPU_REGION_VALID ) |
\r
626 ( portPRIVILEGED_RAM_REGION );
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628 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
629 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
630 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
631 ( portMPU_REGION_ENABLE );
\r
633 /* By default allow everything to access the general peripherals. The
\r
634 system peripherals and registers are protected. */
\r
635 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
636 ( portMPU_REGION_VALID ) |
\r
637 ( portGENERAL_PERIPHERALS_REGION );
\r
639 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
640 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
641 ( portMPU_REGION_ENABLE );
\r
643 /* Enable the memory fault exception. */
\r
644 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
646 /* Enable the MPU with the background region configured. */
\r
647 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
650 /*-----------------------------------------------------------*/
\r
652 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
654 uint32_t ulRegionSize, ulReturnValue = 4;
\r
656 /* 32 is the smallest region size, 31 is the largest valid value for
\r
658 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
660 if( ulActualSizeInBytes <= ulRegionSize )
\r
670 /* Shift the code by one before returning so it can be written directly
\r
671 into the the correct bit position of the attribute register. */
\r
672 return ( ulReturnValue << 1UL );
\r
674 /*-----------------------------------------------------------*/
\r
676 __asm BaseType_t xIsPrivileged( void )
\r
680 mrs r0, control /* r0 = CONTROL. */
\r
681 tst r0, #1 /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
\r
683 movne r0, #0 /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
\r
684 moveq r0, #1 /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
\r
685 bx lr /* Return. */
\r
687 /*-----------------------------------------------------------*/
\r
689 __asm void vResetPrivilege( void )
\r
693 mrs r0, control /* r0 = CONTROL. */
\r
694 orrs r0, #1 /* r0 = r0 | 1. */
\r
695 msr control, r0 /* CONTROL = r0. */
\r
696 bx lr /* Return. */
\r
698 /*-----------------------------------------------------------*/
\r
700 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
702 extern uint32_t __SRAM_segment_start__;
\r
703 extern uint32_t __SRAM_segment_end__;
\r
704 extern uint32_t __privileged_data_start__;
\r
705 extern uint32_t __privileged_data_end__;
\r
711 if( xRegions == NULL )
\r
713 /* No MPU regions are specified so allow access to all RAM. */
\r
714 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
715 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
716 ( portMPU_REGION_VALID ) |
\r
717 ( portSTACK_REGION );
\r
719 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
720 ( portMPU_REGION_READ_WRITE ) |
\r
721 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
722 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
723 ( portMPU_REGION_ENABLE );
\r
725 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
726 just removed the privileged only parameters. */
\r
727 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
728 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
729 ( portMPU_REGION_VALID ) |
\r
730 ( portSTACK_REGION + 1 );
\r
732 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
733 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
734 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
735 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
736 ( portMPU_REGION_ENABLE );
\r
738 /* Invalidate all other regions. */
\r
739 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
741 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
742 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
747 /* This function is called automatically when the task is created - in
\r
748 which case the stack region parameters will be valid. At all other
\r
749 times the stack parameters will not be valid and it is assumed that the
\r
750 stack region has already been configured. */
\r
751 if( ulStackDepth > 0 )
\r
753 /* Define the region that allows access to the stack. */
\r
754 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
755 ( ( uint32_t ) pxBottomOfStack ) |
\r
756 ( portMPU_REGION_VALID ) |
\r
757 ( portSTACK_REGION ); /* Region number. */
\r
759 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
760 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
761 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
762 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
763 ( portMPU_REGION_ENABLE );
\r
768 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
770 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
772 /* Translate the generic region definition contained in
\r
773 xRegions into the CM3 specific MPU settings that are then
\r
774 stored in xMPUSettings. */
\r
775 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
776 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
777 ( portMPU_REGION_VALID ) |
\r
778 ( portSTACK_REGION + ul ); /* Region number. */
\r
780 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
781 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
782 ( xRegions[ lIndex ].ulParameters ) |
\r
783 ( portMPU_REGION_ENABLE );
\r
787 /* Invalidate the region. */
\r
788 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
789 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
796 /*-----------------------------------------------------------*/
\r
798 __asm uint32_t prvPortGetIPSR( void )
\r
805 /*-----------------------------------------------------------*/
\r
807 #if( configASSERT_DEFINED == 1 )
\r
809 void vPortValidateInterruptPriority( void )
\r
811 uint32_t ulCurrentInterrupt;
\r
812 uint8_t ucCurrentPriority;
\r
814 /* Obtain the number of the currently executing interrupt. */
\r
815 ulCurrentInterrupt = prvPortGetIPSR();
\r
817 /* Is the interrupt number a user defined interrupt? */
\r
818 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
820 /* Look up the interrupt's priority. */
\r
821 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
823 /* The following assertion will fail if a service routine (ISR) for
\r
824 an interrupt that has been assigned a priority above
\r
825 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
826 function. ISR safe FreeRTOS API functions must *only* be called
\r
827 from interrupts that have been assigned a priority at or below
\r
828 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
830 Numerically low interrupt priority numbers represent logically high
\r
831 interrupt priorities, therefore the priority of the interrupt must
\r
832 be set to a value equal to or numerically *higher* than
\r
833 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
835 Interrupts that use the FreeRTOS API must not be left at their
\r
836 default priority of zero as that is the highest possible priority,
\r
837 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
838 and therefore also guaranteed to be invalid.
\r
840 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
841 interrupt entry is as fast and simple as possible.
\r
843 The following links provide detailed information:
\r
844 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
845 http://www.freertos.org/FAQHelp.html */
\r
846 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
849 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
850 that define each interrupt's priority to be split between bits that
\r
851 define the interrupt's pre-emption priority bits and bits that define
\r
852 the interrupt's sub-priority. For simplicity all bits must be defined
\r
853 to be pre-emption priority bits. The following assertion will fail if
\r
854 this is not the case (if some bits represent a sub-priority).
\r
856 If the application only uses CMSIS libraries for interrupt
\r
857 configuration then the correct setting can be achieved on all Cortex-M
\r
858 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
859 scheduler. Note however that some vendor specific peripheral libraries
\r
860 assume a non-zero priority group setting, in which cases using a value
\r
861 of zero will result in unpredicable behaviour. */
\r
862 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
865 #endif /* configASSERT_DEFINED */
\r