2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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75 all the API functions to use the MPU wrappers. That should only be done when
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76 task.h is included from an application file. */
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77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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82 #include "event_groups.h"
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83 #include "mpu_prototypes.h"
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85 #ifndef __TARGET_FPU_VFP
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86 #error This port can only be used when the project options are configured to enable hardware floating point support.
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89 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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91 /* Constants required to access and manipulate the NVIC. */
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92 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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93 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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95 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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96 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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97 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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98 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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100 /* Constants required to access and manipulate the MPU. */
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101 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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102 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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103 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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104 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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105 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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106 #define portMPU_ENABLE ( 0x01UL )
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107 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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108 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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109 #define portMPU_REGION_VALID ( 0x10UL )
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110 #define portMPU_REGION_ENABLE ( 0x01UL )
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111 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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112 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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114 /* Constants required to access and manipulate the SysTick. */
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115 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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116 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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117 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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118 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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119 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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120 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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122 /* Constants required to manipulate the VFP. */
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123 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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124 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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126 /* Constants required to set up the initial stack. */
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127 #define portINITIAL_XPSR ( 0x01000000UL )
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128 #define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
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129 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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130 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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132 /* Constants required to check the validity of an interrupt priority. */
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133 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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134 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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135 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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136 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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137 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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138 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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139 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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140 #define portPRIGROUP_SHIFT ( 8UL )
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142 /* Offsets in the stack to the parameters when inside the SVC handler. */
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143 #define portOFFSET_TO_PC ( 6 )
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145 /* For strict compliance with the Cortex-M spec the task start address should
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146 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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147 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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149 /* Each task maintains its own interrupt status in the critical nesting
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150 variable. Note this is not saved as part of the task context as context
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151 switches can only occur when uxCriticalNesting is zero. */
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152 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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155 * Setup the timer to generate the tick interrupts.
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157 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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160 * Configure a number of standard MPU regions that are used by all tasks.
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162 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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165 * Start first task is a separate function so it can be tested in isolation.
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167 static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
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170 * Return the smallest MPU region size that a given number of bytes will fit
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171 * into. The region size is returned as the value that should be programmed
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172 * into the region attribute register for that region.
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174 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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177 * Checks to see if being called from the context of an unprivileged task, and
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178 * if so raises the privilege level and returns false - otherwise does nothing
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179 * other than return true.
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181 BaseType_t xPortRaisePrivilege( void );
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184 * Standard FreeRTOS exception handlers.
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186 void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
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187 void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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188 void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
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191 * Starts the scheduler by restoring the context of the first task to run.
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193 static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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196 * C portion of the SVC handler. The SVC handler is split between an asm entry
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197 * and a C wrapper for simplicity of coding and maintenance.
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199 void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;
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202 * Function to enable the VFP.
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204 static void vPortEnableVFP( void );
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207 * Utility function.
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209 static uint32_t prvPortGetIPSR( void );
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212 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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213 * FreeRTOS API functions are not called from interrupts that have been assigned
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214 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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216 #if ( configASSERT_DEFINED == 1 )
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217 static uint8_t ucMaxSysCallPriority = 0;
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218 static uint32_t ulMaxPRIGROUPValue = 0;
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219 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
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220 #endif /* configASSERT_DEFINED */
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222 /*-----------------------------------------------------------*/
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225 * See header file for description.
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227 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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229 /* Simulate the stack frame as it would be created by a context switch
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231 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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232 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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234 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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236 *pxTopOfStack = 0; /* LR */
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237 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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238 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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240 /* A save method is being used that requires each task to maintain its
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241 own exec return value. */
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243 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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245 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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247 if( xRunPrivileged == pdTRUE )
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249 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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253 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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256 return pxTopOfStack;
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258 /*-----------------------------------------------------------*/
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260 void prvSVCHandler( uint32_t *pulParam )
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262 uint8_t ucSVCNumber;
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265 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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266 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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267 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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268 switch( ucSVCNumber )
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270 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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271 prvRestoreContextOfFirstTask();
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274 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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275 /* Barriers are normally not required
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276 but do ensure the code is completely
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277 within the specified behaviour for the
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279 __asm volatile( "dsb" );
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280 __asm volatile( "isb" );
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284 case portSVC_RAISE_PRIVILEGE : __asm
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286 mrs ulReg, control /* Obtain current control value. */
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287 bic ulReg, #1 /* Set privilege bit. */
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288 msr control, ulReg /* Write back new control value. */
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292 default : /* Unknown SVC call. */
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296 /*-----------------------------------------------------------*/
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298 __asm void vPortSVCHandler( void )
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300 extern prvSVCHandler
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304 /* Assumes psp was in use. */
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305 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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315 /*-----------------------------------------------------------*/
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317 __asm void prvRestoreContextOfFirstTask( void )
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321 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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324 msr msp, r0 /* Set the msp back to the start of the stack. */
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325 ldr r3, =pxCurrentTCB /* Restore the context. */
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327 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
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328 add r1, r1, #4 /* Move onto the second item in the TCB... */
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329 ldr r2, =0xe000ed9c /* Region Base Address register. */
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330 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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331 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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332 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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334 msr psp, r0 /* Restore the task stack pointer. */
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340 /*-----------------------------------------------------------*/
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343 * See header file for description.
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345 BaseType_t xPortStartScheduler( void )
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347 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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348 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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349 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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351 #if( configASSERT_DEFINED == 1 )
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353 volatile uint32_t ulOriginalPriority;
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354 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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355 volatile uint8_t ucMaxPriorityValue;
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357 /* Determine the maximum priority from which ISR safe FreeRTOS API
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358 functions can be called. ISR safe functions are those that end in
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359 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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360 ensure interrupt entry is as fast and simple as possible.
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362 Save the interrupt priority value that is about to be clobbered. */
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363 ulOriginalPriority = *pucFirstUserPriorityRegister;
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365 /* Determine the number of priority bits available. First write to all
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367 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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369 /* Read the value back to see how many bits stuck. */
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370 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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372 /* Use the same mask on the maximum system call priority. */
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373 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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375 /* Calculate the maximum acceptable priority group value for the number
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376 of bits read back. */
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377 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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378 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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380 ulMaxPRIGROUPValue--;
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381 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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384 /* Shift the priority group value back to its position within the AIRCR
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386 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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387 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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389 /* Restore the clobbered interrupt priority register to its original
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391 *pucFirstUserPriorityRegister = ulOriginalPriority;
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393 #endif /* conifgASSERT_DEFINED */
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395 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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396 handler higher priority so it can be used to exit a critical section (where
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397 lower priorities are masked). */
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398 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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399 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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401 /* Configure the regions in the MPU that are common to all tasks. */
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404 /* Start the timer that generates the tick ISR. Interrupts are disabled
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406 prvSetupTimerInterrupt();
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408 /* Initialise the critical nesting count ready for the first task. */
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409 uxCriticalNesting = 0;
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411 /* Ensure the VFP is enabled - it should be anyway. */
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414 /* Lazy save always. */
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415 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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417 /* Start the first task. */
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418 prvStartFirstTask();
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420 /* Should not get here! */
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423 /*-----------------------------------------------------------*/
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425 __asm void prvStartFirstTask( void )
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429 ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
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432 msr msp, r0 /* Set the msp back to the start of the stack. */
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433 cpsie i /* Globally enable interrupts. */
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437 svc portSVC_START_SCHEDULER /* System call to start first task. */
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442 void vPortEndScheduler( void )
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444 /* Not implemented in ports where there is nothing to return to.
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445 Artificially force an assert. */
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446 configASSERT( uxCriticalNesting == 1000UL );
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448 /*-----------------------------------------------------------*/
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450 void vPortEnterCritical( void )
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452 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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454 portDISABLE_INTERRUPTS();
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455 uxCriticalNesting++;
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457 vPortResetPrivilege( xRunningPrivileged );
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459 /*-----------------------------------------------------------*/
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461 void vPortExitCritical( void )
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463 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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465 configASSERT( uxCriticalNesting );
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466 uxCriticalNesting--;
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467 if( uxCriticalNesting == 0 )
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469 portENABLE_INTERRUPTS();
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471 vPortResetPrivilege( xRunningPrivileged );
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473 /*-----------------------------------------------------------*/
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475 __asm void xPortPendSVHandler( void )
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477 extern uxCriticalNesting;
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478 extern pxCurrentTCB;
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479 extern vTaskSwitchContext;
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485 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
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488 tst r14, #0x10 /* Is the task using the FPU context? If so, push high vfp registers. */
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490 vstmdbeq r0!, {s16-s31}
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493 stmdb r0!, {r1, r4-r11, r14} /* Save the remaining registers. */
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494 str r0, [r2] /* Save the new top of stack into the first member of the TCB. */
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495 clrex /* Ensure thread safety of atomic operations. */
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498 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
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502 bl vTaskSwitchContext
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506 /* Restore the context. */
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508 ldr r0, [r1] /* The first item in the TCB is the task top of stack. */
\r
509 add r1, r1, #4 /* Move onto the second item in the TCB... */
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510 ldr r2, =0xe000ed9c /* Region Base Address register. */
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511 ldmia r1!, {r4-r11} /* Read 4 sets of MPU registers. */
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512 stmia r2!, {r4-r11} /* Write 4 sets of MPU registers. */
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513 ldmia r0!, {r3-r11, r14} /* Pop the registers that are not automatically saved on exception entry. */
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516 tst r14, #0x10 /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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518 vldmiaeq r0!, {s16-s31}
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524 /*-----------------------------------------------------------*/
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526 void xPortSysTickHandler( void )
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530 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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532 /* Increment the RTOS tick. */
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533 if( xTaskIncrementTick() != pdFALSE )
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535 /* Pend a context switch. */
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536 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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539 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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541 /*-----------------------------------------------------------*/
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544 * Setup the systick timer to generate the tick interrupts at the required
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547 static void prvSetupTimerInterrupt( void )
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549 /* Reset the SysTick. */
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550 portNVIC_SYSTICK_CTRL_REG = 0UL;
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551 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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553 /* Configure SysTick to interrupt at the requested rate. */
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554 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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555 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
\r
557 /*-----------------------------------------------------------*/
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559 __asm void vPortSwitchToUserMode( void )
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568 /*-----------------------------------------------------------*/
\r
570 __asm void vPortEnableVFP( void )
\r
574 ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
\r
577 orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
\r
583 /*-----------------------------------------------------------*/
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585 static void prvSetupMPU( void )
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587 extern uint32_t __privileged_functions_end__;
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588 extern uint32_t __FLASH_segment_start__;
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589 extern uint32_t __FLASH_segment_end__;
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590 extern uint32_t __privileged_data_start__;
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591 extern uint32_t __privileged_data_end__;
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593 /* Check the expected MPU is present. */
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594 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
\r
596 /* First setup the entire flash for unprivileged read only access. */
\r
597 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
598 ( portMPU_REGION_VALID ) |
\r
599 ( portUNPRIVILEGED_FLASH_REGION );
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601 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
\r
602 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
603 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
604 ( portMPU_REGION_ENABLE );
\r
606 /* Setup the first 16K for privileged only access (even though less
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607 than 10K is actually being used). This is where the kernel code is
\r
609 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
610 ( portMPU_REGION_VALID ) |
\r
611 ( portPRIVILEGED_FLASH_REGION );
\r
613 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
614 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
615 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
616 ( portMPU_REGION_ENABLE );
\r
618 /* Setup the privileged data RAM region. This is where the kernel data
\r
620 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
621 ( portMPU_REGION_VALID ) |
\r
622 ( portPRIVILEGED_RAM_REGION );
\r
624 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
625 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
626 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
627 ( portMPU_REGION_ENABLE );
\r
629 /* By default allow everything to access the general peripherals. The
\r
630 system peripherals and registers are protected. */
\r
631 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
632 ( portMPU_REGION_VALID ) |
\r
633 ( portGENERAL_PERIPHERALS_REGION );
\r
635 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
636 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
637 ( portMPU_REGION_ENABLE );
\r
639 /* Enable the memory fault exception. */
\r
640 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
642 /* Enable the MPU with the background region configured. */
\r
643 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
646 /*-----------------------------------------------------------*/
\r
648 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
650 uint32_t ulRegionSize, ulReturnValue = 4;
\r
652 /* 32 is the smallest region size, 31 is the largest valid value for
\r
654 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
656 if( ulActualSizeInBytes <= ulRegionSize )
\r
666 /* Shift the code by one before returning so it can be written directly
\r
667 into the the correct bit position of the attribute register. */
\r
668 return ( ulReturnValue << 1UL );
\r
670 /*-----------------------------------------------------------*/
\r
672 __asm BaseType_t xPortRaisePrivilege( void )
\r
675 tst r0, #1 /* Is the task running privileged? */
\r
677 movne r0, #0 /* CONTROL[0]!=0, return false. */
\r
678 svcne portSVC_RAISE_PRIVILEGE /* Switch to privileged. */
\r
679 moveq r0, #1 /* CONTROL[0]==0, return true. */
\r
682 /*-----------------------------------------------------------*/
\r
684 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
686 extern uint32_t __SRAM_segment_start__;
\r
687 extern uint32_t __SRAM_segment_end__;
\r
688 extern uint32_t __privileged_data_start__;
\r
689 extern uint32_t __privileged_data_end__;
\r
695 if( xRegions == NULL )
\r
697 /* No MPU regions are specified so allow access to all RAM. */
\r
698 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
699 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
700 ( portMPU_REGION_VALID ) |
\r
701 ( portSTACK_REGION );
\r
703 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
704 ( portMPU_REGION_READ_WRITE ) |
\r
705 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
706 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
707 ( portMPU_REGION_ENABLE );
\r
709 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
710 just removed the privileged only parameters. */
\r
711 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
712 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
713 ( portMPU_REGION_VALID ) |
\r
714 ( portSTACK_REGION + 1 );
\r
716 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
717 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
718 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
719 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
720 ( portMPU_REGION_ENABLE );
\r
722 /* Invalidate all other regions. */
\r
723 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
725 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
726 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
731 /* This function is called automatically when the task is created - in
\r
732 which case the stack region parameters will be valid. At all other
\r
733 times the stack parameters will not be valid and it is assumed that the
\r
734 stack region has already been configured. */
\r
735 if( ulStackDepth > 0 )
\r
737 /* Define the region that allows access to the stack. */
\r
738 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
739 ( ( uint32_t ) pxBottomOfStack ) |
\r
740 ( portMPU_REGION_VALID ) |
\r
741 ( portSTACK_REGION ); /* Region number. */
\r
743 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
744 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
745 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
746 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
747 ( portMPU_REGION_ENABLE );
\r
752 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
754 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
756 /* Translate the generic region definition contained in
\r
757 xRegions into the CM3 specific MPU settings that are then
\r
758 stored in xMPUSettings. */
\r
759 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
760 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
761 ( portMPU_REGION_VALID ) |
\r
762 ( portSTACK_REGION + ul ); /* Region number. */
\r
764 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
765 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
766 ( xRegions[ lIndex ].ulParameters ) |
\r
767 ( portMPU_REGION_ENABLE );
\r
771 /* Invalidate the region. */
\r
772 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
773 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
780 /*-----------------------------------------------------------*/
\r
782 __asm uint32_t prvPortGetIPSR( void )
\r
789 /*-----------------------------------------------------------*/
\r
791 #if( configASSERT_DEFINED == 1 )
\r
793 void vPortValidateInterruptPriority( void )
\r
795 uint32_t ulCurrentInterrupt;
\r
796 uint8_t ucCurrentPriority;
\r
798 /* Obtain the number of the currently executing interrupt. */
\r
799 ulCurrentInterrupt = prvPortGetIPSR();
\r
801 /* Is the interrupt number a user defined interrupt? */
\r
802 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
804 /* Look up the interrupt's priority. */
\r
805 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
807 /* The following assertion will fail if a service routine (ISR) for
\r
808 an interrupt that has been assigned a priority above
\r
809 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
810 function. ISR safe FreeRTOS API functions must *only* be called
\r
811 from interrupts that have been assigned a priority at or below
\r
812 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
814 Numerically low interrupt priority numbers represent logically high
\r
815 interrupt priorities, therefore the priority of the interrupt must
\r
816 be set to a value equal to or numerically *higher* than
\r
817 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
819 Interrupts that use the FreeRTOS API must not be left at their
\r
820 default priority of zero as that is the highest possible priority,
\r
821 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
822 and therefore also guaranteed to be invalid.
\r
824 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
825 interrupt entry is as fast and simple as possible.
\r
827 The following links provide detailed information:
\r
828 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
829 http://www.freertos.org/FAQHelp.html */
\r
830 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
833 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
834 that define each interrupt's priority to be split between bits that
\r
835 define the interrupt's pre-emption priority bits and bits that define
\r
836 the interrupt's sub-priority. For simplicity all bits must be defined
\r
837 to be pre-emption priority bits. The following assertion will fail if
\r
838 this is not the case (if some bits represent a sub-priority).
\r
840 If the application only uses CMSIS libraries for interrupt
\r
841 configuration then the correct setting can be achieved on all Cortex-M
\r
842 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
843 scheduler. Note however that some vendor specific peripheral libraries
\r
844 assume a non-zero priority group setting, in which cases using a value
\r
845 of zero will result in unpredicable behaviour. */
\r
846 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
849 #endif /* configASSERT_DEFINED */
\r