2 * FreeRTOS Kernel V10.2.1
\r
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /*-----------------------------------------------------------
\r
29 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
30 *----------------------------------------------------------*/
\r
32 /* Scheduler includes. */
\r
33 #include "FreeRTOS.h"
\r
36 #ifndef __TARGET_FPU_VFP
\r
37 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
40 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
\r
41 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
\r
44 #ifndef configSYSTICK_CLOCK_HZ
\r
45 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
46 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
47 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
49 /* The way the SysTick is clocked is not modified in case it is not the same
\r
51 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
54 /* The __weak attribute does not work as you might expect with the Keil tools
\r
55 so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
\r
56 the application writer wants to provide their own implementation of
\r
57 vPortSetupTimerInterrupt(). Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
59 #ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
\r
60 #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
\r
63 /* Constants required to manipulate the core. Registers first... */
\r
64 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
65 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
66 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
67 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
68 /* ...then bits in the registers. */
\r
69 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
70 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
71 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
72 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
73 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
75 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
76 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
78 /* Constants required to check the validity of an interrupt priority. */
\r
79 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
80 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
81 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
82 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
83 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
84 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
85 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
86 #define portPRIGROUP_SHIFT ( 8UL )
\r
88 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
89 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
91 /* Constants required to manipulate the VFP. */
\r
92 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
93 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
95 /* Constants required to set up the initial stack. */
\r
96 #define portINITIAL_XPSR ( 0x01000000 )
\r
97 #define portINITIAL_EXC_RETURN ( 0xfffffffd )
\r
99 /* The systick is a 24-bit counter. */
\r
100 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
102 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
103 occurred while the SysTick counter is stopped during tickless idle
\r
105 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
107 /* For strict compliance with the Cortex-M spec the task start address should
\r
108 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
109 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
112 * Setup the timer to generate the tick interrupts. The implementation in this
\r
113 * file is weak to allow application writers to change the timer used to
\r
114 * generate the tick interrupt.
\r
116 void vPortSetupTimerInterrupt( void );
\r
119 * Exception handlers.
\r
121 void xPortPendSVHandler( void );
\r
122 void xPortSysTickHandler( void );
\r
123 void vPortSVCHandler( void );
\r
126 * Start first task is a separate function so it can be tested in isolation.
\r
128 static void prvStartFirstTask( void );
\r
131 * Functions defined in portasm.s to enable the VFP.
\r
133 static void prvEnableVFP( void );
\r
136 * Used to catch tasks that attempt to return from their implementing function.
\r
138 static void prvTaskExitError( void );
\r
140 /*-----------------------------------------------------------*/
\r
142 /* Each task maintains its own interrupt status in the critical nesting
\r
144 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
147 * The number of SysTick increments that make up one tick period.
\r
149 #if( configUSE_TICKLESS_IDLE == 1 )
\r
150 static uint32_t ulTimerCountsForOneTick = 0;
\r
151 #endif /* configUSE_TICKLESS_IDLE */
\r
154 * The maximum number of tick periods that can be suppressed is limited by the
\r
155 * 24 bit resolution of the SysTick timer.
\r
157 #if( configUSE_TICKLESS_IDLE == 1 )
\r
158 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
159 #endif /* configUSE_TICKLESS_IDLE */
\r
162 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
163 * power functionality only.
\r
165 #if( configUSE_TICKLESS_IDLE == 1 )
\r
166 static uint32_t ulStoppedTimerCompensation = 0;
\r
167 #endif /* configUSE_TICKLESS_IDLE */
\r
170 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
171 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
172 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
174 #if ( configASSERT_DEFINED == 1 )
\r
175 static uint8_t ucMaxSysCallPriority = 0;
\r
176 static uint32_t ulMaxPRIGROUPValue = 0;
\r
177 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
178 #endif /* configASSERT_DEFINED */
\r
180 /*-----------------------------------------------------------*/
\r
183 * See header file for description.
\r
185 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
187 /* Simulate the stack frame as it would be created by a context switch
\r
190 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
191 of interrupts, and to ensure alignment. */
\r
194 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
196 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
198 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
\r
200 /* Save code space by skipping register initialisation. */
\r
201 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
202 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
204 /* A save method is being used that requires each task to maintain its
\r
205 own exec return value. */
\r
207 *pxTopOfStack = portINITIAL_EXC_RETURN;
\r
209 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
211 return pxTopOfStack;
\r
213 /*-----------------------------------------------------------*/
\r
215 static void prvTaskExitError( void )
\r
217 /* A function that implements a task must not exit or attempt to return to
\r
218 its caller as there is nothing to return to. If a task wants to exit it
\r
219 should instead call vTaskDelete( NULL ).
\r
221 Artificially force an assert() to be triggered if configASSERT() is
\r
222 defined, then stop here so application writers can catch the error. */
\r
223 configASSERT( uxCriticalNesting == ~0UL );
\r
224 portDISABLE_INTERRUPTS();
\r
227 /*-----------------------------------------------------------*/
\r
229 __asm void vPortSVCHandler( void )
\r
233 /* Get the location of the current TCB. */
\r
234 ldr r3, =pxCurrentTCB
\r
237 /* Pop the core registers. */
\r
238 ldmia r0!, {r4-r11, r14}
\r
245 /*-----------------------------------------------------------*/
\r
247 __asm void prvStartFirstTask( void )
\r
251 /* Use the NVIC offset register to locate the stack. */
\r
252 ldr r0, =0xE000ED08
\r
255 /* Set the msp back to the start of the stack. */
\r
257 /* Clear the bit that indicates the FPU is in use in case the FPU was used
\r
258 before the scheduler was started - which would otherwise result in the
\r
259 unnecessary leaving of space in the SVC stack for lazy saving of FPU
\r
263 /* Globally enable interrupts. */
\r
268 /* Call SVC to start the first task. */
\r
273 /*-----------------------------------------------------------*/
\r
275 __asm void prvEnableVFP( void )
\r
279 /* The FPU enable bits are in the CPACR. */
\r
280 ldr.w r0, =0xE000ED88
\r
283 /* Enable CP10 and CP11 coprocessors, then save back. */
\r
284 orr r1, r1, #( 0xf << 20 )
\r
289 /*-----------------------------------------------------------*/
\r
292 * See header file for description.
\r
294 BaseType_t xPortStartScheduler( void )
\r
296 #if( configASSERT_DEFINED == 1 )
\r
298 volatile uint32_t ulOriginalPriority;
\r
299 volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
300 volatile uint8_t ucMaxPriorityValue;
\r
302 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
303 functions can be called. ISR safe functions are those that end in
\r
304 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
305 ensure interrupt entry is as fast and simple as possible.
\r
307 Save the interrupt priority value that is about to be clobbered. */
\r
308 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
310 /* Determine the number of priority bits available. First write to all
\r
312 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
314 /* Read the value back to see how many bits stuck. */
\r
315 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
317 /* The kernel interrupt priority should be set to the lowest
\r
319 configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
\r
321 /* Use the same mask on the maximum system call priority. */
\r
322 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
324 /* Calculate the maximum acceptable priority group value for the number
\r
325 of bits read back. */
\r
326 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
327 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
329 ulMaxPRIGROUPValue--;
\r
330 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
333 #ifdef __NVIC_PRIO_BITS
\r
335 /* Check the CMSIS configuration that defines the number of
\r
336 priority bits matches the number of priority bits actually queried
\r
337 from the hardware. */
\r
338 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
342 #ifdef configPRIO_BITS
\r
344 /* Check the FreeRTOS configuration that defines the number of
\r
345 priority bits matches the number of priority bits actually queried
\r
346 from the hardware. */
\r
347 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
351 /* Shift the priority group value back to its position within the AIRCR
\r
353 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
354 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
356 /* Restore the clobbered interrupt priority register to its original
\r
358 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
360 #endif /* conifgASSERT_DEFINED */
\r
362 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
363 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
364 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
366 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
368 vPortSetupTimerInterrupt();
\r
370 /* Initialise the critical nesting count ready for the first task. */
\r
371 uxCriticalNesting = 0;
\r
373 /* Ensure the VFP is enabled - it should be anyway. */
\r
376 /* Lazy save always. */
\r
377 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
379 /* Start the first task. */
\r
380 prvStartFirstTask();
\r
382 /* Should not get here! */
\r
385 /*-----------------------------------------------------------*/
\r
387 void vPortEndScheduler( void )
\r
389 /* Not implemented in ports where there is nothing to return to.
\r
390 Artificially force an assert. */
\r
391 configASSERT( uxCriticalNesting == 1000UL );
\r
393 /*-----------------------------------------------------------*/
\r
395 void vPortEnterCritical( void )
\r
397 portDISABLE_INTERRUPTS();
\r
398 uxCriticalNesting++;
\r
400 /* This is not the interrupt safe version of the enter critical function so
\r
401 assert() if it is being called from an interrupt context. Only API
\r
402 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
403 the critical nesting count is 1 to protect against recursive calls if the
\r
404 assert function also uses a critical section. */
\r
405 if( uxCriticalNesting == 1 )
\r
407 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
410 /*-----------------------------------------------------------*/
\r
412 void vPortExitCritical( void )
\r
414 configASSERT( uxCriticalNesting );
\r
415 uxCriticalNesting--;
\r
416 if( uxCriticalNesting == 0 )
\r
418 portENABLE_INTERRUPTS();
\r
421 /*-----------------------------------------------------------*/
\r
423 __asm void xPortPendSVHandler( void )
\r
425 extern uxCriticalNesting;
\r
426 extern pxCurrentTCB;
\r
427 extern vTaskSwitchContext;
\r
433 /* Get the location of the current TCB. */
\r
434 ldr r3, =pxCurrentTCB
\r
437 /* Is the task using the FPU context? If so, push high vfp registers. */
\r
440 vstmdbeq r0!, {s16-s31}
\r
442 /* Save the core registers. */
\r
443 stmdb r0!, {r4-r11, r14}
\r
445 /* Save the new top of stack into the first member of the TCB. */
\r
448 stmdb sp!, {r0, r3}
\r
449 mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
455 bl vTaskSwitchContext
\r
458 ldmia sp!, {r0, r3}
\r
460 /* The first item in pxCurrentTCB is the task top of stack. */
\r
464 /* Pop the core registers. */
\r
465 ldmia r0!, {r4-r11, r14}
\r
467 /* Is the task using the FPU context? If so, pop the high vfp registers
\r
471 vldmiaeq r0!, {s16-s31}
\r
475 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
\r
476 #if WORKAROUND_PMU_CM001 == 1
\r
485 /*-----------------------------------------------------------*/
\r
487 void xPortSysTickHandler( void )
\r
489 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
490 executes all interrupts must be unmasked. There is therefore no need to
\r
491 save and then restore the interrupt mask value as its value is already
\r
492 known - therefore the slightly faster vPortRaiseBASEPRI() function is used
\r
493 in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
\r
494 vPortRaiseBASEPRI();
\r
496 /* Increment the RTOS tick. */
\r
497 if( xTaskIncrementTick() != pdFALSE )
\r
499 /* A context switch is required. Context switching is performed in
\r
500 the PendSV interrupt. Pend the PendSV interrupt. */
\r
501 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
504 vPortClearBASEPRIFromISR();
\r
506 /*-----------------------------------------------------------*/
\r
508 #if( configUSE_TICKLESS_IDLE == 1 )
\r
510 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
512 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
513 TickType_t xModifiableIdleTime;
\r
515 /* Make sure the SysTick reload value does not overflow the counter. */
\r
516 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
518 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
521 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
522 is accounted for as best it can be, but using the tickless mode will
\r
523 inevitably result in some tiny drift of the time maintained by the
\r
524 kernel with respect to calendar time. */
\r
525 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
527 /* Calculate the reload value required to wait xExpectedIdleTime
\r
528 tick periods. -1 is used because this code will execute part way
\r
529 through one of the tick periods. */
\r
530 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
531 if( ulReloadValue > ulStoppedTimerCompensation )
\r
533 ulReloadValue -= ulStoppedTimerCompensation;
\r
536 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
537 method as that will mask interrupts that should exit sleep mode. */
\r
539 __dsb( portSY_FULL_READ_WRITE );
\r
540 __isb( portSY_FULL_READ_WRITE );
\r
542 /* If a context switch is pending or a task is waiting for the scheduler
\r
543 to be unsuspended then abandon the low power entry. */
\r
544 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
546 /* Restart from whatever is left in the count register to complete
\r
547 this tick period. */
\r
548 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
550 /* Restart SysTick. */
\r
551 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
553 /* Reset the reload register to the value required for normal tick
\r
555 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
557 /* Re-enable interrupts - see comments above __disable_irq() call
\r
563 /* Set the new reload value. */
\r
564 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
566 /* Clear the SysTick count flag and set the count value back to
\r
568 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
570 /* Restart SysTick. */
\r
571 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
573 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
574 set its parameter to 0 to indicate that its implementation contains
\r
575 its own wait for interrupt or wait for event instruction, and so wfi
\r
576 should not be executed again. However, the original expected idle
\r
577 time variable must remain unmodified, so a copy is taken. */
\r
578 xModifiableIdleTime = xExpectedIdleTime;
\r
579 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
580 if( xModifiableIdleTime > 0 )
\r
582 __dsb( portSY_FULL_READ_WRITE );
\r
584 __isb( portSY_FULL_READ_WRITE );
\r
586 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
588 /* Re-enable interrupts to allow the interrupt that brought the MCU
\r
589 out of sleep mode to execute immediately. see comments above
\r
590 __disable_interrupt() call above. */
\r
592 __dsb( portSY_FULL_READ_WRITE );
\r
593 __isb( portSY_FULL_READ_WRITE );
\r
595 /* Disable interrupts again because the clock is about to be stopped
\r
596 and interrupts that execute while the clock is stopped will increase
\r
597 any slippage between the time maintained by the RTOS and calendar
\r
600 __dsb( portSY_FULL_READ_WRITE );
\r
601 __isb( portSY_FULL_READ_WRITE );
\r
603 /* Disable the SysTick clock without reading the
\r
604 portNVIC_SYSTICK_CTRL_REG register to ensure the
\r
605 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
\r
606 the time the SysTick is stopped for is accounted for as best it can
\r
607 be, but using the tickless mode will inevitably result in some tiny
\r
608 drift of the time maintained by the kernel with respect to calendar
\r
610 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
612 /* Determine if the SysTick clock has already counted to zero and
\r
613 been set back to the current reload value (the reload back being
\r
614 correct for the entire expected idle time) or if the SysTick is yet
\r
615 to count to zero (in which case an interrupt other than the SysTick
\r
616 must have brought the system out of sleep mode). */
\r
617 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
619 uint32_t ulCalculatedLoadValue;
\r
621 /* The tick interrupt is already pending, and the SysTick count
\r
622 reloaded with ulReloadValue. Reset the
\r
623 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
625 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
627 /* Don't allow a tiny value, or values that have somehow
\r
628 underflowed because the post sleep hook did something
\r
629 that took too long. */
\r
630 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
632 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
635 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
637 /* As the pending tick will be processed as soon as this
\r
638 function exits, the tick value maintained by the tick is stepped
\r
639 forward by one less than the time spent waiting. */
\r
640 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
644 /* Something other than the tick interrupt ended the sleep.
\r
645 Work out how long the sleep lasted rounded to complete tick
\r
646 periods (not the ulReload value which accounted for part
\r
648 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
650 /* How many complete tick periods passed while the processor
\r
652 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
654 /* The reload value is set to whatever fraction of a single tick
\r
656 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
659 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
660 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
662 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
663 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
664 vTaskStepTick( ulCompleteTickPeriods );
\r
665 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
667 /* Exit with interrpts enabled. */
\r
672 #endif /* #if configUSE_TICKLESS_IDLE */
\r
674 /*-----------------------------------------------------------*/
\r
677 * Setup the SysTick timer to generate the tick interrupts at the required
\r
680 #if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
\r
682 void vPortSetupTimerInterrupt( void )
\r
684 /* Calculate the constants required to configure the tick interrupt. */
\r
685 #if( configUSE_TICKLESS_IDLE == 1 )
\r
687 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
688 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
689 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
691 #endif /* configUSE_TICKLESS_IDLE */
\r
693 /* Stop and clear the SysTick. */
\r
694 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
695 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
697 /* Configure SysTick to interrupt at the requested rate. */
\r
698 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
699 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
702 #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
\r
703 /*-----------------------------------------------------------*/
\r
705 __asm uint32_t vPortGetIPSR( void )
\r
712 /*-----------------------------------------------------------*/
\r
714 #if( configASSERT_DEFINED == 1 )
\r
716 void vPortValidateInterruptPriority( void )
\r
718 uint32_t ulCurrentInterrupt;
\r
719 uint8_t ucCurrentPriority;
\r
721 /* Obtain the number of the currently executing interrupt. */
\r
722 ulCurrentInterrupt = vPortGetIPSR();
\r
724 /* Is the interrupt number a user defined interrupt? */
\r
725 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
727 /* Look up the interrupt's priority. */
\r
728 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
730 /* The following assertion will fail if a service routine (ISR) for
\r
731 an interrupt that has been assigned a priority above
\r
732 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
733 function. ISR safe FreeRTOS API functions must *only* be called
\r
734 from interrupts that have been assigned a priority at or below
\r
735 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
737 Numerically low interrupt priority numbers represent logically high
\r
738 interrupt priorities, therefore the priority of the interrupt must
\r
739 be set to a value equal to or numerically *higher* than
\r
740 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
742 Interrupts that use the FreeRTOS API must not be left at their
\r
743 default priority of zero as that is the highest possible priority,
\r
744 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
745 and therefore also guaranteed to be invalid.
\r
747 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
748 interrupt entry is as fast and simple as possible.
\r
750 The following links provide detailed information:
\r
751 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
752 http://www.freertos.org/FAQHelp.html */
\r
753 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
756 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
757 that define each interrupt's priority to be split between bits that
\r
758 define the interrupt's pre-emption priority bits and bits that define
\r
759 the interrupt's sub-priority. For simplicity all bits must be defined
\r
760 to be pre-emption priority bits. The following assertion will fail if
\r
761 this is not the case (if some bits represent a sub-priority).
\r
763 If the application only uses CMSIS libraries for interrupt
\r
764 configuration then the correct setting can be achieved on all Cortex-M
\r
765 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
766 scheduler. Note however that some vendor specific peripheral libraries
\r
767 assume a non-zero priority group setting, in which cases using a value
\r
768 of zero will result in unpredictable behaviour. */
\r
769 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
772 #endif /* configASSERT_DEFINED */
\r