2 * FreeRTOS Kernel V10.1.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 /*-----------------------------------------------------------
\r
29 * Implementation of functions defined in portable.h for the RX100 port.
\r
30 *----------------------------------------------------------*/
\r
32 /* Standard C includes. */
\r
35 /* Scheduler includes. */
\r
36 #include "FreeRTOS.h"
\r
39 /* Library includes. */
\r
42 /* Hardware specifics. */
\r
43 #include "iodefine.h"
\r
45 /*-----------------------------------------------------------*/
\r
47 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
\r
48 PSW is set with U and I set, and PM and IPL clear. */
\r
49 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
\r
51 /* The peripheral clock is divided by this value before being supplying the
\r
53 #if ( configUSE_TICKLESS_IDLE == 0 )
\r
54 /* If tickless idle is not used then the divisor can be fixed. */
\r
55 #define portCLOCK_DIVISOR 8UL
\r
56 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
\r
57 #define portCLOCK_DIVISOR 512UL
\r
58 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
\r
59 #define portCLOCK_DIVISOR 128UL
\r
60 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
\r
61 #define portCLOCK_DIVISOR 32UL
\r
63 #define portCLOCK_DIVISOR 8UL
\r
67 /* Keys required to lock and unlock access to certain system registers
\r
69 #define portUNLOCK_KEY 0xA50B
\r
70 #define portLOCK_KEY 0xA500
\r
72 /*-----------------------------------------------------------*/
\r
74 /* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
\r
75 and therefore installed in the vector table, when the FreeRTOS code is built
\r
77 extern BaseType_t vSoftwareInterruptEntry;
\r
78 const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
\r
80 /*-----------------------------------------------------------*/
\r
83 * Function to start the first task executing - written in asm code as direct
\r
84 * access to registers is required.
\r
86 static void prvStartFirstTask( void );
\r
89 * Software interrupt handler. Performs the actual context switch (saving and
\r
90 * restoring of registers). Written in asm code as direct register access is
\r
93 static void prvYieldHandler( void );
\r
96 * The entry point for the software interrupt handler. This is the function
\r
97 * that calls the inline asm function prvYieldHandler(). It is installed in
\r
98 * the vector table, but the code that installs it is in prvYieldHandler rather
\r
99 * than using a #pragma.
\r
101 void vSoftwareInterruptISR( void );
\r
104 * Sets up the periodic ISR used for the RTOS tick using the CMT.
\r
105 * The application writer can define configSETUP_TICK_INTERRUPT() (in
\r
106 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
\r
107 * in place of prvSetupTimerInterrupt().
\r
109 static void prvSetupTimerInterrupt( void );
\r
110 #ifndef configSETUP_TICK_INTERRUPT
\r
111 /* The user has not provided their own tick interrupt configuration so use
\r
112 the definition in this file (which uses the interval timer). */
\r
113 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
\r
114 #endif /* configSETUP_TICK_INTERRUPT */
\r
117 * Called after the sleep mode registers have been configured, prvSleep()
\r
118 * executes the pre and post sleep macros, and actually calls the wait
\r
121 #if configUSE_TICKLESS_IDLE == 1
\r
122 static void prvSleep( TickType_t xExpectedIdleTime );
\r
123 #endif /* configUSE_TICKLESS_IDLE */
\r
125 /*-----------------------------------------------------------*/
\r
127 /* These is accessed by the inline assembler functions. */
\r
128 extern void *pxCurrentTCB;
\r
129 extern void vTaskSwitchContext( void );
\r
131 /*-----------------------------------------------------------*/
\r
133 /* Calculate how many clock increments make up a single tick period. */
\r
134 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
136 #if configUSE_TICKLESS_IDLE == 1
\r
138 /* Holds the maximum number of ticks that can be suppressed - which is
\r
139 basically how far into the future an interrupt can be generated. Set
\r
140 during initialisation. This is the maximum possible value that the
\r
141 compare match register can hold divided by ulMatchValueForOneTick. */
\r
142 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
144 /* Flag set from the tick interrupt to allow the sleep processing to know if
\r
145 sleep mode was exited because of a tick interrupt, or an interrupt
\r
146 generated by something else. */
\r
147 static volatile uint32_t ulTickFlag = pdFALSE;
\r
149 /* The CMT counter is stopped temporarily each time it is re-programmed.
\r
150 The following constant offsets the CMT counter match value by the number of
\r
151 CMT counts that would typically be missed while the counter was stopped to
\r
152 compensate for the lost time. The large difference between the divided CMT
\r
153 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
\r
154 equal zero - and be optimised away. */
\r
155 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
\r
159 /*-----------------------------------------------------------*/
\r
162 * See header file for description.
\r
164 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
166 /* Offset to end up on 8 byte boundary. */
\r
169 /* R0 is not included as it is the stack pointer. */
\r
170 *pxTopOfStack = 0x00;
\r
172 *pxTopOfStack = 0x00;
\r
174 *pxTopOfStack = portINITIAL_PSW;
\r
176 *pxTopOfStack = ( StackType_t ) pxCode;
\r
178 /* When debugging it can be useful if every register is set to a known
\r
179 value. Otherwise code space can be saved by just setting the registers
\r
180 that need to be set. */
\r
181 #ifdef USE_FULL_REGISTER_INITIALISATION
\r
184 *pxTopOfStack = 0x12345678; /* r15. */
\r
186 *pxTopOfStack = 0xaaaabbbb;
\r
188 *pxTopOfStack = 0xdddddddd;
\r
190 *pxTopOfStack = 0xcccccccc;
\r
192 *pxTopOfStack = 0xbbbbbbbb;
\r
194 *pxTopOfStack = 0xaaaaaaaa;
\r
196 *pxTopOfStack = 0x99999999;
\r
198 *pxTopOfStack = 0x88888888;
\r
200 *pxTopOfStack = 0x77777777;
\r
202 *pxTopOfStack = 0x66666666;
\r
204 *pxTopOfStack = 0x55555555;
\r
206 *pxTopOfStack = 0x44444444;
\r
208 *pxTopOfStack = 0x33333333;
\r
210 *pxTopOfStack = 0x22222222;
\r
215 /* Leave space for the registers that will get popped from the stack
\r
216 when the task first starts executing. */
\r
217 pxTopOfStack -= 15;
\r
221 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
\r
223 *pxTopOfStack = 0x12345678; /* Accumulator. */
\r
225 *pxTopOfStack = 0x87654321; /* Accumulator. */
\r
227 return pxTopOfStack;
\r
229 /*-----------------------------------------------------------*/
\r
231 BaseType_t xPortStartScheduler( void )
\r
233 /* Use pxCurrentTCB just so it does not get optimised away. */
\r
234 if( pxCurrentTCB != NULL )
\r
236 /* Call an application function to set up the timer that will generate
\r
237 the tick interrupt. This way the application can decide which
\r
238 peripheral to use. If tickless mode is used then the default
\r
239 implementation defined in this file (which uses CMT0) should not be
\r
241 configSETUP_TICK_INTERRUPT();
\r
243 /* Enable the software interrupt. */
\r
244 _IEN( _ICU_SWINT ) = 1;
\r
246 /* Ensure the software interrupt is clear. */
\r
247 _IR( _ICU_SWINT ) = 0;
\r
249 /* Ensure the software interrupt is set to the kernel priority. */
\r
250 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
252 /* Start the first task. */
\r
253 prvStartFirstTask();
\r
256 /* Execution should not reach here as the tasks are now running!
\r
257 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
\r
258 a warning about a statically declared function not being referenced in the
\r
259 case that the application writer has provided their own tick interrupt
\r
260 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
\r
261 their own routine will be called in place of prvSetupTimerInterrupt()). */
\r
262 prvSetupTimerInterrupt();
\r
264 /* Just to make sure the function is not optimised away. */
\r
265 ( void ) vSoftwareInterruptISR();
\r
267 /* Should not get here. */
\r
270 /*-----------------------------------------------------------*/
\r
272 #pragma inline_asm prvStartFirstTask
\r
273 static void prvStartFirstTask( void )
\r
275 /* When starting the scheduler there is nothing that needs moving to the
\r
276 interrupt stack because the function is not called from an interrupt.
\r
277 Just ensure the current stack is the user stack. */
\r
280 /* Obtain the location of the stack associated with which ever task
\r
281 pxCurrentTCB is currently pointing to. */
\r
282 MOV.L #_pxCurrentTCB, R15
\r
286 /* Restore the registers from the stack of the task pointed to by
\r
289 MVTACLO R15 /* Accumulator low 32 bits. */
\r
291 MVTACHI R15 /* Accumulator high 32 bits. */
\r
292 POPM R1-R15 /* R1 to R15 - R0 is not included as it is the SP. */
\r
293 RTE /* This pops the remaining registers. */
\r
297 /*-----------------------------------------------------------*/
\r
299 #pragma interrupt ( prvTickISR( vect = configTICK_VECTOR, enable ) )
\r
300 void prvTickISR( void )
\r
302 /* Increment the tick, and perform any processing the new tick value
\r
304 set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
306 if( xTaskIncrementTick() != pdFALSE )
\r
311 set_ipl( configKERNEL_INTERRUPT_PRIORITY );
\r
313 #if configUSE_TICKLESS_IDLE == 1
\r
315 /* The CPU woke because of a tick. */
\r
316 ulTickFlag = pdTRUE;
\r
318 /* If this is the first tick since exiting tickless mode then the CMT
\r
319 compare match value needs resetting. */
\r
320 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
\r
324 /*-----------------------------------------------------------*/
\r
326 void vSoftwareInterruptISR( void )
\r
330 /*-----------------------------------------------------------*/
\r
332 #pragma inline_asm prvYieldHandler
\r
333 static void prvYieldHandler( void )
\r
335 /* Re-enable interrupts. */
\r
338 /* Move the data that was automatically pushed onto the interrupt stack
\r
339 when the interrupt occurred from the interrupt stack to the user stack.
\r
341 R15 is saved before it is clobbered. */
\r
344 /* Read the user stack pointer. */
\r
347 /* Move the address down to the data being moved. */
\r
351 /* Copy the data across. */
\r
352 MOV.L [ R0 ], [ R15 ] ; R15
\r
353 MOV.L 4[ R0 ], 4[ R15 ] ; PC
\r
354 MOV.L 8[ R0 ], 8[ R15 ] ; PSW
\r
356 /* Move the interrupt stack pointer to its new correct position. */
\r
359 /* All the rest of the registers are saved directly to the user stack. */
\r
362 /* Save the rest of the general registers (R15 has been saved already). */
\r
365 /* Save the accumulator. */
\r
368 MVFACMI R15 ; Middle order word.
\r
369 SHLL #16, R15 ; Shifted left as it is restored to the low order word.
\r
372 /* Save the stack pointer to the TCB. */
\r
373 MOV.L #_pxCurrentTCB, R15
\r
377 /* Ensure the interrupt mask is set to the syscall priority while the
\r
378 kernel structures are being accessed. */
\r
379 MVTIPL #configMAX_SYSCALL_INTERRUPT_PRIORITY
\r
381 /* Select the next task to run. */
\r
382 BSR.A _vTaskSwitchContext
\r
384 /* Reset the interrupt mask as no more data structure access is
\r
386 MVTIPL #configKERNEL_INTERRUPT_PRIORITY
\r
388 /* Load the stack pointer of the task that is now selected as the Running
\r
389 state task from its TCB. */
\r
390 MOV.L #_pxCurrentTCB,R15
\r
394 /* Restore the context of the new task. The PSW (Program Status Word) and
\r
395 PC will be popped by the RTE instruction. */
\r
405 /*-----------------------------------------------------------*/
\r
407 void vPortEndScheduler( void )
\r
409 /* Not implemented in ports where there is nothing to return to.
\r
410 Artificially force an assert. */
\r
411 configASSERT( pxCurrentTCB == NULL );
\r
413 /* The following line is just to prevent the symbol getting optimised away. */
\r
414 ( void ) vTaskSwitchContext();
\r
416 /*-----------------------------------------------------------*/
\r
418 static void prvSetupTimerInterrupt( void )
\r
421 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
427 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
429 /* Interrupt on compare match. */
\r
430 CMT0.CMCR.BIT.CMIE = 1;
\r
432 /* Set the compare match value. */
\r
433 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
\r
435 /* Divide the PCLK. */
\r
436 #if portCLOCK_DIVISOR == 512
\r
438 CMT0.CMCR.BIT.CKS = 3;
\r
440 #elif portCLOCK_DIVISOR == 128
\r
442 CMT0.CMCR.BIT.CKS = 2;
\r
444 #elif portCLOCK_DIVISOR == 32
\r
446 CMT0.CMCR.BIT.CKS = 1;
\r
448 #elif portCLOCK_DIVISOR == 8
\r
450 CMT0.CMCR.BIT.CKS = 0;
\r
454 #error Invalid portCLOCK_DIVISOR setting
\r
459 /* Enable the interrupt... */
\r
460 _IEN( _CMT0_CMI0 ) = 1;
\r
462 /* ...and set its priority to the application defined kernel priority. */
\r
463 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
\r
465 /* Start the timer. */
\r
466 CMT.CMSTR0.BIT.STR0 = 1;
\r
468 /*-----------------------------------------------------------*/
\r
470 #if configUSE_TICKLESS_IDLE == 1
\r
472 static void prvSleep( TickType_t xExpectedIdleTime )
\r
474 /* Allow the application to define some pre-sleep processing. */
\r
475 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
\r
477 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
\r
478 means the application defined code has already executed the WAIT
\r
480 if( xExpectedIdleTime > 0 )
\r
485 /* Allow the application to define some post sleep processing. */
\r
486 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
489 #endif /* configUSE_TICKLESS_IDLE */
\r
490 /*-----------------------------------------------------------*/
\r
492 #if configUSE_TICKLESS_IDLE == 1
\r
494 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
496 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
\r
497 eSleepModeStatus eSleepAction;
\r
499 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
\r
501 /* Make sure the CMT reload value does not overflow the counter. */
\r
502 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
504 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
507 /* Calculate the reload value required to wait xExpectedIdleTime tick
\r
509 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
\r
510 if( ulMatchValue > ulStoppedTimerCompensation )
\r
512 /* Compensate for the fact that the CMT is going to be stopped
\r
514 ulMatchValue -= ulStoppedTimerCompensation;
\r
517 /* Stop the CMT momentarily. The time the CMT is stopped for is
\r
518 accounted for as best it can be, but using the tickless mode will
\r
519 inevitably result in some tiny drift of the time maintained by the
\r
520 kernel with respect to calendar time. */
\r
521 CMT.CMSTR0.BIT.STR0 = 0;
\r
522 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
524 /* Nothing to do here. */
\r
527 /* Critical section using the global interrupt bit as the i bit is
\r
528 automatically reset by the WAIT instruction. */
\r
531 /* The tick flag is set to false before sleeping. If it is true when
\r
532 sleep mode is exited then sleep mode was probably exited because the
\r
533 tick was suppressed for the entire xExpectedIdleTime period. */
\r
534 ulTickFlag = pdFALSE;
\r
536 /* If a context switch is pending then abandon the low power entry as
\r
537 the context switch might have been pended by an external interrupt that
\r
538 requires processing. */
\r
539 eSleepAction = eTaskConfirmSleepModeStatus();
\r
540 if( eSleepAction == eAbortSleep )
\r
542 /* Restart tick. */
\r
543 CMT.CMSTR0.BIT.STR0 = 1;
\r
546 else if( eSleepAction == eNoTasksWaitingTimeout )
\r
548 /* Protection off. */
\r
549 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
551 /* Ready for software standby with all clocks stopped. */
\r
552 SYSTEM.SBYCR.BIT.SSBY = 1;
\r
554 /* Protection on. */
\r
555 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
557 /* Sleep until something happens. Calling prvSleep() will
\r
558 automatically reset the i bit in the PSW. */
\r
559 prvSleep( xExpectedIdleTime );
\r
561 /* Restart the CMT. */
\r
562 CMT.CMSTR0.BIT.STR0 = 1;
\r
566 /* Protection off. */
\r
567 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
569 /* Ready for deep sleep mode. */
\r
570 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
\r
571 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
\r
572 SYSTEM.SBYCR.BIT.SSBY = 0;
\r
574 /* Protection on. */
\r
575 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
577 /* Adjust the match value to take into account that the current
\r
578 time slice is already partially complete. */
\r
579 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
\r
580 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
582 /* Restart the CMT to count up to the new match value. */
\r
584 CMT.CMSTR0.BIT.STR0 = 1;
\r
586 /* Sleep until something happens. Calling prvSleep() will
\r
587 automatically reset the i bit in the PSW. */
\r
588 prvSleep( xExpectedIdleTime );
\r
590 /* Stop CMT. Again, the time the SysTick is stopped for is
\r
591 accounted for as best it can be, but using the tickless mode will
\r
592 inevitably result in some tiny drift of the time maintained by the
\r
593 kernel with respect to calendar time. */
\r
594 CMT.CMSTR0.BIT.STR0 = 0;
\r
595 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
597 /* Nothing to do here. */
\r
600 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
\r
602 if( ulTickFlag != pdFALSE )
\r
604 /* The tick interrupt has already executed, although because
\r
605 this function is called with the scheduler suspended the actual
\r
606 tick processing will not occur until after this function has
\r
607 exited. Reset the match value with whatever remains of this
\r
609 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
610 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
612 /* The tick interrupt handler will already have pended the tick
\r
613 processing in the kernel. As the pending tick will be
\r
614 processed as soon as this function exits, the tick value
\r
615 maintained by the tick is stepped forward by one less than the
\r
616 time spent sleeping. The actual stepping of the tick appears
\r
617 later in this function. */
\r
618 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
622 /* Something other than the tick interrupt ended the sleep.
\r
623 How many complete tick periods passed while the processor was
\r
625 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
627 /* The match value is set to whatever fraction of a single tick
\r
629 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
630 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
633 /* Restart the CMT so it runs up to the match value. The match value
\r
634 will get set to the value required to generate exactly one tick period
\r
635 the next time the CMT interrupt executes. */
\r
637 CMT.CMSTR0.BIT.STR0 = 1;
\r
639 /* Wind the tick forward by the number of tick periods that the CPU
\r
640 remained in a low power state. */
\r
641 vTaskStepTick( ulCompleteTickPeriods );
\r
645 #endif /* configUSE_TICKLESS_IDLE */
\r