2 * Some constants, hardware definitions and comments taken from ST's HAL driver
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3 * library, COPYRIGHT(c) 2015 STMicroelectronics.
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7 * FreeRTOS+TCP 191100 experimental
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8 * Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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10 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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11 * this software and associated documentation files (the "Software"), to deal in
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12 * the Software without restriction, including without limitation the rights to
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13 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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14 * the Software, and to permit persons to whom the Software is furnished to do so,
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15 * subject to the following conditions:
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17 * The above copyright notice and this permission notice shall be included in all
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18 * copies or substantial portions of the Software.
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20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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22 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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23 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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24 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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25 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 * http://www.FreeRTOS.org
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28 * http://aws.amazon.com/freertos
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30 * 1 tab == 4 spaces!
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33 /* Standard includes. */
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38 /* FreeRTOS includes. */
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39 #include "FreeRTOS.h"
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44 /* FreeRTOS+TCP includes. */
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45 #include "FreeRTOS_IP.h"
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46 #include "FreeRTOS_Sockets.h"
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47 #include "FreeRTOS_IP_Private.h"
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48 #include "FreeRTOS_DNS.h"
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49 #include "NetworkBufferManagement.h"
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50 #include "NetworkInterface.h"
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52 #include "phyHandling.h"
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56 #include "stm32f7xx_hal.h"
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58 #include "stm32f4xx_hal.h"
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61 /* Interrupt events to process. Currently only the Rx event is processed
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62 although code for other events is included to allow for possible future
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64 #define EMAC_IF_RX_EVENT 1UL
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65 #define EMAC_IF_TX_EVENT 2UL
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66 #define EMAC_IF_ERR_EVENT 4UL
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67 #define EMAC_IF_ALL_EVENT ( EMAC_IF_RX_EVENT | EMAC_IF_TX_EVENT | EMAC_IF_ERR_EVENT )
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69 #define ETH_DMA_ALL_INTS \
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70 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_ER | \
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71 ETH_DMA_IT_FBE | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
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72 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
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76 #define ipFRAGMENT_OFFSET_BIT_MASK ( ( uint16_t ) 0x0fff ) /* The bits in the two byte IP header field that make up the fragment offset value. */
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79 * Most users will want a PHY that negotiates about
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80 * the connection properties: speed, dmix and duplex.
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81 * On some rare cases, you want to select what is being
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82 * advertised, properties like MDIX and duplex.
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85 #if !defined( ipconfigETHERNET_AN_ENABLE )
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86 /* Enable auto-negotiation */
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87 #define ipconfigETHERNET_AN_ENABLE 1
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90 #if !defined( ipconfigETHERNET_AUTO_CROSS_ENABLE )
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91 #define ipconfigETHERNET_AUTO_CROSS_ENABLE 1
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94 #if( ipconfigETHERNET_AN_ENABLE == 0 )
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96 * The following three defines are only used in case there
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97 * is no auto-negotiation.
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99 #if !defined( ipconfigETHERNET_CROSSED_LINK )
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100 #define ipconfigETHERNET_CROSSED_LINK 1
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103 #if !defined( ipconfigETHERNET_USE_100MB )
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104 #define ipconfigETHERNET_USE_100MB 1
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107 #if !defined( ipconfigETHERNET_USE_FULL_DUPLEX )
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108 #define ipconfigETHERNET_USE_FULL_DUPLEX 1
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110 #endif /* ipconfigETHERNET_AN_ENABLE == 0 */
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112 /* Default the size of the stack used by the EMAC deferred handler task to twice
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113 the size of the stack used by the idle task - but allow this to be overridden in
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114 FreeRTOSConfig.h as configMINIMAL_STACK_SIZE is a user definable constant. */
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115 #ifndef configEMAC_TASK_STACK_SIZE
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116 #define configEMAC_TASK_STACK_SIZE ( 2 * configMINIMAL_STACK_SIZE )
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119 /* Two choices must be made: RMII versus MII,
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120 and the index of the PHY in use ( between 0 and 31 ). */
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121 #ifndef ipconfigUSE_RMII
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123 #define ipconfigUSE_RMII 1
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125 #define ipconfigUSE_RMII 0
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126 #endif /* STM32F7xx */
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127 #endif /* ipconfigUSE_RMII */
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129 #ifndef ipconfigPHY_INDEX
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131 #define ipconfigPHY_INDEX 0
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133 #define ipconfigPHY_INDEX 1
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134 #endif /* STM32F7xx */
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135 #endif /* ipconfigPHY_INDEX */
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138 /*-----------------------------------------------------------*/
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141 * A deferred interrupt handler task that processes
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143 static void prvEMACHandlerTask( void *pvParameters );
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146 * Force a negotiation with the Switch or Router and wait for LS.
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148 static void prvEthernetUpdateConfig( BaseType_t xForce );
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151 * See if there is a new packet and forward it to the IP-task.
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153 static BaseType_t prvNetworkInterfaceInput( void );
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155 #if( ipconfigUSE_LLMNR != 0 )
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157 * For LLMNR, an extra MAC-address must be configured to
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158 * be able to receive the multicast messages.
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160 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr);
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164 * Check if a given packet should be accepted.
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166 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer );
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169 * Initialise the TX descriptors.
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171 static void prvDMATxDescListInit( void );
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174 * Initialise the RX descriptors.
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176 static void prvDMARxDescListInit( void );
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178 /* After packets have been sent, the network
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179 buffers will be released. */
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180 static void vClearTXBuffers( void );
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182 /*-----------------------------------------------------------*/
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184 /* Bit map of outstanding ETH interrupt events for processing. Currently only
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185 the Rx interrupt is handled, although code is included for other events to
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186 enable future expansion. */
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187 static volatile uint32_t ulISREvents;
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189 #if( ipconfigUSE_LLMNR == 1 )
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190 static const uint8_t xLLMNR_MACAddress[] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFC };
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193 static EthernetPhy_t xPhyObject;
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195 /* Ethernet handle. */
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196 static ETH_HandleTypeDef xETH;
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198 /* xTXDescriptorSemaphore is a counting semaphore with
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199 a maximum count of ETH_TXBUFNB, which is the number of
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200 DMA TX descriptors. */
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201 static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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204 * Note: it is adviced to define both
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206 * #define ipconfigZERO_COPY_RX_DRIVER 1
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207 * #define ipconfigZERO_COPY_TX_DRIVER 1
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209 * The method using memcpy is slower and probaly uses more RAM memory.
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210 * The possibility is left in the code just for comparison.
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212 * It is adviced to define ETH_TXBUFNB at least 4. Note that no
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213 * TX buffers are allocated in a zero-copy driver.
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215 /* MAC buffers: ---------------------------------------------------------*/
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217 /* Put the DMA descriptors in '.first_data'.
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218 This is important for STM32F7, which has an L1 data cache.
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219 The first 64KB of the SRAM is not cached. */
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221 /* Ethernet Rx MA Descriptor */
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222 __attribute__ ((aligned (32)))
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223 __attribute__ ((section(".first_data")))
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224 ETH_DMADescTypeDef DMARxDscrTab[ ETH_RXBUFNB ];
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226 #if( ipconfigZERO_COPY_RX_DRIVER == 0 )
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227 /* Ethernet Receive Buffer */
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228 __ALIGN_BEGIN uint8_t Rx_Buff[ ETH_RXBUFNB ][ ETH_RX_BUF_SIZE ] __ALIGN_END;
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231 /* Ethernet Tx DMA Descriptor */
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232 __attribute__ ((aligned (32)))
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233 __attribute__ ((section(".first_data")))
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234 ETH_DMADescTypeDef DMATxDscrTab[ ETH_TXBUFNB ];
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236 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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237 /* Ethernet Transmit Buffer */
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238 __ALIGN_BEGIN uint8_t Tx_Buff[ ETH_TXBUFNB ][ ETH_TX_BUF_SIZE ] __ALIGN_END;
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241 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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242 /* DMATxDescToClear points to the next TX DMA descriptor
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243 that must be cleared by vClearTXBuffers(). */
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244 static __IO ETH_DMADescTypeDef *DMATxDescToClear;
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247 /* ucMACAddress as it appears in main.c */
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248 extern const uint8_t ucMACAddress[ 6 ];
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250 /* Holds the handle of the task used as a deferred interrupt processor. The
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251 handle is used so direct notifications can be sent to the task for all EMAC/DMA
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252 related interrupts. */
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253 static TaskHandle_t xEMACTaskHandle = NULL;
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255 /* For local use only: describe the PHY's properties: */
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256 const PhyProperties_t xPHYProperties =
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258 #if( ipconfigETHERNET_AN_ENABLE != 0 )
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259 .ucSpeed = PHY_SPEED_AUTO,
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260 .ucDuplex = PHY_DUPLEX_AUTO,
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262 #if( ipconfigETHERNET_USE_100MB != 0 )
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263 .ucSpeed = PHY_SPEED_100,
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265 .ucSpeed = PHY_SPEED_10,
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268 #if( ipconfigETHERNET_USE_FULL_DUPLEX != 0 )
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269 .duplex = PHY_DUPLEX_FULL,
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271 .duplex = PHY_DUPLEX_HALF,
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275 #if( ipconfigETHERNET_AN_ENABLE != 0 ) && ( ipconfigETHERNET_AUTO_CROSS_ENABLE != 0 )
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276 .ucMDI_X = PHY_MDIX_AUTO,
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277 #elif( ipconfigETHERNET_CROSSED_LINK != 0 )
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278 .ucMDI_X = PHY_MDIX_CROSSED,
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280 .ucMDI_X = PHY_MDIX_DIRECT,
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284 /*-----------------------------------------------------------*/
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286 void HAL_ETH_RxCpltCallback( ETH_HandleTypeDef *heth )
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288 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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290 /* Ethernet RX-Complete callback function, elsewhere declared as weak. */
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291 ulISREvents |= EMAC_IF_RX_EVENT;
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292 /* Wakeup the prvEMACHandlerTask. */
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293 if( xEMACTaskHandle != NULL )
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295 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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296 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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299 /*-----------------------------------------------------------*/
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301 void HAL_ETH_TxCpltCallback( ETH_HandleTypeDef *heth )
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303 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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305 /* This call-back is only useful in case packets are being sent
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306 zero-copy. Once they're sent, the buffers will be released
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307 by the function vClearTXBuffers(). */
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308 ulISREvents |= EMAC_IF_TX_EVENT;
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309 /* Wakeup the prvEMACHandlerTask. */
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310 if( xEMACTaskHandle != NULL )
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312 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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313 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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317 /*-----------------------------------------------------------*/
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319 static void vClearTXBuffers()
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321 __IO ETH_DMADescTypeDef *txLastDescriptor = xETH.TxDesc;
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322 size_t uxCount = ( ( UBaseType_t ) ETH_TXBUFNB ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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323 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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324 NetworkBufferDescriptor_t *pxNetworkBuffer;
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325 uint8_t *ucPayLoad;
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328 /* This function is called after a TX-completion interrupt.
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329 It will release each Network Buffer used in xNetworkInterfaceOutput().
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330 'uxCount' represents the number of descriptors given to DMA for transmission.
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331 After sending a packet, the DMA will clear the 'ETH_DMATXDESC_OWN' bit. */
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332 while( ( uxCount > 0 ) && ( ( DMATxDescToClear->Status & ETH_DMATXDESC_OWN ) == 0 ) )
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334 if( ( DMATxDescToClear == txLastDescriptor ) && ( uxCount != ETH_TXBUFNB ) )
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338 #if( ipconfigZERO_COPY_TX_DRIVER != 0 )
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340 ucPayLoad = ( uint8_t * )DMATxDescToClear->Buffer1Addr;
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342 if( ucPayLoad != NULL )
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344 pxNetworkBuffer = pxPacketBuffer_to_NetworkBuffer( ucPayLoad );
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345 if( pxNetworkBuffer != NULL )
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347 vReleaseNetworkBufferAndDescriptor( pxNetworkBuffer ) ;
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349 DMATxDescToClear->Buffer1Addr = ( uint32_t )0u;
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352 #endif /* ipconfigZERO_COPY_TX_DRIVER */
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354 DMATxDescToClear = ( ETH_DMADescTypeDef * )( DMATxDescToClear->Buffer2NextDescAddr );
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357 /* Tell the counting semaphore that one more TX descriptor is available. */
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358 xSemaphoreGive( xTXDescriptorSemaphore );
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361 /*-----------------------------------------------------------*/
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363 BaseType_t xNetworkInterfaceInitialise( void )
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365 HAL_StatusTypeDef hal_eth_init_status;
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366 BaseType_t xResult;
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368 if( xEMACTaskHandle == NULL )
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370 if( xTXDescriptorSemaphore == NULL )
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372 xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ETH_TXBUFNB, ( UBaseType_t ) ETH_TXBUFNB );
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373 configASSERT( xTXDescriptorSemaphore );
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376 /* Initialise ETH */
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378 xETH.Instance = ETH;
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379 //#warning Enable auto-nego again
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380 xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
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381 // xETH.Init.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE;
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382 xETH.Init.Speed = ETH_SPEED_100M;
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383 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
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384 xETH.Init.PhyAddress = ipconfigPHY_INDEX;
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386 xETH.Init.MACAddr = ( uint8_t *) ucMACAddress;
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387 xETH.Init.RxMode = ETH_RXINTERRUPT_MODE;
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389 /* using the ETH_CHECKSUM_BY_HARDWARE option:
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390 both the IP and the protocol checksums will be calculated
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391 by the peripheral. */
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392 xETH.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
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394 #if( ipconfigUSE_RMII != 0 )
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396 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
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400 xETH.Init.MediaInterface = ETH_MEDIA_INTERFACE_MII;
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402 #endif /* ipconfigUSE_RMII */
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404 hal_eth_init_status = HAL_ETH_Init( &xETH );
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406 /* Only for inspection by debugger. */
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407 ( void ) hal_eth_init_status;
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409 /* Set the TxDesc and RxDesc pointers. */
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410 xETH.TxDesc = DMATxDscrTab;
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411 xETH.RxDesc = DMARxDscrTab;
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413 /* Make sure that all unused fields are cleared. */
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414 memset( &DMATxDscrTab, '\0', sizeof( DMATxDscrTab ) );
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415 memset( &DMARxDscrTab, '\0', sizeof( DMARxDscrTab ) );
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417 /* Initialize Tx Descriptors list: Chain Mode */
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418 DMATxDescToClear = DMATxDscrTab;
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420 /* Initialise TX-descriptors. */
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421 prvDMATxDescListInit();
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423 /* Initialise RX-descriptors. */
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424 prvDMARxDescListInit();
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426 #if( ipconfigUSE_LLMNR != 0 )
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428 /* Program the LLMNR address at index 1. */
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429 prvMACAddressConfig( &xETH, ETH_MAC_ADDRESS1, ( uint8_t *) xLLMNR_MACAddress );
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433 /* Force a negotiation with the Switch or Router and wait for LS. */
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434 prvEthernetUpdateConfig( pdTRUE );
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436 /* The deferred interrupt handler task is created at the highest
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437 possible priority to ensure the interrupt handler can return directly
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438 to it. The task's handle is stored in xEMACTaskHandle so interrupts can
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439 notify the task when there is something to process. */
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440 xTaskCreate( prvEMACHandlerTask, "EMAC", configEMAC_TASK_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, &xEMACTaskHandle );
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441 } /* if( xEMACTaskHandle == NULL ) */
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443 if( xPhyObject.ulLinkStatusMask != 0 )
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445 xETH.Instance->DMAIER |= ETH_DMA_ALL_INTS;
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447 FreeRTOS_printf( ( "Link Status is high\n" ) ) ;
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451 /* For now pdFAIL will be returned. But prvEMACHandlerTask() is running
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452 and it will keep on checking the PHY and set 'ulLinkStatusMask' when necessary. */
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454 FreeRTOS_printf( ( "Link Status still low\n" ) ) ;
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456 /* When returning non-zero, the stack will become active and
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457 start DHCP (in configured) */
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460 /*-----------------------------------------------------------*/
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462 static void prvDMATxDescListInit()
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464 ETH_DMADescTypeDef *pxDMADescriptor;
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467 /* Get the pointer on the first member of the descriptor list */
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468 pxDMADescriptor = DMATxDscrTab;
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470 /* Fill each DMA descriptor with the right values */
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471 for( xIndex = 0; xIndex < ETH_TXBUFNB; xIndex++, pxDMADescriptor++ )
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473 /* Set Second Address Chained bit */
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474 pxDMADescriptor->Status = ETH_DMATXDESC_TCH;
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476 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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478 /* Set Buffer1 address pointer */
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479 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Tx_Buff[ xIndex ] );
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483 if( xETH.Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE )
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485 /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */
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486 pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
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489 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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490 if( xIndex < ETH_TXBUFNB - 1 )
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492 /* Set next descriptor address register with next descriptor base address */
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493 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMADescriptor + 1 );
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497 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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498 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMATxDscrTab;
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502 /* Set Transmit Descriptor List Address Register */
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503 xETH.Instance->DMATDLAR = ( uint32_t ) DMATxDscrTab;
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505 /*-----------------------------------------------------------*/
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507 static void prvDMARxDescListInit()
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509 ETH_DMADescTypeDef *pxDMADescriptor;
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515 /* Get the pointer on the first member of the descriptor list */
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516 pxDMADescriptor = DMARxDscrTab;
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518 /* Fill each DMA descriptor with the right values */
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519 for( xIndex = 0; xIndex < ETH_RXBUFNB; xIndex++, pxDMADescriptor++ )
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522 /* Set Buffer1 size and Second Address Chained bit */
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523 pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
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525 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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527 /* Set Buffer1 address pointer */
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528 NetworkBufferDescriptor_t *pxBuffer;
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530 pxBuffer = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, 100ul );
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531 /* If the assert below fails, make sure that there are at least 'ETH_RXBUFNB'
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532 Network Buffers available during start-up ( ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ) */
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533 configASSERT( pxBuffer != NULL );
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534 if( pxBuffer != NULL )
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536 pxDMADescriptor->Buffer1Addr = (uint32_t)pxBuffer->pucEthernetBuffer;
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537 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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542 /* Set Buffer1 address pointer */
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543 pxDMADescriptor->Buffer1Addr = ( uint32_t )( Rx_Buff[ xIndex ] );
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544 /* Set Own bit of the Rx descriptor Status */
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545 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
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549 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
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550 if( xIndex < ETH_RXBUFNB - 1 )
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552 /* Set next descriptor address register with next descriptor base address */
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553 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t )( pxDMADescriptor + 1 );
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557 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
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558 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) DMARxDscrTab;
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562 /* Set Receive Descriptor List Address Register */
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563 xETH.Instance->DMARDLAR = ( uint32_t ) DMARxDscrTab;
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565 /*-----------------------------------------------------------*/
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567 static void prvMACAddressConfig(ETH_HandleTypeDef *heth, uint32_t ulIndex, uint8_t *Addr)
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569 uint32_t ulTempReg;
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571 /* Calculate the selected MAC address high register. */
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572 ulTempReg = 0x80000000ul | ( ( uint32_t ) Addr[ 5 ] << 8 ) | ( uint32_t ) Addr[ 4 ];
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574 /* Load the selected MAC address high register. */
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575 ( *(__IO uint32_t *)( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + ulIndex ) ) ) = ulTempReg;
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577 /* Calculate the selected MAC address low register. */
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578 ulTempReg = ( ( uint32_t ) Addr[ 3 ] << 24 ) | ( ( uint32_t ) Addr[ 2 ] << 16 ) | ( ( uint32_t ) Addr[ 1 ] << 8 ) | Addr[ 0 ];
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580 /* Load the selected MAC address low register */
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581 ( *(__IO uint32_t *) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + ulIndex ) ) ) = ulTempReg;
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583 /*-----------------------------------------------------------*/
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585 BaseType_t xNetworkInterfaceOutput( NetworkBufferDescriptor_t * const pxDescriptor, BaseType_t bReleaseAfterSend )
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587 BaseType_t xReturn = pdFAIL;
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588 uint32_t ulTransmitSize = 0;
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589 __IO ETH_DMADescTypeDef *pxDmaTxDesc;
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590 /* Do not wait too long for a free TX DMA buffer. */
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591 const TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 50u );
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593 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
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595 ProtocolPacket_t *pxPacket;
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597 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
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599 configASSERT( bReleaseAfterSend != 0 );
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601 #endif /* ipconfigZERO_COPY_RX_DRIVER */
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603 /* If the peripheral must calculate the checksum, it wants
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604 the protocol checksum to have a value of zero. */
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605 pxPacket = ( ProtocolPacket_t * ) ( pxDescriptor->pucEthernetBuffer );
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607 if( pxPacket->xICMPPacket.xIPHeader.ucProtocol == ipPROTOCOL_ICMP )
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609 pxPacket->xICMPPacket.xICMPHeader.usChecksum = ( uint16_t )0u;
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614 /* Open a do {} while ( 0 ) loop to be able to call break. */
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617 if( xPhyObject.ulLinkStatusMask != 0 )
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619 if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
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621 /* Time-out waiting for a free TX descriptor. */
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625 /* This function does the actual transmission of the packet. The packet is
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626 contained in 'pxDescriptor' that is passed to the function. */
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627 pxDmaTxDesc = xETH.TxDesc;
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629 /* Is this buffer available? */
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630 configASSERT ( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) == 0 );
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633 /* Is this buffer available? */
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634 /* Get bytes in current buffer. */
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635 ulTransmitSize = pxDescriptor->xDataLength;
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637 if( ulTransmitSize > ETH_TX_BUF_SIZE )
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639 ulTransmitSize = ETH_TX_BUF_SIZE;
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642 #if( ipconfigZERO_COPY_TX_DRIVER == 0 )
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644 /* Copy the bytes. */
\r
645 memcpy( ( void * ) pxDmaTxDesc->Buffer1Addr, pxDescriptor->pucEthernetBuffer, ulTransmitSize );
\r
649 /* Move the buffer. */
\r
650 pxDmaTxDesc->Buffer1Addr = ( uint32_t )pxDescriptor->pucEthernetBuffer;
\r
651 /* The Network Buffer has been passed to DMA, no need to release it. */
\r
652 bReleaseAfterSend = pdFALSE_UNSIGNED;
\r
654 #endif /* ipconfigZERO_COPY_TX_DRIVER */
\r
656 /* Ask to set the IPv4 checksum.
\r
657 Also need an Interrupt on Completion so that 'vClearTXBuffers()' will be called.. */
\r
658 pxDmaTxDesc->Status |= ETH_DMATXDESC_CIC_TCPUDPICMP_FULL | ETH_DMATXDESC_IC;
\r
660 /* Prepare transmit descriptors to give to DMA. */
\r
662 /* Set LAST and FIRST segment */
\r
663 pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
\r
664 /* Set frame size */
\r
665 pxDmaTxDesc->ControlBufferSize = ( ulTransmitSize & ETH_DMATXDESC_TBS1 );
\r
666 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
667 pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;
\r
669 /* Point to next descriptor */
\r
670 xETH.TxDesc = ( ETH_DMADescTypeDef * ) ( xETH.TxDesc->Buffer2NextDescAddr );
\r
671 /* Ensure completion of memory access */
\r
673 /* Resume DMA transmission*/
\r
674 xETH.Instance->DMATPDR = 0;
\r
675 iptraceNETWORK_INTERFACE_TRANSMIT();
\r
681 /* The PHY has no Link Status, packet shall be dropped. */
\r
684 /* The buffer has been sent so can be released. */
\r
685 if( bReleaseAfterSend != pdFALSE )
\r
687 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
\r
692 /*-----------------------------------------------------------*/
\r
694 static BaseType_t xMayAcceptPacket( uint8_t *pcBuffer )
\r
696 const ProtocolPacket_t *pxProtPacket = ( const ProtocolPacket_t * )pcBuffer;
\r
698 switch( pxProtPacket->xTCPPacket.xEthernetHeader.usFrameType )
\r
700 case ipARP_FRAME_TYPE:
\r
701 /* Check it later. */
\r
703 case ipIPv4_FRAME_TYPE:
\r
704 /* Check it here. */
\r
707 /* Refuse the packet. */
\r
711 #if( ipconfigETHERNET_DRIVER_FILTERS_PACKETS == 1 )
\r
713 const IPHeader_t *pxIPHeader = &(pxProtPacket->xTCPPacket.xIPHeader);
\r
714 uint32_t ulDestinationIPAddress;
\r
716 /* Ensure that the incoming packet is not fragmented (only outgoing packets
\r
717 * can be fragmented) as these are the only handled IP frames currently. */
\r
718 if( ( pxIPHeader->usFragmentOffset & FreeRTOS_ntohs( ipFRAGMENT_OFFSET_BIT_MASK ) ) != 0U )
\r
722 /* HT: Might want to make the following configurable because
\r
723 * most IP messages have a standard length of 20 bytes */
\r
725 /* 0x45 means: IPv4 with an IP header of 5 x 4 = 20 bytes
\r
726 * 0x47 means: IPv4 with an IP header of 7 x 4 = 28 bytes */
\r
727 if( pxIPHeader->ucVersionHeaderLength < 0x45 || pxIPHeader->ucVersionHeaderLength > 0x4F )
\r
732 ulDestinationIPAddress = pxIPHeader->ulDestinationIPAddress;
\r
733 /* Is the packet for this node? */
\r
734 if( ( ulDestinationIPAddress != *ipLOCAL_IP_ADDRESS_POINTER ) &&
\r
735 /* Is it a broadcast address x.x.x.255 ? */
\r
736 ( ( FreeRTOS_ntohl( ulDestinationIPAddress ) & 0xff ) != 0xff ) &&
\r
737 #if( ipconfigUSE_LLMNR == 1 )
\r
738 ( ulDestinationIPAddress != ipLLMNR_IP_ADDR ) &&
\r
740 ( *ipLOCAL_IP_ADDRESS_POINTER != 0 ) ) {
\r
741 FreeRTOS_printf( ( "Drop IP %lxip\n", FreeRTOS_ntohl( ulDestinationIPAddress ) ) );
\r
745 if( pxIPHeader->ucProtocol == ipPROTOCOL_UDP )
\r
747 uint16_t port = pxProtPacket->xUDPPacket.xUDPHeader.usDestinationPort;
\r
749 if( ( xPortHasUDPSocket( port ) == pdFALSE )
\r
750 #if ipconfigUSE_LLMNR == 1
\r
751 && ( port != FreeRTOS_ntohs( ipLLMNR_PORT ) )
\r
753 #if ipconfigUSE_NBNS == 1
\r
754 && ( port != FreeRTOS_ntohs( ipNBNS_PORT ) )
\r
756 #if ipconfigUSE_DNS == 1
\r
757 && ( pxProtPacket->xUDPPacket.xUDPHeader.usSourcePort != FreeRTOS_ntohs( ipDNS_PORT ) )
\r
760 /* Drop this packet, not for this device. */
\r
765 #endif /* ipconfigETHERNET_DRIVER_FILTERS_PACKETS */
\r
768 /*-----------------------------------------------------------*/
\r
770 static BaseType_t prvNetworkInterfaceInput( void )
\r
772 NetworkBufferDescriptor_t *pxCurDescriptor;
\r
773 NetworkBufferDescriptor_t *pxNewDescriptor = NULL;
\r
774 BaseType_t xReceivedLength, xAccepted;
\r
775 __IO ETH_DMADescTypeDef *pxDMARxDescriptor;
\r
776 xIPStackEvent_t xRxEvent = { eNetworkRxEvent, NULL };
\r
777 const TickType_t xDescriptorWaitTime = pdMS_TO_TICKS( 250 );
\r
778 uint8_t *pucBuffer;
\r
780 pxDMARxDescriptor = xETH.RxDesc;
\r
782 if( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_OWN) == 0 )
\r
784 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
785 xReceivedLength = ( ( pxDMARxDescriptor->Status & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
\r
787 pucBuffer = (uint8_t *) pxDMARxDescriptor->Buffer1Addr;
\r
789 /* Update the ETHERNET DMA global Rx descriptor with next Rx descriptor */
\r
790 /* Chained Mode */
\r
791 /* Selects the next DMA Rx descriptor list for next buffer to read */
\r
792 xETH.RxDesc = ( ETH_DMADescTypeDef* )pxDMARxDescriptor->Buffer2NextDescAddr;
\r
796 xReceivedLength = 0;
\r
799 /* Obtain the size of the packet and put it into the "usReceivedLength" variable. */
\r
801 /* get received frame */
\r
802 if( xReceivedLength > 0ul )
\r
804 /* In order to make the code easier and faster, only packets in a single buffer
\r
805 will be accepted. This can be done by making the buffers large enough to
\r
806 hold a complete Ethernet packet (1536 bytes).
\r
807 Therefore, two sanity checks: */
\r
808 configASSERT( xReceivedLength <= ETH_RX_BUF_SIZE );
\r
810 if( ( pxDMARxDescriptor->Status & ( ETH_DMARXDESC_CE | ETH_DMARXDESC_IPV4HCE | ETH_DMARXDESC_FT ) ) != ETH_DMARXDESC_FT )
\r
812 /* Not an Ethernet frame-type or a checmsum error. */
\r
813 xAccepted = pdFALSE;
\r
817 /* See if this packet must be handled. */
\r
818 xAccepted = xMayAcceptPacket( pucBuffer );
\r
821 if( xAccepted != pdFALSE )
\r
823 /* The packet wil be accepted, but check first if a new Network Buffer can
\r
824 be obtained. If not, the packet will still be dropped. */
\r
825 pxNewDescriptor = pxGetNetworkBufferWithDescriptor( ETH_RX_BUF_SIZE, xDescriptorWaitTime );
\r
827 if( pxNewDescriptor == NULL )
\r
829 /* A new descriptor can not be allocated now. This packet will be dropped. */
\r
830 xAccepted = pdFALSE;
\r
833 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
835 /* Find out which Network Buffer was originally passed to the descriptor. */
\r
836 pxCurDescriptor = pxPacketBuffer_to_NetworkBuffer( pucBuffer );
\r
837 configASSERT( pxCurDescriptor != NULL );
\r
841 /* In this mode, the two descriptors are the same. */
\r
842 pxCurDescriptor = pxNewDescriptor;
\r
843 if( pxNewDescriptor != NULL )
\r
845 /* The packet is acepted and a new Network Buffer was created,
\r
846 copy data to the Network Bufffer. */
\r
847 memcpy( pxNewDescriptor->pucEthernetBuffer, pucBuffer, xReceivedLength );
\r
852 if( xAccepted != pdFALSE )
\r
854 pxCurDescriptor->xDataLength = xReceivedLength;
\r
855 xRxEvent.pvData = ( void * ) pxCurDescriptor;
\r
857 /* Pass the data to the TCP/IP task for processing. */
\r
858 if( xSendEventStructToIPTask( &xRxEvent, xDescriptorWaitTime ) == pdFALSE )
\r
860 /* Could not send the descriptor into the TCP/IP stack, it
\r
861 must be released. */
\r
862 vReleaseNetworkBufferAndDescriptor( pxCurDescriptor );
\r
863 iptraceETHERNET_RX_EVENT_LOST();
\r
867 iptraceNETWORK_INTERFACE_RECEIVE();
\r
871 /* Release descriptors to DMA */
\r
872 #if( ipconfigZERO_COPY_RX_DRIVER != 0 )
\r
874 /* Set Buffer1 address pointer */
\r
875 if( pxNewDescriptor != NULL )
\r
877 pxDMARxDescriptor->Buffer1Addr = (uint32_t)pxNewDescriptor->pucEthernetBuffer;
\r
881 /* The packet was dropped and the same Network
\r
882 Buffer will be used to receive a new packet. */
\r
885 #endif /* ipconfigZERO_COPY_RX_DRIVER */
\r
887 /* Set Buffer1 size and Second Address Chained bit */
\r
888 pxDMARxDescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | (uint32_t)ETH_RX_BUF_SIZE;
\r
889 pxDMARxDescriptor->Status = ETH_DMARXDESC_OWN;
\r
891 /* Ensure completion of memory access */
\r
893 /* When Rx Buffer unavailable flag is set clear it and resume
\r
895 if( ( xETH.Instance->DMASR & ETH_DMASR_RBUS ) != 0 )
\r
897 /* Clear RBUS ETHERNET DMA flag. */
\r
898 xETH.Instance->DMASR = ETH_DMASR_RBUS;
\r
900 /* Resume DMA reception. */
\r
901 xETH.Instance->DMARPDR = 0;
\r
905 return ( xReceivedLength > 0 );
\r
907 /*-----------------------------------------------------------*/
\r
910 BaseType_t xSTM32_PhyRead( BaseType_t xAddress, BaseType_t xRegister, uint32_t *pulValue )
\r
912 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
913 BaseType_t xResult;
\r
914 HAL_StatusTypeDef xHALResult;
\r
916 xETH.Init.PhyAddress = xAddress;
\r
917 xHALResult = HAL_ETH_ReadPHYRegister( &xETH, ( uint16_t )xRegister, pulValue );
\r
918 xETH.Init.PhyAddress = usPrevAddress;
\r
920 if( xHALResult == HAL_OK )
\r
930 /*-----------------------------------------------------------*/
\r
932 BaseType_t xSTM32_PhyWrite( BaseType_t xAddress, BaseType_t xRegister, uint32_t ulValue )
\r
934 uint16_t usPrevAddress = xETH.Init.PhyAddress;
\r
935 BaseType_t xResult;
\r
936 HAL_StatusTypeDef xHALResult;
\r
938 xETH.Init.PhyAddress = xAddress;
\r
939 xHALResult = HAL_ETH_WritePHYRegister( &xETH, ( uint16_t )xRegister, ulValue );
\r
940 xETH.Init.PhyAddress = usPrevAddress;
\r
942 if( xHALResult == HAL_OK )
\r
952 /*-----------------------------------------------------------*/
\r
956 BaseType_t xPhyCount;
\r
957 BaseType_t xPhyIndex;
\r
959 vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );
\r
960 xPhyCount = xPhyDiscover( &xPhyObject );
\r
961 FreeRTOS_printf( ( "PHY count %ld\n", xPhyCount ) );
\r
962 for( xPhyIndex = 0; xPhyIndex < xPhyCount; xPhyIndex++ )
\r
964 FreeRTOS_printf( ( "PHY[%d] at address %d ( 0x%08X )\n",
\r
966 xPhyObject.ucPhyIndexes[ xPhyIndex ],
\r
967 xPhyObject.ulPhyIDs[ xPhyIndex ] ) );
\r
973 void vMACBProbePhy( void )
\r
975 vPhyInitialise( &xPhyObject, xSTM32_PhyRead, xSTM32_PhyWrite );
\r
976 xPhyDiscover( &xPhyObject );
\r
977 xPhyConfigure( &xPhyObject, &xPHYProperties );
\r
979 /*-----------------------------------------------------------*/
\r
981 static void prvEthernetUpdateConfig( BaseType_t xForce )
\r
983 FreeRTOS_printf( ( "prvEthernetUpdateConfig: LS mask %02X Force %d\n",
\r
984 xPhyObject.ulLinkStatusMask,
\r
987 if( ( xForce != pdFALSE ) || ( xPhyObject.ulLinkStatusMask != 0 ) )
\r
989 /* Restart the auto-negotiation. */
\r
990 if( xETH.Init.AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE )
\r
992 xPhyStartAutoNegotiation( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
994 /* Configure the MAC with the Duplex Mode fixed by the
\r
995 auto-negotiation process. */
\r
996 if( xPhyObject.xPhyProperties.ucDuplex == PHY_DUPLEX_FULL )
\r
998 xETH.Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1002 xETH.Init.DuplexMode = ETH_MODE_HALFDUPLEX;
\r
1005 /* Configure the MAC with the speed fixed by the
\r
1006 auto-negotiation process. */
\r
1007 if( xPhyObject.xPhyProperties.ucSpeed == PHY_SPEED_10 )
\r
1009 xETH.Init.Speed = ETH_SPEED_10M;
\r
1013 xETH.Init.Speed = ETH_SPEED_100M;
\r
1016 else /* AutoNegotiation Disable */
\r
1018 /* Check parameters */
\r
1019 assert_param( IS_ETH_SPEED( xETH.Init.Speed ) );
\r
1020 assert_param( IS_ETH_DUPLEX_MODE( xETH.Init.DuplexMode ) );
\r
1022 if( xETH.Init.DuplexMode == ETH_MODE_FULLDUPLEX )
\r
1024 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_HALF;
\r
1028 xPhyObject.xPhyPreferences.ucDuplex = PHY_DUPLEX_FULL;
\r
1031 if( xETH.Init.Speed == ETH_SPEED_10M )
\r
1033 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_10;
\r
1037 xPhyObject.xPhyPreferences.ucSpeed = PHY_SPEED_100;
\r
1040 xPhyObject.xPhyPreferences.ucMDI_X = PHY_MDIX_AUTO;
\r
1042 /* Use predefined (fixed) configuration. */
\r
1043 xPhyFixedValue( &xPhyObject, xPhyGetMask( &xPhyObject ) );
\r
1046 /* ETHERNET MAC Re-Configuration */
\r
1047 HAL_ETH_ConfigMAC( &xETH, (ETH_MACInitTypeDef *) NULL);
\r
1049 /* Restart MAC interface */
\r
1050 HAL_ETH_Start( &xETH);
\r
1054 /* Stop MAC interface */
\r
1055 HAL_ETH_Stop( &xETH );
\r
1058 /*-----------------------------------------------------------*/
\r
1060 BaseType_t xGetPhyLinkStatus( void )
\r
1062 BaseType_t xReturn;
\r
1064 if( xPhyObject.ulLinkStatusMask != 0 )
\r
1075 /*-----------------------------------------------------------*/
\r
1077 #define niBUFFER_1_PACKET_SIZE 1536
\r
1079 static __attribute__ ((section(".first_data"))) uint8_t ucNetworkPackets[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS * niBUFFER_1_PACKET_SIZE ] __attribute__ ( ( aligned( 32 ) ) );
\r
1081 void vNetworkInterfaceAllocateRAMToBuffers( NetworkBufferDescriptor_t pxNetworkBuffers[ ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS ] )
\r
1084 uint8_t *ucRAMBuffer = ucNetworkPackets;
\r
1087 for( ul = 0; ul < ipconfigNUM_NETWORK_BUFFER_DESCRIPTORS; ul++ )
\r
1089 pxNetworkBuffers[ ul ].pucEthernetBuffer = ucRAMBuffer + ipBUFFER_PADDING;
\r
1090 *( ( unsigned * ) ucRAMBuffer ) = ( unsigned ) ( &( pxNetworkBuffers[ ul ] ) );
\r
1091 ucRAMBuffer += niBUFFER_1_PACKET_SIZE;
\r
1094 /*-----------------------------------------------------------*/
\r
1096 static void prvEMACHandlerTask( void *pvParameters )
\r
1098 UBaseType_t uxLastMinBufferCount = 0;
\r
1099 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1100 UBaseType_t uxLastMinQueueSpace = 0;
\r
1102 UBaseType_t uxCurrentCount;
\r
1103 BaseType_t xResult;
\r
1104 const TickType_t ulMaxBlockTime = pdMS_TO_TICKS( 100UL );
\r
1106 /* Remove compiler warnings about unused parameters. */
\r
1107 ( void ) pvParameters;
\r
1112 uxCurrentCount = uxGetMinimumFreeNetworkBuffers();
\r
1113 if( uxLastMinBufferCount != uxCurrentCount )
\r
1115 /* The logging produced below may be helpful
\r
1116 while tuning +TCP: see how many buffers are in use. */
\r
1117 uxLastMinBufferCount = uxCurrentCount;
\r
1118 FreeRTOS_printf( ( "Network buffers: %lu lowest %lu\n",
\r
1119 uxGetNumberOfFreeNetworkBuffers(), uxCurrentCount ) );
\r
1122 if( xTXDescriptorSemaphore != NULL )
\r
1124 static UBaseType_t uxLowestSemCount = ( UBaseType_t ) ETH_TXBUFNB - 1;
\r
1126 uxCurrentCount = uxSemaphoreGetCount( xTXDescriptorSemaphore );
\r
1127 if( uxLowestSemCount > uxCurrentCount )
\r
1129 uxLowestSemCount = uxCurrentCount;
\r
1130 FreeRTOS_printf( ( "TX DMA buffers: lowest %lu\n", uxLowestSemCount ) );
\r
1135 #if( ipconfigCHECK_IP_QUEUE_SPACE != 0 )
\r
1137 uxCurrentCount = uxGetMinimumIPQueueSpace();
\r
1138 if( uxLastMinQueueSpace != uxCurrentCount )
\r
1140 /* The logging produced below may be helpful
\r
1141 while tuning +TCP: see how many buffers are in use. */
\r
1142 uxLastMinQueueSpace = uxCurrentCount;
\r
1143 FreeRTOS_printf( ( "Queue space: lowest %lu\n", uxCurrentCount ) );
\r
1146 #endif /* ipconfigCHECK_IP_QUEUE_SPACE */
\r
1148 if( ( ulISREvents & EMAC_IF_ALL_EVENT ) == 0 )
\r
1150 /* No events to process now, wait for the next. */
\r
1151 ulTaskNotifyTake( pdFALSE, ulMaxBlockTime );
\r
1154 if( ( ulISREvents & EMAC_IF_RX_EVENT ) != 0 )
\r
1156 ulISREvents &= ~EMAC_IF_RX_EVENT;
\r
1158 xResult = prvNetworkInterfaceInput();
\r
1161 while( prvNetworkInterfaceInput() > 0 )
\r
1167 if( ( ulISREvents & EMAC_IF_TX_EVENT ) != 0 )
\r
1169 /* Code to release TX buffers if zero-copy is used. */
\r
1170 ulISREvents &= ~EMAC_IF_TX_EVENT;
\r
1171 /* Check if DMA packets have been delivered. */
\r
1172 vClearTXBuffers();
\r
1175 if( ( ulISREvents & EMAC_IF_ERR_EVENT ) != 0 )
\r
1177 /* Future extension: logging about errors that occurred. */
\r
1178 ulISREvents &= ~EMAC_IF_ERR_EVENT;
\r
1180 if( xPhyCheckLinkStatus( &xPhyObject, xResult ) != 0 )
\r
1182 /* Something has changed to a Link Status, need re-check. */
\r
1183 prvEthernetUpdateConfig( pdFALSE );
\r
1187 /*-----------------------------------------------------------*/
\r
1189 void ETH_IRQHandler( void )
\r
1191 HAL_ETH_IRQHandler( &xETH );
\r