2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* FreeRTOS includes. */
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30 #include "FreeRTOS.h"
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32 /* Utility functions to implement run time stats on Cortex-M CPUs. The collected
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33 run time data can be viewed through the CLI interface. See the following URL for
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34 more information on run time stats:
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35 http://www.freertos.org/rtos-run-time-stats.html */
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37 /* Addresses of registers in the Cortex-M debug hardware. */
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38 #define rtsDWT_CYCCNT ( *( ( unsigned long * ) 0xE0001004 ) )
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39 #define rtsDWT_CONTROL ( *( ( unsigned long * ) 0xE0001000 ) )
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40 #define rtsSCB_DEMCR ( *( ( unsigned long * ) 0xE000EDFC ) )
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41 #define rtsTRCENA_BIT ( 0x01000000UL )
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42 #define rtsCOUNTER_ENABLE_BIT ( 0x01UL )
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44 /* Simple shift divide for scaling to avoid an overflow occurring too soon. The
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45 number of bits to shift depends on the clock speed. */
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46 #define runtimeSLOWER_CLOCK_SPEEDS ( 70000000UL )
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47 #define runtimeSHIFT_13 13
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48 #define runtimeOVERFLOW_BIT_13 ( 1UL << ( 32UL - runtimeSHIFT_13 ) )
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49 #define runtimeSHIFT_14 14
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50 #define runtimeOVERFLOW_BIT_14 ( 1UL << ( 32UL - runtimeSHIFT_14 ) )
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52 /*-----------------------------------------------------------*/
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54 void vMainConfigureTimerForRunTimeStats( void )
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56 /* Enable TRCENA. */
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57 rtsSCB_DEMCR = rtsSCB_DEMCR | rtsTRCENA_BIT;
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59 /* Reset counter. */
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62 /* Enable counter. */
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63 rtsDWT_CONTROL = rtsDWT_CONTROL | rtsCOUNTER_ENABLE_BIT;
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65 /*-----------------------------------------------------------*/
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67 uint32_t ulMainGetRunTimeCounterValue( void )
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69 static unsigned long ulLastCounterValue = 0UL, ulOverflows = 0;
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70 unsigned long ulValueNow;
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72 ulValueNow = rtsDWT_CYCCNT;
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74 /* Has the value overflowed since it was last read. */
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75 if( ulValueNow < ulLastCounterValue )
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79 ulLastCounterValue = ulValueNow;
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81 /* Cannot use configCPU_CLOCK_HZ directly as it may itself not be a constant
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82 but instead map to a variable that holds the clock speed. */
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84 /* There is no prescale on the counter, so simulate in software. */
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85 if( configCPU_CLOCK_HZ < runtimeSLOWER_CLOCK_SPEEDS )
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87 ulValueNow >>= runtimeSHIFT_13;
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88 ulValueNow += ( runtimeOVERFLOW_BIT_13 * ulOverflows );
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92 ulValueNow >>= runtimeSHIFT_14;
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93 ulValueNow += ( runtimeOVERFLOW_BIT_14 * ulOverflows );
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98 /*-----------------------------------------------------------*/
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