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   1 /***********************************************************************//**\r
   2  * @file                lpc18xx_clkpwr.h\r
   3  * @brief               Contains all macro definitions and function prototypes\r
   4  *                              support for Clock and Power Control firmware library on LPC18xx\r
   5  * @version             1.0\r
   6  * @date                14. Dec. 2010\r
   7  * @author              NXP MCU SW Application Team\r
   8  **************************************************************************\r
   9  * Software that is described herein is for illustrative purposes only\r
  10  * which provides customers with programming information regarding the\r
  11  * products. This software is supplied "AS IS" without any warranties.\r
  12  * NXP Semiconductors assumes no responsibility or liability for the\r
  13  * use of the software, conveys no license or title under any patent,\r
  14  * copyright, or mask work right to the product. NXP Semiconductors\r
  15  * reserves the right to make changes in the software without\r
  16  * notification. NXP Semiconductors also make no representation or\r
  17  * warranty that such application will be suitable for the specified\r
  18  * use without further testing or modification.\r
  19  **************************************************************************/\r
  20 \r
  21 /* Peripheral group ----------------------------------------------------------- */\r
  22 /** @defgroup CLKPWR CLKPWR\r
  23  * @ingroup LPC1800CMSIS_FwLib_Drivers\r
  24  * @{\r
  25  */\r
  26 \r
  27 #ifndef LPC18XX_CLKPWR_H_\r
  28 #define LPC18XX_CLKPWR_H_\r
  29 \r
  30 /* Includes ------------------------------------------------------------------- */\r
  31 #include "LPC18xx.h"\r
  32 #include "lpc_types.h"\r
  33 \r
  34 #ifdef __cplusplus\r
  35 extern "C"\r
  36 {\r
  37 #endif\r
  38 \r
  39 /* Public Macros -------------------------------------------------------------- */\r
  40 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros\r
  41  * @{\r
  42  */\r
  43 \r
  44 typedef enum {\r
  45         /* Clock Source */\r
  46         CLKPWR_CLKSRC_32KHZ_OSC = 0,\r
  47         CLKPWR_CLKSRC_IRC,\r
  48         CLKPWR_CLKSRC_ENET_RX_CLK,\r
  49         CLKPWR_CLKSRC_ENET_TX_CLK,\r
  50         CLKPWR_CLKSRC_GP_CLKIN,\r
  51         CLKPWR_CLKSRC_TCK,\r
  52         CLKPWR_CLKSRC_XTAL_OSC,\r
  53         CLKPWR_CLKSRC_PLL0,\r
  54         CLKPWR_CLKSRC_PLL1,\r
  55         CLKPWR_CLKSRC_IDIVA = CLKPWR_CLKSRC_PLL1 + 3,\r
  56         CLKPWR_CLKSRC_IDIVB,\r
  57         CLKPWR_CLKSRC_IDIVC,\r
  58         CLKPWR_CLKSRC_IDIVD,\r
  59         CLKPWR_CLKSRC_IDIVE,\r
  60 \r
  61         /* Base */\r
  62         CLKPWR_BASE_SAFE,\r
  63         CLKPWR_BASE_USB0,\r
  64         CLKPWR_BASE_USB1 = CLKPWR_BASE_USB0 + 2,\r
  65         CLKPWR_BASE_M3,\r
  66         CLKPWR_BASE_SPIFI,\r
  67         //CLKPWR_BASE_SPI,\r
  68         CLKPWR_BASE_PHY_RX = CLKPWR_BASE_SPIFI + 2,\r
  69         CLKPWR_BASE_PHY_TX,\r
  70         CLKPWR_BASE_APB1,\r
  71         CLKPWR_BASE_APB3,\r
  72         CLKPWR_BASE_LCD,\r
  73         CLKPWR_BASE_SDIO = CLKPWR_BASE_LCD + 2,\r
  74         CLKPWR_BASE_SSP0,\r
  75         CLKPWR_BASE_SSP1,\r
  76         CLKPWR_BASE_UART0,\r
  77         CLKPWR_BASE_UART1,\r
  78         CLKPWR_BASE_UART2,\r
  79         CLKPWR_BASE_UART3,\r
  80         CLKPWR_BASE_CLKOUT,\r
  81         CLKPWR_ENTITY_NUM\r
  82 } CLKPWR_ENTITY_T;\r
  83 \r
  84 #define CLKPWR_CLKSRC_NUM (CLKPWR_CLKSRC_IDIVE+1)\r
  85 \r
  86 typedef enum {\r
  87         CLKPWR_PLL0_MODE_1d = 0,\r
  88         CLKPWR_PLL0_MODE_1c,\r
  89         CLKPWR_PLL0_MODE_1b,\r
  90         CLKPWR_PLL0_MODE_1a,\r
  91 }CLKPWR_PLL0_MODE;\r
  92 \r
  93 typedef enum {\r
  94         CLKPWR_PERIPHERAL_ADC0 = 0,\r
  95         CLKPWR_PERIPHERAL_ADC1,\r
  96         CLKPWR_PERIPHERAL_AES,\r
  97 //      CLKPWR_PERIPHERAL_ALARMTIMER_CGU_RGU_RTC_WIC,\r
  98         CLKPWR_PERIPHERAL_APB1_BUS,\r
  99         CLKPWR_PERIPHERAL_APB3_BUS,\r
 100         CLKPWR_PERIPHERAL_CAN,\r
 101         CLKPWR_PERIPHERAL_CREG,\r
 102         CLKPWR_PERIPHERAL_DAC,\r
 103         CLKPWR_PERIPHERAL_DMA,\r
 104         CLKPWR_PERIPHERAL_EMC,\r
 105         CLKPWR_PERIPHERAL_ETHERNET,\r
 106         CLKPWR_PERIPHERAL_ETHERNET_TX, //HIDE\r
 107         CLKPWR_PERIPHERAL_GPIO,\r
 108         CLKPWR_PERIPHERAL_I2C0,\r
 109         CLKPWR_PERIPHERAL_I2C1,\r
 110         CLKPWR_PERIPHERAL_I2S,\r
 111         CLKPWR_PERIPHERAL_LCD,\r
 112         CLKPWR_PERIPHERAL_M3CORE,\r
 113         CLKPWR_PERIPHERAL_M3_BUS,\r
 114         CLKPWR_PERIPHERAL_MOTOCON,\r
 115         CLKPWR_PERIPHERAL_QEI,\r
 116         CLKPWR_PERIPHERAL_RITIMER,\r
 117         CLKPWR_PERIPHERAL_SCT,\r
 118         CLKPWR_PERIPHERAL_SCU,\r
 119         CLKPWR_PERIPHERAL_SDIO,\r
 120         CLKPWR_PERIPHERAL_SPIFI,\r
 121         CLKPWR_PERIPHERAL_SSP0,\r
 122         CLKPWR_PERIPHERAL_SSP1,\r
 123         CLKPWR_PERIPHERAL_TIMER0,\r
 124         CLKPWR_PERIPHERAL_TIMER1,\r
 125         CLKPWR_PERIPHERAL_TIMER2,\r
 126         CLKPWR_PERIPHERAL_TIMER3,\r
 127         CLKPWR_PERIPHERAL_UART0,\r
 128         CLKPWR_PERIPHERAL_UART1,\r
 129         CLKPWR_PERIPHERAL_UART2,\r
 130         CLKPWR_PERIPHERAL_UART3,\r
 131         CLKPWR_PERIPHERAL_USB0,\r
 132         CLKPWR_PERIPHERAL_USB1,\r
 133         CLKPWR_PERIPHERAL_WWDT,\r
 134         CLKPWR_PERIPHERAL_NUM\r
 135 } CLKPWR_PERIPHERAL_T;\r
 136 //typedef CLKPWR_CLK_T CLKPWR_BASE_T;\r
 137 \r
 138 typedef struct {\r
 139         uint8_t RegBaseEntity;\r
 140         uint16_t RegBranchOffset;\r
 141         uint8_t PerBaseEntity;\r
 142         uint16_t PerBranchOffset;\r
 143         uint8_t next;\r
 144 } CLKPWR_PERIPHERAL_S;\r
 145 \r
 146 typedef enum {\r
 147         CLKPWR_ERROR_SUCCESS = 0,\r
 148         CLKPWR_ERROR_CONNECT_TOGETHER,\r
 149         CLKPWR_ERROR_INVALID_ENTITY,\r
 150         CLKPWR_ERROR_INVALID_CLOCK_SOURCE,\r
 151         CLKPWR_ERROR_INVALID_PARAM,\r
 152         CLKPWR_ERROR_FREQ_OUTOF_RANGE\r
 153 } CLKPWR_ERROR;\r
 154 \r
 155 /* Branch clocks from CLKPWR_BASE_SAFE */\r
 156 \r
 157 #define CLKPWR_ENTITY_NONE      CLKPWR_ENTITY_NUM\r
 158 \r
 159 #define ISBITCLR(x,bit) ((x&(1<<bit))^(1<<bit))\r
 160 #define ISBITSET(x,bit) (x&(1<<bit))\r
 161 #define ISMASKSET(x,mask) (x&mask)\r
 162 \r
 163 #define CLKPWR_CTRL_EN_MASK             1\r
 164 #define CLKPWR_CTRL_SRC_MASK    (0xF<<24)\r
 165 #define CLKPWR_CTRL_AUTOBLOCK_MASK      (1<<11)\r
 166 #define CLKPWR_PLL1_FBSEL_MASK  (1<<6)\r
 167 #define CLKPWR_PLL1_BYPASS_MASK (1<<1)\r
 168 #define CLKPWR_PLL1_DIRECT_MASK (1<<7)\r
 169 \r
 170 #define CLKPWR_SLEEP_MODE_DEEP_SLEEP    0x3F00AA\r
 171 #define CLKPWR_SLEEP_MODE_POWER_DOWN    0x3FFCBA\r
 172 #define CLKPWR_SLEEP_MODE_DEEP_POWER_DOWN       0x3FFF7F\r
 173 \r
 174 /* Public Functions ----------------------------------------------------------- */\r
 175 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions\r
 176  * @{\r
 177  */\r
 178 /* Clock Generator */\r
 179 \r
 180 uint32_t        CLKPWR_ConfigPWR (CLKPWR_PERIPHERAL_T PPType, FunctionalState en);\r
 181 \r
 182 uint32_t        CLKPWR_GetPCLKFrequency (CLKPWR_PERIPHERAL_T Clock);\r
 183 \r
 184 /* Clock Source and Base Clock operation */\r
 185 uint32_t        CLKPWR_SetXTALOSC(uint32_t ClockFrequency);\r
 186 uint32_t        CLKPWR_SetDIV(CLKPWR_ENTITY_T SelectDivider, uint32_t divisor);\r
 187 uint32_t        CLKPWR_SetPLL0(void);\r
 188 uint32_t        CLKPWR_SetPLL1(uint32_t mult);\r
 189 uint32_t        CLKPWR_EnableEntity(CLKPWR_ENTITY_T ClockEntity, uint32_t en);\r
 190 uint32_t        CLKPWR_EntityConnect(CLKPWR_ENTITY_T ClockSource, CLKPWR_ENTITY_T ClockEntity);\r
 191 uint32_t        CLKPWR_GetBaseStatus(CLKPWR_ENTITY_T Base);\r
 192 \r
 193 void            CLKPWR_UpdateClock(void);\r
 194 uint32_t        CLKPWR_RealFrequencyCompare(CLKPWR_ENTITY_T Clock, CLKPWR_ENTITY_T CompareToClock, uint32_t *m, uint32_t *d);\r
 195 \r
 196 uint32_t        CLKPWR_Init(void);\r
 197 uint32_t        CLKPWR_DeInit(void);\r
 198 \r
 199 void CLKPWR_Sleep(void);\r
 200 void CLKPWR_DeepSleep(void);\r
 201 void CLKPWR_PowerDown(void);\r
 202 void CLKPWR_DeepPowerDown(void);\r
 203 \r
 204 /**\r
 205  * @}\r
 206  */\r
 207 \r
 208 \r
 209 #ifdef __cplusplus\r
 210 }\r
 211 #endif\r
 212 \r
 213 #endif /* LPC18XX_CLKPWR_H_ */\r
 214 \r
 215 /**\r
 216  * @}\r
 217  */\r
 218 \r
 219 /* --------------------------------- End Of File ------------------------------ */\r