git.sur5r.net Git - freertos/blob - FreeRTOS-Plus/Demo/FreeRTOS_Plus_UDP_and_CLI_LPC1830_GCC/ThirdParty/CMSISv2p10_LPC18xx_DriverLib/inc/lpc18xx_gpdma.h

   1 /**********************************************************************\r
   2 * $Id$          lpc18xx_gpdma.h         2011-06-02\r
   3 *//**\r
   4 * @file         lpc18xx_gpdma.h\r
   5 * @brief        Contains all macro definitions and function prototypes\r
   6 *                       support for GPDMA firmware library on LPC18xx\r
   7 * @version      1.0\r
   8 * @date         02. June. 2011\r
   9 * @author       NXP MCU SW Application Team\r
  10 *\r
  11 * Copyright(C) 2011, NXP Semiconductor\r
  12 * All rights reserved.\r
  13 *\r
  14 ***********************************************************************\r
  15 * Software that is described herein is for illustrative purposes only\r
  16 * which provides customers with programming information regarding the\r
  17 * products. This software is supplied "AS IS" without any warranties.\r
  18 * NXP Semiconductors assumes no responsibility or liability for the\r
  19 * use of the software, conveys no license or title under any patent,\r
  20 * copyright, or mask work right to the product. NXP Semiconductors\r
  21 * reserves the right to make changes in the software without\r
  22 * notification. NXP Semiconductors also make no representation or\r
  23 * warranty that such application will be suitable for the specified\r
  24 * use without further testing or modification.\r
  25 **********************************************************************/\r
  26 \r
  27 /* Peripheral group ----------------------------------------------------------- */\r
  28 /** @defgroup GPDMA GPDMA (General Purpose DMA)\r
  29  * @ingroup LPC1800CMSIS_FwLib_Drivers\r
  30  * @{\r
  31  */\r
  32 \r
  33 #ifndef LPC18XX_GPDMA_H_\r
  34 #define LPC18XX_GPDMA_H_\r
  35 \r
  36 /* Includes ------------------------------------------------------------------- */\r
  37 #include "LPC18xx.h"\r
  38 #include "lpc_types.h"\r
  39 \r
  40 \r
  41 #ifdef __cplusplus\r
  42 extern "C"\r
  43 {\r
  44 #endif\r
  45 \r
  46 /* Public Macros -------------------------------------------------------------- */\r
  47 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros\r
  48  * @{\r
  49  */\r
  50 \r
  51 /** DMA Connection number definitions */\r
  52 #define GPDMA_CONN_SPIFI                        ((0UL))                 /**< SPIFI                              */\r
  53 #define GPDMA_CONN_MAT0_0                       ((1UL))                 /**< MAT0.0                     */\r
  54 #define GPDMA_CONN_UART0_Tx                     ((2UL))                 /**< UART0 Tx                   */\r
  55 #define GPDMA_CONN_MAT0_1                       ((3UL))                 /**< MAT0.1                     */\r
  56 #define GPDMA_CONN_UART0_Rx                     ((4UL))                 /**< UART0 Rx                   */\r
  57 #define GPDMA_CONN_MAT1_0                       ((5UL))                 /**< MAT1.0                     */\r
  58 #define GPDMA_CONN_UART1_Tx                     ((6UL))                 /**< UART1 Tx                   */\r
  59 #define GPDMA_CONN_MAT1_1               ((7UL))                 /**< MAT1.1                     */\r
  60 #define GPDMA_CONN_UART1_Rx                     ((8UL))                 /**< UART1 Rx                   */\r
  61 #define GPDMA_CONN_MAT2_0               ((9UL))                 /**< MAT2.0                     */\r
  62 #define GPDMA_CONN_UART2_Tx                     ((10UL))                /**< UART2 Tx                   */\r
  63 #define GPDMA_CONN_MAT2_1               ((11UL))                /**< MAT2.1                     */\r
  64 #define GPDMA_CONN_UART2_Rx                     ((12UL))                /**< UART2 Rx                   */\r
  65 #define GPDMA_CONN_MAT3_0                       ((13UL))                /**< MAT3.0                     */\r
  66 #define GPDMA_CONN_UART3_Tx                     ((14UL))                /**< UART3 Tx                   */\r
  67 #define GPDMA_CONN_SCT_0                        ((15UL))                /**< SCT timer channel 0*/\r
  68 #define GPDMA_CONN_MAT3_1               ((16UL))                /**< MAT3.1                     */\r
  69 #define GPDMA_CONN_UART3_Rx                     ((17UL))                /**< UART3 Rx                   */\r
  70 #define GPDMA_CONN_SCT_1                        ((18UL))                /**< SCT timer channel 1*/\r
  71 #define GPDMA_CONN_SSP0_Rx                      ((19UL))                /**< SSP0 Rx                    */\r
  72 #define GPDMA_CONN_I2S_Channel_0        ((20UL))                /**< I2S channel 0              */\r
  73 #define GPDMA_CONN_SSP0_Tx                      ((21UL))                /**< SSP0 Tx                    */\r
  74 #define GPDMA_CONN_I2S_Channel_1        ((22UL))                /**< I2S channel 1              */\r
  75 #define GPDMA_CONN_SSP1_Rx                      ((23UL))                /**< SSP1 Rx                    */\r
  76 #define GPDMA_CONN_SSP1_Tx                      ((24UL))                /**< SSP1 Tx                    */\r
  77 #define GPDMA_CONN_ADC_0                        ((25UL))                /**< ADC 0                              */\r
  78 #define GPDMA_CONN_ADC_1                        ((26UL))                /**< ADC 1                              */\r
  79 #define GPDMA_CONN_DAC                          ((27UL))                /**< DAC                                */\r
  80 \r
  81 /** GPDMA Transfer type definitions */\r
  82 #define GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA                           ((0UL))         /**< Memory to memory - DMA control */\r
  83 #define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA                           ((1UL))         /**< Memory to peripheral - DMA control */\r
  84 #define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA                           ((2UL))         /**< Peripheral to memory - DMA control */\r
  85 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA                           ((3UL))         /**< Source peripheral to destination peripheral - DMA control */\r
  86 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL        ((4UL))         /**< Source peripheral to destination peripheral - destination peripheral control */\r
  87 #define GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL            ((5UL))         /**< Memory to peripheral - peripheral control */\r
  88 #define GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL            ((6UL))         /**< Peripheral to memory - peripheral control */\r
  89 #define GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL         ((7UL))         /**< Source peripheral to destination peripheral - source peripheral control */\r
  90 \r
  91 /** Burst size in Source and Destination definitions */\r
  92 #define GPDMA_BSIZE_1   ((0UL)) /**< Burst size = 1 */\r
  93 #define GPDMA_BSIZE_4   ((1UL)) /**< Burst size = 4 */\r
  94 #define GPDMA_BSIZE_8   ((2UL)) /**< Burst size = 8 */\r
  95 #define GPDMA_BSIZE_16  ((3UL)) /**< Burst size = 16 */\r
  96 #define GPDMA_BSIZE_32  ((4UL)) /**< Burst size = 32 */\r
  97 #define GPDMA_BSIZE_64  ((5UL)) /**< Burst size = 64 */\r
  98 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */\r
  99 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */\r
 100 \r
 101 /** Width in Source transfer width and Destination transfer width definitions */\r
 102 #define GPDMA_WIDTH_BYTE                ((0UL)) /**< Width = 1 byte */\r
 103 #define GPDMA_WIDTH_HALFWORD    ((1UL)) /**< Width = 2 bytes */\r
 104 #define GPDMA_WIDTH_WORD                ((2UL)) /**< Width = 4 bytes */\r
 105 \r
 106 /** LPC_GPDMA base addresses    */\r
 107 #define LPC_GPDMACH0_BASE       0x40002100\r
 108 #define LPC_GPDMACH1_BASE       0x40002120\r
 109 #define LPC_GPDMACH2_BASE       0x40002140\r
 110 #define LPC_GPDMACH3_BASE       0x40002160\r
 111 #define LPC_GPDMACH4_BASE       0x40002180\r
 112 #define LPC_GPDMACH5_BASE       0x400021A0\r
 113 #define LPC_GPDMACH6_BASE       0x400021C0\r
 114 #define LPC_GPDMACH7_BASE       0x400021E0\r
 115 \r
 116 /* LPC_GPDMA channels definitions       */\r
 117 #define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )\r
 118 #define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )\r
 119 #define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )\r
 120 #define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )\r
 121 #define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )\r
 122 #define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )\r
 123 #define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )\r
 124 #define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )\r
 125 /**\r
 126  * @}\r
 127  */\r
 128 \r
 129 \r
 130 /* Private Macros ------------------------------------------------------------- */\r
 131 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros\r
 132  * @{\r
 133  */\r
 134 \r
 135 /* --------------------- BIT DEFINITIONS -------------------------------------- */\r
 136 /*********************************************************************//**\r
 137  * Macro defines for DMA Interrupt Status register\r
 138  **********************************************************************/\r
 139 #define GPDMA_DMACIntStat_Ch(n)                 (((1UL<<n)&0xFF))\r
 140 #define GPDMA_DMACIntStat_BITMASK               ((0xFF))\r
 141 \r
 142 /*********************************************************************//**\r
 143  * Macro defines for DMA Interrupt Terminal Count Request Status register\r
 144  **********************************************************************/\r
 145 #define GPDMA_DMACIntTCStat_Ch(n)               (((1UL<<n)&0xFF))\r
 146 #define GPDMA_DMACIntTCStat_BITMASK             ((0xFF))\r
 147 \r
 148 /*********************************************************************//**\r
 149  * Macro defines for DMA Interrupt Terminal Count Request Clear register\r
 150  **********************************************************************/\r
 151 #define GPDMA_DMACIntTCClear_Ch(n)              (((1UL<<n)&0xFF))\r
 152 #define GPDMA_DMACIntTCClear_BITMASK    ((0xFF))\r
 153 \r
 154 /*********************************************************************//**\r
 155  * Macro defines for DMA Interrupt Error Status register\r
 156  **********************************************************************/\r
 157 #define GPDMA_DMACIntErrStat_Ch(n)              (((1UL<<n)&0xFF))\r
 158 #define GPDMA_DMACIntErrStat_BITMASK    ((0xFF))\r
 159 \r
 160 /*********************************************************************//**\r
 161  * Macro defines for DMA Interrupt Error Clear register\r
 162  **********************************************************************/\r
 163 #define GPDMA_DMACIntErrClr_Ch(n)               (((1UL<<n)&0xFF))\r
 164 #define GPDMA_DMACIntErrClr_BITMASK             ((0xFF))\r
 165 \r
 166 /*********************************************************************//**\r
 167  * Macro defines for DMA Raw Interrupt Terminal Count Status register\r
 168  **********************************************************************/\r
 169 #define GPDMA_DMACRawIntTCStat_Ch(n)    (((1UL<<n)&0xFF))\r
 170 #define GPDMA_DMACRawIntTCStat_BITMASK  ((0xFF))\r
 171 \r
 172 /*********************************************************************//**\r
 173  * Macro defines for DMA Raw Error Interrupt Status register\r
 174  **********************************************************************/\r
 175 #define GPDMA_DMACRawIntErrStat_Ch(n)   (((1UL<<n)&0xFF))\r
 176 #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))\r
 177 \r
 178 /*********************************************************************//**\r
 179  * Macro defines for DMA Enabled Channel register\r
 180  **********************************************************************/\r
 181 #define GPDMA_DMACEnbldChns_Ch(n)               (((1UL<<n)&0xFF))\r
 182 #define GPDMA_DMACEnbldChns_BITMASK             ((0xFF))\r
 183 \r
 184 /*********************************************************************//**\r
 185  * Macro defines for DMA Software Burst Request register\r
 186  **********************************************************************/\r
 187 #define GPDMA_DMACSoftBReq_Src(n)               (((1UL<<n)&0xFFFF))\r
 188 #define GPDMA_DMACSoftBReq_BITMASK              ((0xFFFF))\r
 189 \r
 190 /*********************************************************************//**\r
 191  * Macro defines for DMA Software Single Request register\r
 192  **********************************************************************/\r
 193 #define GPDMA_DMACSoftSReq_Src(n)               (((1UL<<n)&0xFFFF))\r
 194 #define GPDMA_DMACSoftSReq_BITMASK              ((0xFFFF))\r
 195 \r
 196 /*********************************************************************//**\r
 197  * Macro defines for DMA Software Last Burst Request register\r
 198  **********************************************************************/\r
 199 #define GPDMA_DMACSoftLBReq_Src(n)              (((1UL<<n)&0xFFFF))\r
 200 #define GPDMA_DMACSoftLBReq_BITMASK             ((0xFFFF))\r
 201 \r
 202 /*********************************************************************//**\r
 203  * Macro defines for DMA Software Last Single Request register\r
 204  **********************************************************************/\r
 205 #define GPDMA_DMACSoftLSReq_Src(n)              (((1UL<<n)&0xFFFF))\r
 206 #define GPDMA_DMACSoftLSReq_BITMASK             ((0xFFFF))\r
 207 \r
 208 /*********************************************************************//**\r
 209  * Macro defines for DMA Configuration register\r
 210  **********************************************************************/\r
 211 #define GPDMA_DMACConfig_E                              ((0x01))         /**< DMA Controller enable*/\r
 212 #define GPDMA_DMACConfig_M0                             ((0x02))         /**< AHB Master 0 endianness configuration*/\r
 213 #define GPDMA_DMACConfig_M1                             ((0x04))         /**< AHB Master 1 endianness configuration*/\r
 214 #define GPDMA_DMACConfig_BITMASK                ((0x07))\r
 215 \r
 216 /*********************************************************************//**\r
 217  * Macro defines for DMA Synchronization register\r
 218  **********************************************************************/\r
 219 #define GPDMA_DMACSync_Src(n)                   (((1UL<<n)&0xFFFF))\r
 220 #define GPDMA_DMACSync_BITMASK                  ((0xFFFF))\r
 221 \r
 222 /*********************************************************************//**\r
 223  * Macro defines for DMA Channel Linked List Item registers\r
 224  **********************************************************************/\r
 225 /** DMA Channel Linked List Item registers bit mask*/\r
 226 #define GPDMA_DMACCxLLI_BITMASK                 ((0xFFFFFFFC))\r
 227 \r
 228 /*********************************************************************//**\r
 229  * Macro defines for DMA channel control registers\r
 230  **********************************************************************/\r
 231 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))    /**< Transfer size*/\r
 232 #define GPDMA_DMACCxControl_SBSize(n)           (((n&0x07)<<12))        /**< Source burst size*/\r
 233 #define GPDMA_DMACCxControl_DBSize(n)           (((n&0x07)<<15))        /**< Destination burst size*/\r
 234 #define GPDMA_DMACCxControl_SWidth(n)           (((n&0x07)<<18))        /**< Source transfer width*/\r
 235 #define GPDMA_DMACCxControl_DWidth(n)           (((n&0x07)<<21))        /**< Destination transfer width*/\r
 236 #define GPDMA_DMACCxControl_SrcTransUseAHBMaster1       ((1UL<<24)) /**< Source AHB master select*/\r
 237 #define GPDMA_DMACCxControl_DestTransUseAHBMaster1      ((1UL<<25)) /**< Destination AHB master select*/\r
 238 #define GPDMA_DMACCxControl_SI                          ((1UL<<26))             /**< Source increment*/\r
 239 #define GPDMA_DMACCxControl_DI                          ((1UL<<27))             /**< Destination increment*/\r
 240 #define GPDMA_DMACCxControl_Prot1                       ((1UL<<28))             /**< Indicates that the access is in user mode or privileged mode*/\r
 241 #define GPDMA_DMACCxControl_Prot2                       ((1UL<<29))             /**< Indicates that the access is bufferable or not bufferable*/\r
 242 #define GPDMA_DMACCxControl_Prot3                       ((1UL<<30))             /**< Indicates that the access is cacheable or not cacheable*/\r
 243 #define GPDMA_DMACCxControl_I                           ((1UL<<31))             /**< Terminal count interrupt enable bit */\r
 244 /** DMA channel control registers bit mask */\r
 245 #define GPDMA_DMACCxControl_BITMASK                     ((0xFCFFFFFF))\r
 246 \r
 247 /*********************************************************************//**\r
 248  * Macro defines for DMA Channel Configuration registers\r
 249  **********************************************************************/\r
 250 #define GPDMA_DMACCxConfig_E                                    ((1UL<<0))                      /**< DMA control enable*/\r
 251 #define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n&0x1F)<<1))         /**< Source peripheral*/\r
 252 #define GPDMA_DMACCxConfig_DestPeripheral(n)    (((n&0x1F)<<6))         /**< Destination peripheral*/\r
 253 #define GPDMA_DMACCxConfig_TransferType(n)              (((n&0x7)<<11))         /**< This value indicates the type of transfer*/\r
 254 #define GPDMA_DMACCxConfig_IE                                   ((1UL<<14))                     /**< Interrupt error mask*/\r
 255 #define GPDMA_DMACCxConfig_ITC                                  ((1UL<<15))             /**< Terminal count interrupt mask*/\r
 256 #define GPDMA_DMACCxConfig_L                                    ((1UL<<16))             /**< Lock*/\r
 257 #define GPDMA_DMACCxConfig_A                                    ((1UL<<17))             /**< Active*/\r
 258 #define GPDMA_DMACCxConfig_H                                    ((1UL<<18))             /**< Halt*/\r
 259 /** DMA Channel Configuration registers bit mask */\r
 260 #define GPDMA_DMACCxConfig_BITMASK                              ((0x7FFFF))\r
 261 \r
 262 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */\r
 263 /* Macros check GPDMA channel */\r
 264 #define PARAM_GPDMA_CHANNEL(n)  (n<=7)\r
 265 \r
 266 /* Macros check GPDMA connection type */\r
 267 #define PARAM_GPDMA_CONN(n)             ((n==GPDMA_CONN_SPIFI) || (n==GPDMA_CONN_DAC) \\r
 268 || (n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \\r
 269 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \\r
 270 || (n==GPDMA_CONN_ADC_0)   || (n==GPDMA_CONN_ADC_1) \\r
 271 || (n==GPDMA_CONN_I2S_Channel_0) || (n==GPDMA_CONN_I2S_Channel_1) \\r
 272 || (n==GPDMA_CONN_SCT_0)   || (n==GPDMA_CONN_SCT_1) \\r
 273 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \\r
 274 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \\r
 275 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \\r
 276 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \\r
 277 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \\r
 278 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \\r
 279 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \\r
 280 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))\r
 281 \r
 282 /* Macros check GPDMA burst size type */\r
 283 #define PARAM_GPDMA_BSIZE(n)    ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \\r
 284 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \\r
 285 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \\r
 286 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))\r
 287 \r
 288 /* Macros check GPDMA width type */\r
 289 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \\r
 290 || (n==GPDMA_WIDTH_WORD))\r
 291 \r
 292 /* Macros check GPDMA status type */\r
 293 #define PARAM_GPDMA_STAT(n)     ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \\r
 294 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \\r
 295 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))\r
 296 \r
 297 /* Macros check GPDMA transfer type */\r
 298 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA) \\r
 299 ||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA)\\r
 300 ||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL)||(n==GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL)\\r
 301 ||(n==GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL)||(n==GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL))\r
 302 \r
 303 /* Macros check GPDMA state clear type */\r
 304 #define PARAM_GPDMA_STATCLR(n)  ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))\r
 305 \r
 306 /**\r
 307  * @}\r
 308  */\r
 309 \r
 310 \r
 311 /* Public Types --------------------------------------------------------------- */\r
 312 /** @defgroup GPDMA_Public_Types GPDMA Public Types\r
 313  * @{\r
 314  */\r
 315 \r
 316 /**\r
 317  * @brief GPDMA Channel Registers\r
 318  */\r
 319 typedef struct\r
 320 {\r
 321   __IO uint32_t CSrcAddr;\r
 322   __IO uint32_t CDestAddr;\r
 323   __IO uint32_t CLLI;\r
 324   __IO uint32_t CControl;\r
 325   __IO uint32_t CConfig;\r
 326 } LPC_GPDMACH_TypeDef;\r
 327 \r
 328 /**\r
 329  * @brief GPDMA Status enumeration\r
 330  */\r
 331 typedef enum {\r
 332         GPDMA_STAT_INT,                 /**< GPDMA Interrupt Status */\r
 333         GPDMA_STAT_INTTC,               /**< GPDMA Interrupt Terminal Count Request Status */\r
 334         GPDMA_STAT_INTERR,              /**< GPDMA Interrupt Error Status */\r
 335         GPDMA_STAT_RAWINTTC,    /**< GPDMA Raw Interrupt Terminal Count Status */\r
 336         GPDMA_STAT_RAWINTERR,   /**< GPDMA Raw Error Interrupt Status */\r
 337         GPDMA_STAT_ENABLED_CH   /**< GPDMA Enabled Channel Status */\r
 338 } GPDMA_Status_Type;\r
 339 \r
 340 /**\r
 341  * @brief GPDMA Interrupt clear status enumeration\r
 342  */\r
 343 typedef enum{\r
 344         GPDMA_STATCLR_INTTC,    /**< GPDMA Interrupt Terminal Count Request Clear */\r
 345         GPDMA_STATCLR_INTERR    /**< GPDMA Interrupt Error Clear */\r
 346 }GPDMA_StateClear_Type;\r
 347 \r
 348 /**\r
 349  * @brief GPDMA Channel configuration structure type definition\r
 350  */\r
 351 typedef struct {\r
 352         uint32_t ChannelNum;    /**< DMA channel number, should be in\r
 353                                                                 range from 0 to 7.\r
 354                                                                 Note: DMA channel 0 has the highest priority\r
 355                                                                 and DMA channel 7 the lowest priority.\r
 356                                                                 */\r
 357         uint32_t TransferSize;  /**< Length/Size of transfer */\r
 358         uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */\r
 359         uint32_t SrcMemAddr;    /**< Physical Source Address, used in case TransferType is chosen as\r
 360                                                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */\r
 361         uint32_t DstMemAddr;    /**< Physical Destination Address, used in case TransferType is chosen as\r
 362                                                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */\r
 363         uint32_t TransferType;  /**< Transfer Type, should be one of the following:\r
 364                                                         - GPDMA_TRANSFERTYPE_M2M_CONTROLLER_DMA: Memory to memory - DMA control\r
 365                                                         - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_DMA: Memory to peripheral - DMA control\r
 366                                                         - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_DMA: Peripheral to memory - DMA control\r
 367                                                         - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DMA: Source peripheral to destination peripheral - DMA control\r
 368                                                         - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_DestPERIPHERAL: Source peripheral to destination peripheral - destination peripheral control\r
 369                                                         - GPDMA_TRANSFERTYPE_M2P_CONTROLLER_PERIPHERAL: Memory to peripheral - peripheral control\r
 370                                                         - GPDMA_TRANSFERTYPE_P2M_CONTROLLER_PERIPHERAL: Peripheral to memory - peripheral control\r
 371                                                         - GPDMA_TRANSFERTYPE_P2P_CONTROLLER_SrcPERIPHERAL:      Source peripheral to destination peripheral - source peripheral control\r
 372                                                         */\r
 373         uint32_t SrcConn;               /**< Peripheral Source Connection type, used in case TransferType is chosen as\r
 374                                                         GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of\r
 375                                                         following:\r
 376                                                          - GPDMA_CONN_SSP0_Tx: SSP0, Tx\r
 377                                                          - GPDMA_CONN_SSP0_Rx: SSP0, Rx\r
 378                                                          - GPDMA_CONN_SSP1_Tx: SSP1, Tx\r
 379                                                          - GPDMA_CONN_SSP1_Rx: SSP1, Rx\r
 380                                                          - GPDMA_CONN_ADC_0: ADC0\r
 381                                                          - GPDMA_CONN_ADC_1: ADC1\r
 382                                                          - GPDMA_CONN_SCT_0: SCT0\r
 383                                                          - GPDMA_CONN_SCT_1: SCT1\r
 384                                                          - GPDMA_CONN_I2S_Channel_0: I2S Channel 0\r
 385                                                          - GPDMA_CONN_I2S_Channel_1: I2S Channel 1\r
 386                                                          - GPDMA_CONN_DAC: DAC\r
 387                                                          - GPDMA_CONN_SPIFI: SPIFI\r
 388                                                          - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0\r
 389                                                          - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1\r
 390                                                          - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0\r
 391                                                          - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1\r
 392                                                          - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0\r
 393                                                          - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1\r
 394                                                          - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0\r
 395                                                          - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1\r
 396                                                          */\r
 397         uint32_t DstConn;               /**< Peripheral Destination Connection type, used in case TransferType is chosen as\r
 398                                                         GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of\r
 399                                                         following:\r
 400                                                          - GPDMA_CONN_SSP0_Tx: SSP0, Tx\r
 401                                                          - GPDMA_CONN_SSP0_Rx: SSP0, Rx\r
 402                                                          - GPDMA_CONN_SSP1_Tx: SSP1, Tx\r
 403                                                          - GPDMA_CONN_SSP1_Rx: SSP1, Rx\r
 404                                                          - GPDMA_CONN_ADC_0: ADC0\r
 405                                                          - GPDMA_CONN_ADC_1: ADC1\r
 406                                                          - GPDMA_CONN_SCT_0: SCT0\r
 407                                                          - GPDMA_CONN_SCT_1: SCT1\r
 408                                                          - GPDMA_CONN_I2S_Channel_0: I2S Channel 0\r
 409                                                          - GPDMA_CONN_I2S_Channel_1: I2S Channel 1\r
 410                                                          - GPDMA_CONN_DAC: DAC\r
 411                                                          - GPDMA_CONN_SPIFI: SPIFI\r
 412                                                          - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0\r
 413                                                          - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1\r
 414                                                          - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0\r
 415                                                          - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1\r
 416                                                          - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0\r
 417                                                          - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1\r
 418                                                          - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0\r
 419                                                          - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1\r
 420                                                          */\r
 421         uint32_t DMALLI;                /**< Linker List Item structure data address\r
 422                                                         if there's no Linker List, set as '0'\r
 423                                                         */\r
 424 } GPDMA_Channel_CFG_Type;\r
 425 \r
 426 /**\r
 427  * @brief GPDMA Linker List Item structure type definition\r
 428  */\r
 429 typedef struct {\r
 430         uint32_t SrcAddr;       /**< Source Address */\r
 431         uint32_t DstAddr;       /**< Destination address */\r
 432         uint32_t NextLLI;       /**< Next LLI address, otherwise set to '0' */\r
 433         uint32_t Control;       /**< GPDMA Control of this LLI */\r
 434 } GPDMA_LLI_Type;\r
 435 \r
 436 \r
 437 /**\r
 438  * @}\r
 439  */\r
 440 \r
 441 /* Public Functions ----------------------------------------------------------- */\r
 442 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions\r
 443  * @{\r
 444  */\r
 445 \r
 446 void GPDMA_Init(void);\r
 447 \r
 448 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);\r
 449 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);\r
 450 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);\r
 451 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);\r
 452 \r
 453 /**\r
 454  * @}\r
 455  */\r
 456 \r
 457 \r
 458 #ifdef __cplusplus\r
 459 }\r
 460 #endif\r
 461 \r
 462 #endif /* LPC18XX_GPDMA_H_ */\r
 463 \r
 464 /**\r
 465  * @}\r
 466  */\r
 467 \r
 468 /* --------------------------------- End Of File ------------------------------ */\r