1 /**********************************************************************
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2 * $Id$ lpc18xx_ssp.h 2011-06-02
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4 * @file lpc18xx_ssp.h
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5 * @brief Contains all macro definitions and function prototypes
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6 * support for SSP firmware library on LPC18xx
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8 * @date 02. June. 2011
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9 * @author NXP MCU SW Application Team
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11 * Copyright(C) 2011, NXP Semiconductor
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12 * All rights reserved.
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14 ***********************************************************************
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15 * Software that is described herein is for illustrative purposes only
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16 * which provides customers with programming information regarding the
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17 * products. This software is supplied "AS IS" without any warranties.
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18 * NXP Semiconductors assumes no responsibility or liability for the
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19 * use of the software, conveys no license or title under any patent,
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20 * copyright, or mask work right to the product. NXP Semiconductors
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21 * reserves the right to make changes in the software without
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22 * notification. NXP Semiconductors also make no representation or
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23 * warranty that such application will be suitable for the specified
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24 * use without further testing or modification.
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25 **********************************************************************/
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27 /* Peripheral group ----------------------------------------------------------- */
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28 /** @defgroup SSP SSP (Synchronous Serial Port)
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29 * @ingroup LPC1800CMSIS_FwLib_Drivers
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33 #ifndef LPC18XX_SSP_H_
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34 #define LPC18XX_SSP_H_
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36 /* Includes ------------------------------------------------------------------- */
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37 #include "LPC18xx.h"
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38 #include "lpc_types.h"
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46 /* Public Macros -------------------------------------------------------------- */
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47 /** @defgroup SSP_Private_Macros SSP Private Macros
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51 /*********************************************************************//**
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52 * SSP configuration parameter defines
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53 **********************************************************************/
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54 /** Clock phase control bit */
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55 #define SSP_CPHA_FIRST ((uint32_t)(0))
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56 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
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59 /** Clock polarity control bit */
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60 /* There's no bug here!!!
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61 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
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62 * That means the active clock is in HI state.
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63 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
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64 * high between frames. That means the active clock is in LO state.
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66 #define SSP_CPOL_HI ((uint32_t)(0))
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67 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
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69 /** SSP master mode enable */
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70 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
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71 #define SSP_MASTER_MODE ((uint32_t)(0))
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73 /** SSP data bit number defines */
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74 #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
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75 #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
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76 #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
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77 #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
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78 #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
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79 #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
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80 #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
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81 #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
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82 #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
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83 #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
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84 #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
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85 #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
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86 #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
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88 /** SSP Frame Format definition */
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89 /** Motorola SPI mode */
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90 #define SSP_FRAME_SPI SSP_CR0_FRF_SPI
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91 /** TI synchronous serial mode */
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92 #define SSP_FRAME_TI SSP_CR0_FRF_TI
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93 /** National Micro-wire mode */
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94 #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
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96 /*********************************************************************//**
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97 * SSP Status defines
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98 **********************************************************************/
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99 /** SSP status TX FIFO Empty bit */
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100 #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
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101 /** SSP status TX FIFO not full bit */
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102 #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
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103 /** SSP status RX FIFO not empty bit */
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104 #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
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105 /** SSP status RX FIFO full bit */
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106 #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
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107 /** SSP status SSP Busy bit */
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108 #define SSP_STAT_BUSY SSP_SR_BSY
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110 /*********************************************************************//**
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111 * SSP Interrupt Configuration defines
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112 **********************************************************************/
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113 /** Receive Overrun */
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114 #define SSP_INTCFG_ROR SSP_IMSC_ROR
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115 /** Receive TimeOut */
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116 #define SSP_INTCFG_RT SSP_IMSC_RT
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117 /** Rx FIFO is at least half full */
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118 #define SSP_INTCFG_RX SSP_IMSC_RX
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119 /** Tx FIFO is at least half empty */
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120 #define SSP_INTCFG_TX SSP_IMSC_TX
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122 /*********************************************************************//**
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123 * SSP Configured Interrupt Status defines
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124 **********************************************************************/
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125 /** Receive Overrun */
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126 #define SSP_INTSTAT_ROR SSP_MIS_ROR
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127 /** Receive TimeOut */
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128 #define SSP_INTSTAT_RT SSP_MIS_RT
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129 /** Rx FIFO is at least half full */
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130 #define SSP_INTSTAT_RX SSP_MIS_RX
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131 /** Tx FIFO is at least half empty */
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132 #define SSP_INTSTAT_TX SSP_MIS_TX
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134 /*********************************************************************//**
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135 * SSP Raw Interrupt Status defines
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136 **********************************************************************/
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137 /** Receive Overrun */
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138 #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
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139 /** Receive TimeOut */
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140 #define SSP_INTSTAT_RAW_RT SSP_RIS_RT
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141 /** Rx FIFO is at least half full */
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142 #define SSP_INTSTAT_RAW_RX SSP_RIS_RX
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143 /** Tx FIFO is at least half empty */
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144 #define SSP_INTSTAT_RAW_TX SSP_RIS_TX
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146 /*********************************************************************//**
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147 * SSP Interrupt Clear defines
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148 **********************************************************************/
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149 /** Writing a 1 to this bit clears the "frame was received when
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150 * RxFIFO was full" interrupt */
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151 #define SSP_INTCLR_ROR SSP_ICR_ROR
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152 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
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153 * has not been read for a timeout period" interrupt */
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154 #define SSP_INTCLR_RT SSP_ICR_RT
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156 /*********************************************************************//**
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158 **********************************************************************/
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159 /** SSP bit for enabling RX DMA */
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160 #define SSP_DMA_TX SSP_DMA_RXDMA_EN
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161 /** SSP bit for enabling TX DMA */
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162 #define SSP_DMA_RX SSP_DMA_TXDMA_EN
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164 /* SSP Status Implementation definitions */
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165 #define SSP_STAT_DONE (1UL<<8) /**< Done */
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166 #define SSP_STAT_ERROR (1UL<<9) /**< Error */
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169 /* --------------------- BIT DEFINITIONS -------------------------------------- */
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170 /*********************************************************************//**
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171 * Macro defines for CR0 register
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172 **********************************************************************/
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173 /** SSP data size select, must be 4 bits to 16 bits */
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174 #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
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175 /** SSP control 0 Motorola SPI mode */
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176 #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
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177 /** SSP control 0 TI synchronous serial mode */
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178 #define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
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179 /** SSP control 0 National Micro-wire mode */
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180 #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
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181 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
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182 bus clock high between frames, (0) = low */
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183 #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
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184 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
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185 on the second clock transition of the frame, (0) = first */
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186 #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
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187 /** SSP serial clock rate value load macro, divider rate is
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188 PERIPH_CLK / (cpsr * (SCR + 1)) */
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189 #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
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190 /** SSP CR0 bit mask */
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191 #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
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193 /*********************************************************************//**
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194 * Macro defines for CR1 register
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195 **********************************************************************/
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196 /** SSP control 1 loopback mode enable bit */
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197 #define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
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198 /** SSP control 1 enable bit */
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199 #define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
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200 /** SSP control 1 slave enable */
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201 #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
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202 /** SSP control 1 slave out disable bit, disables transmit line in slave
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204 #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
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205 /** SSP CR1 bit mask */
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206 #define SSP_CR1_BITMASK ((uint32_t)(0x0F))
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208 /*********************************************************************//**
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209 * Macro defines for DR register
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210 **********************************************************************/
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211 /** SSP data bit mask */
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212 #define SSP_DR_BITMASK(n) ((n)&0xFFFF)
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214 /*********************************************************************//**
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215 * Macro defines for SR register
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216 **********************************************************************/
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217 /** SSP status TX FIFO Empty bit */
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218 #define SSP_SR_TFE ((uint32_t)(1<<0))
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219 /** SSP status TX FIFO not full bit */
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220 #define SSP_SR_TNF ((uint32_t)(1<<1))
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221 /** SSP status RX FIFO not empty bit */
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222 #define SSP_SR_RNE ((uint32_t)(1<<2))
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223 /** SSP status RX FIFO full bit */
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224 #define SSP_SR_RFF ((uint32_t)(1<<3))
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225 /** SSP status SSP Busy bit */
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226 #define SSP_SR_BSY ((uint32_t)(1<<4))
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227 /** SSP SR bit mask */
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228 #define SSP_SR_BITMASK ((uint32_t)(0x1F))
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230 /*********************************************************************//**
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231 * Macro defines for CPSR register
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232 **********************************************************************/
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233 /** SSP clock prescaler */
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234 #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
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235 /** SSP CPSR bit mask */
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236 #define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
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238 /*********************************************************************//**
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239 * Macro define for (IMSC) Interrupt Mask Set/Clear registers
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240 **********************************************************************/
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241 /** Receive Overrun */
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242 #define SSP_IMSC_ROR ((uint32_t)(1<<0))
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243 /** Receive TimeOut */
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244 #define SSP_IMSC_RT ((uint32_t)(1<<1))
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245 /** Rx FIFO is at least half full */
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246 #define SSP_IMSC_RX ((uint32_t)(1<<2))
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247 /** Tx FIFO is at least half empty */
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248 #define SSP_IMSC_TX ((uint32_t)(1<<3))
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249 /** IMSC bit mask */
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250 #define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
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252 /*********************************************************************//**
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253 * Macro define for (RIS) Raw Interrupt Status registers
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254 **********************************************************************/
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255 /** Receive Overrun */
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256 #define SSP_RIS_ROR ((uint32_t)(1<<0))
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257 /** Receive TimeOut */
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258 #define SSP_RIS_RT ((uint32_t)(1<<1))
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259 /** Rx FIFO is at least half full */
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260 #define SSP_RIS_RX ((uint32_t)(1<<2))
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261 /** Tx FIFO is at least half empty */
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262 #define SSP_RIS_TX ((uint32_t)(1<<3))
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263 /** RIS bit mask */
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264 #define SSP_RIS_BITMASK ((uint32_t)(0x0F))
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266 /*********************************************************************//**
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267 * Macro define for (MIS) Masked Interrupt Status registers
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268 **********************************************************************/
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269 /** Receive Overrun */
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270 #define SSP_MIS_ROR ((uint32_t)(1<<0))
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271 /** Receive TimeOut */
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272 #define SSP_MIS_RT ((uint32_t)(1<<1))
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273 /** Rx FIFO is at least half full */
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274 #define SSP_MIS_RX ((uint32_t)(1<<2))
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275 /** Tx FIFO is at least half empty */
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276 #define SSP_MIS_TX ((uint32_t)(1<<3))
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277 /** MIS bit mask */
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278 #define SSP_MIS_BITMASK ((uint32_t)(0x0F))
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280 /*********************************************************************//**
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281 * Macro define for (ICR) Interrupt Clear registers
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282 **********************************************************************/
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283 /** Writing a 1 to this bit clears the "frame was received when
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284 * RxFIFO was full" interrupt */
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285 #define SSP_ICR_ROR ((uint32_t)(1<<0))
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286 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
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287 * has not been read for a timeout period" interrupt */
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288 #define SSP_ICR_RT ((uint32_t)(1<<1))
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289 /** ICR bit mask */
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290 #define SSP_ICR_BITMASK ((uint32_t)(0x03))
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292 /*********************************************************************//**
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293 * Macro defines for DMACR register
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294 **********************************************************************/
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295 /** SSP bit for enabling RX DMA */
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296 #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
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297 /** SSP bit for enabling TX DMA */
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298 #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
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299 /** DMACR bit mask */
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300 #define SSP_DMA_BITMASK ((uint32_t)(0x03))
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303 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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304 /** Macro to determine if it is valid SSP port number */
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305 #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
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306 || (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
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308 /** Macro check clock phase control mode */
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309 #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
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311 /** Macro check clock polarity mode */
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312 #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
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314 /* Macro check master/slave mode */
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315 #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
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317 /* Macro check databit value */
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318 #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
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319 || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
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320 || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
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321 || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
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322 || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
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323 || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
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324 || (n==SSP_DATABIT_15))
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326 /* Macro check frame type */
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327 #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
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328 || (n==SSP_FRAME_MICROWIRE))
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330 /* Macro check SSP status */
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331 #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
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332 || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
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333 || (n==SSP_STAT_BUSY))
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335 /* Macro check interrupt configuration */
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336 #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
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337 || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
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339 /* Macro check interrupt status value */
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340 #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
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341 || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
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343 /* Macro check interrupt status raw value */
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344 #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
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345 || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
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347 /* Macro check interrupt clear mode */
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348 #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
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350 /* Macro check DMA mode */
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351 #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
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357 /* Public Types --------------------------------------------------------------- */
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358 /** @defgroup SSP_Public_Types SSP Public Types
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362 /** @brief SSP configuration structure */
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364 uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
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365 where x is in range from 4 - 16 */
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366 uint32_t CPHA; /** Clock phase, should be:
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367 - SSP_CPHA_FIRST: first clock edge
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368 - SSP_CPHA_SECOND: second clock edge */
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369 uint32_t CPOL; /** Clock polarity, should be:
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370 - SSP_CPOL_HI: high level
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371 - SSP_CPOL_LO: low level */
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372 uint32_t Mode; /** SSP mode, should be:
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373 - SSP_MASTER_MODE: Master mode
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374 - SSP_SLAVE_MODE: Slave mode */
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375 uint32_t FrameFormat; /** Frame Format:
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376 - SSP_FRAME_SPI: Motorola SPI frame format
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377 - SSP_FRAME_TI: TI frame format
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378 - SSP_FRAME_MICROWIRE: National Microwire frame format */
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379 uint32_t ClockRate; /** Clock rate,in Hz */
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383 * @brief SSP Transfer Type definitions
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386 SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
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387 SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
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388 } SSP_TRANSFER_Type;
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391 * @brief SPI Data configuration structure definitions
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394 void *tx_data; /**< Pointer to transmit data */
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395 uint32_t tx_cnt; /**< Transmit counter */
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396 void *rx_data; /**< Pointer to transmit data */
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397 uint32_t rx_cnt; /**< Receive counter */
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398 uint32_t length; /**< Length of transfer data */
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399 uint32_t status; /**< Current status of SSP activity */
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400 } SSP_DATA_SETUP_Type;
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408 /* Public Functions ----------------------------------------------------------- */
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409 /** @defgroup SSP_Public_Functions SSP Public Functions
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413 void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
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414 void SSP_DeInit(LPC_SSPn_Type* SSPx);
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416 void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
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417 void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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418 void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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419 void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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420 void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);
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421 uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);
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422 int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
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423 SSP_TRANSFER_Type xfType);
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424 FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);
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425 uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);
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426 void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);
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427 IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);
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428 IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);
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429 void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);
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430 void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);
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440 #endif /* LPC18XX_SSP_H_ */
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446 /* --------------------------------- End Of File ------------------------------ */
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