2 * @brief Enhanced Host Controller Interface
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5 * Copyright(C) NXP Semiconductors, 2012
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6 * All rights reserved.
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9 * Software that is described herein is for illustrative purposes only
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10 * which provides customers with programming information regarding the
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11 * LPC products. This software is supplied "AS IS" without any warranties of
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12 * any kind, and NXP Semiconductors and its licensor disclaim any and
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13 * all warranties, express or implied, including all implied warranties of
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14 * merchantability, fitness for a particular purpose and non-infringement of
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15 * intellectual property rights. NXP Semiconductors assumes no responsibility
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16 * or liability for the use of the software, conveys no license or rights under any
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17 * patent, copyright, mask work right, or any other intellectual property rights in
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18 * or to any products. NXP Semiconductors reserves the right to make changes
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19 * in the software without notification. NXP Semiconductors also makes no
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20 * representation or warranty that such application will be suitable for the
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21 * specified use without further testing or modification.
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24 * Permission to use, copy, modify, and distribute this software and its
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25 * documentation is hereby granted, under NXP Semiconductors' and its
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26 * licensor's relevant copyrights in the software, without fee, provided that it
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27 * is used in conjunction with NXP Semiconductors microcontrollers. This
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28 * copyright, permission, and disclaimer notice must appear in all copies of
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31 /** @ingroup Group_HCD
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32 * @defgroup Host_EHCI Enhanced Host Controller Interface Driver
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35 #ifndef __LPC_EHCI_H__
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36 #define __LPC_EHCI_H__
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38 #ifndef __LPC_EHCI_C__ // TODO INCLUDE FROM EHCI.C
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39 #error "EHCI.h is private header and can only be included by EHCI.c, try to include HCD.h instead"
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42 #ifdef __TEST__ // suppress static/inline for Testing purpose
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47 /*=======================================================================*/
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48 /* EHCI C O N F I G U R A T I O N */
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49 /*=======================================================================*/
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50 #define HCD_MAX_QHD HCD_MAX_ENDPOINT /* USBD_USB_HC_EHCI */
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51 //#define HCD_MAX_QTD (HCD_MAX_ENDPOINT+3) /* USBD_USB_HC_EHCI */
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52 #define HCD_MAX_QTD 8 /* USBD_USB_HC_EHCI */
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53 #define HCD_MAX_HS_ITD 4 /* USBD_USB_HC_EHCI */
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54 #define HCD_MAX_SITD 16 /* USBD_USB_HC_EHCI */
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56 #define FRAMELIST_SIZE_BITS 5 /* (0:1024) - (1:512) - (2:256) - (3:128) - (4:64) - (5:32) - (6:16) - (7:8) */
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57 #define FRAME_LIST_SIZE (1024 >> FRAMELIST_SIZE_BITS)
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59 /**********************/
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60 /* USBCMD Register */
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61 /**********************/
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62 #define INT_THRESHOLD_CTRL 0x00080000UL/* Max Int Interval = 8 uframes */
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63 #define ASYNC_SCHEDULE_PARK_MODE_ENABLE NO
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64 #define ASYNC_SCHEDULE_PARK_MODE_COUNT 0
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66 /****************************/
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67 /* USBSTS Register */
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68 /****************************/
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70 /**************************************************/
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71 /* USBINTR Register */
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72 /**************************************************/
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73 #define INT_SOF_RECEIVED_ENABLE NO
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74 // #define INT_ASYNC_ADVANCE_ENABLE Must be YES
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75 // #define INT_SYSTEM_ERR_ENABLE Must be YES
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76 #define INT_FRAME_ROLL_OVER_ENABLE NO
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77 // #define INT_PORT_CHANGE_ENABLE Must be YES
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78 // #define INT_USB_ERR_ENABLE Must be YES
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79 // #define INT_USB_ENABLE Must be YES (NO for NXP chips in favor of UAI, UPI)
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80 // #define INT_USB_ASYNC_INT_ENABLE Must be YES
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81 // #define INT_USB_PERIOD_INT_ENABLE Must be YES
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83 /********************************************/
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84 /* PORTSC Register */
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85 /********************************************/
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86 #define PORT_WAKE_OVER_CURRENT NO
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87 #define PORT_WAKE_ON_DISCONNECT NO
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88 #define PORT_WAKE_ON_CONNECT NO
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89 #define PORT_INDICATOR NO
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91 /*==========================================================================*/
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92 /* EHCI LOCAL DECLARATIONS */
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93 /*==========================================================================*/
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95 /*==========================================================================*/
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96 /* EHCI REGISTERS */
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97 /*==========================================================================*/
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98 /* Bit field definition for USBMODE_H */
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99 #define USBMODE_DeviceController (2)
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100 #define USBMODE_HostController (3)
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101 #define USBMODE_VBusPowerSelect_High (1 << 5)
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103 /* Bit field definition for register UsbCmd */
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104 #define EHC_USBCMD_RunStop 0x00000001UL /* Run or Stop */
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105 #define EHC_USBCMD_HostReset 0x00000002UL /* Host Controller Reset */
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106 #define EHC_USBCMD_FrameListSize 0x0000000CUL /* Frame List Size */
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107 #define EHC_USBCMD_PeriodScheduleEnable 0x00000010UL /* Periodic Schedule Enable */
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108 #define EHC_USBCMD_AsynScheduleEnable 0x00000020UL /* Asynchronous Schedule Enable */
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109 #define EHC_USBCMD_IntAsyncAdvanceDoorbell 0x00000040UL /* Interrupt on Async Advance Doorbell */
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110 #define EHC_USBCMD_LightReset 0x00000080UL /* Light Host Controller Reset */
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111 #define EHC_USBCMD_AsyncScheduleParkCount 0x00000300UL /* Asynchronous Schedule Park Mode Count */
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112 #define EHC_USBCMD_AsyncScheduleParkEnable 0x00000800UL /* Asynchronous Schedule Park Mode Enable */
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113 #define EHC_USBCMD_FrameListSizeBit2 0x00008000UL /* Frame List Size bit 2 - EHCI derivation */
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114 #define EHC_USBCMD_InterruptThresholdControl 0x00FF0000UL /* Interrupt Threshold control */
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116 /* Bit field definition for register UsbStatus */
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117 #define EHC_USBSTS_UsbInt 0x00000001UL /* USB Interrupt */
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118 #define EHC_USBSTS_UsbErrorInt 0x00000002UL /* USB Error Interrupt */
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119 #define EHC_USBSTS_PortChangeDetect 0x00000004UL /* Port Change Detect */
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120 #define EHC_USBSTS_FrameListRollover 0x00000008UL /* Frame List Rollover */
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121 #define EHC_USBSTS_HostSystemError 0x00000010UL /* Host System Error */
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122 #define EHC_USBSTS_IntAsyncAdvance 0x00000020UL /* Interrupt on Async Advance */
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123 #define EHC_USBSTS_SofRecieveInt 0x00000080UL /* SOF - EHCI derivation */
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124 #define EHC_USBSTS_HCHalted 0x00001000UL /* HCHalted */
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125 #define EHC_USBSTS_Reclamation 0x00002000UL /* Reclamation */
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126 #define EHC_USBSTS_PeriodScheduleStatus 0x00004000UL /* Periodic Schedule Status */
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127 #define EHC_USBSTS_AsyncScheduleStatus 0x00008000UL /* Asynchronous Schedule Status */
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128 #define EHC_USBSTS_UsbAsyncInt 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */
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129 #define EHC_USBSTS_UsbPeriodInt 0x00080000UL /* USB Period Interrupt - EHCI derivation */
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131 /* Bit field definition for register UsbIntr */
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132 #define EHC_USBINTR_UsbIntEnable 0x00000001UL /* USB Interrupt Enable */
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133 #define EHC_USBINTR_UsbErroIntEnable 0x00000002UL /* USB Error Interrupt Enable */
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134 #define EHC_USBINTR_PortChangeIntEnable 0x00000004UL /* Port Change Interrupt Enable */
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135 #define EHC_USBINTR_FrameListRolloverEnable 0x00000008UL /* Frame List Rollover Enable */
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136 #define EHC_USBINTR_HostSystemErrorEnable 0x00000010UL /* Host System Error Enable */
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137 #define EHC_USBINTR_IntAsyncAdvanceEnable 0x00000020UL /* Interrupt on Async Advance Enable */
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138 #define EHC_USBINTR_SofRecieveEnable 0x00000080UL /* SOF - EHCI derivation */
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139 #define EHC_USBINTR_UsbAsyncEnable 0x00040000UL /* USB Asynchronous Interrupt - EHCI derivation */
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140 #define EHC_USBINTR_UsbPeriodEnable 0x00080000UL /* USB Period Interrupt - EHCI derivation */
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141 #define EHC_USBINTR_ALL 0x000C00BFUL /* All Interrupt */
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143 /* Bit field definition for register FrIndex */
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144 #define EHC_FRINDEX_MASK 0x000003FFUL /* Frame Index */
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145 #define EHC_UFRAME_MASK 0x00000007UL /* u-Frame Index */
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146 #define EHC_MFRAME_MASK 0x00001FF8UL /* m-Frame Index */
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148 /* Bit field definition for register PortSC */
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149 #define EHC_PORTSC_CurrentConnectStatus 0x00000001UL /* Current Connect Status */
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150 #define EHC_PORTSC_ConnectStatusChange 0x00000002UL /* Connect Status Change */
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151 #define EHC_PORTSC_PortEnable 0x00000004UL /* Port Enabled Status */
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152 #define EHC_PORTSC_PortEnableChange 0x00000008UL /* Port Enabled/Disabled Change */
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153 #define EHC_PORTSC_OvercurrentActive 0x00000010UL /* Over-current Status */
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154 #define EHC_PORTSC_OvercurrentChange 0x00000020UL /* Over-current Change */
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155 #define EHC_PORTSC_ForcePortResume 0x00000040UL /* Force Port Resume */
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156 #define EHC_PORTSC_PortSuspend 0x00000080UL /* Port Suspend */
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157 #define EHC_PORTSC_PortReset 0x00000100UL /* Port Reset */
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158 #define EHC_PORTSC_LineStatus 0x00000C00UL /* Line Status */
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159 #define EHC_PORTSC_PortPowerControl 0x00001000UL /* Port Power Status */
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160 #define EHC_PORTSC_PortOwner 0x00002000UL /* Port Owner Status */
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161 #define EHC_PORTSC_PortIndicatorControl 0x0000C000UL /* Port Indicator Control */
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162 #define EHC_PORTSC_PortTestControl 0x000F0000UL /* Port Test Control */
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163 #define EHC_PORTSC_WakeonConnectEnable 0x00100000UL /* Wake on Connect Enable */
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164 #define EHC_PORTSC_WakeonDisconnectEnable 0x00200000UL /* Wake on Disconnect Enable */
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165 #define EHC_PORTSC_WakeonOvercurrentEnable 0x00400000UL /* Wake on Over-Current Enable */
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166 #define EHC_PORTSC_PhyClockDisable 0x00800000UL /* PHY Clock Disable - EHCI derivation */
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167 #define EHC_PORTSC_PortForceFullspeedConnect 0x01000000UL /* Force Device on Fullspeed mode (disable chirp sequences) - EHCI derivation */
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168 #define EHC_PORTSC_PortSpeed 0x0C000000UL /* Device Speed - EHCI derivation */
\r
170 /* Definitions for Frame List Element Pointer */
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171 #define QTD_MAX_XFER_LENGTH 0x5000
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172 #define FRAMELIST_ALIGNMENT 4096 /* Frame List Alignment */
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173 //#define LINK_TERMINATE 0x01
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174 #define SPLIT_MAX_LEN_UFRAME 188
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176 /*=======================================================================*/
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177 /* E H C I S T R U C T U R E S */
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178 /*=======================================================================*/
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180 /* Memory for EHCI Structures, docs for more information */
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182 typedef union un_EHCD_Link {
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185 uint32_t Terminate : 1;
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191 typedef struct st_EHCD_QTD {
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192 /*---------- Word 1 ----------*/
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195 /*---------- Word 2 ----------*/
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196 /*-- Take advantage of this to store HCD information --*/
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198 uint32_t AlterNextQtd;
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200 uint32_t Terminate : 1;
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203 // === TODO: used reserved space, need to move to other place ===
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205 uint32_t inUse : 1;
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211 /*---------- Word 3 ----------*/
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213 __IO uint32_t PingState_Err : 1;
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214 __IO uint32_t SplitXstate : 1;
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215 __IO uint32_t MissedUframe : 1;
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216 __IO uint32_t TransactionError : 1;
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217 __IO uint32_t Babble : 1;
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218 __IO uint32_t BufferError : 1;
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219 __IO uint32_t Halted : 1;
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220 __IO uint32_t Active : 1;
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222 uint32_t PIDCode : 2;
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223 __IO uint32_t ErrorCounter : 2;
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224 __IO uint32_t CurrentPage : 3;
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225 uint32_t IntOnComplete : 1;
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226 __IO uint32_t TotalBytesToTransfer : 15;
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227 __IO uint32_t DataToggle : 1;
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228 uint32_t : 0;/* Force next member on next storage unit */
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229 /*---------- End Word 3 ----------*/
\r
231 /*---------- Buffer Pointer Word 4-7 ----------*/
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232 uint32_t BufferPointer[5];
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233 } HCD_QTD, *PHCD_QTD; // TODO: because QTD is used to declare overlay in HCD_QHD, we cannot put aligned 32 here ATTR_ALIGNED(32)
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235 typedef struct st_EHCD_QHD {
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236 /*---------- Word 1 ----------*/
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237 NextLinkPointer Horizontal;
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239 /*---------- Word 2 ----------*/
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240 uint32_t DeviceAddress : 7;
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241 uint32_t InActiveOnNextTransaction : 1;
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242 uint32_t EndpointNumber : 4;
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243 uint32_t EndpointSpeed : 2;
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244 uint32_t DataToggleControl : 1;
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245 uint32_t HeadReclamationFlag : 1;
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246 uint32_t MaxPackageSize : 11;
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247 uint32_t ControlEndpointFlag : 1;
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248 uint32_t NakCountReload : 4;
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249 uint32_t : 0;/* Force next member on next storage unit */
\r
250 /*---------- End Word 2 ----------*/
\r
252 /*---------- Word 3 ----------*/
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253 uint32_t uFrameSMask : 8;
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254 uint32_t uFrameCMask : 8;
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255 uint32_t HubAddress : 7;
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256 uint32_t PortNumber : 7;
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258 uint32_t : 0;/* Force next member on next storage unit */
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259 /*---------- End Word 3 ----------*/
\r
261 /*---------- Word 4 ----------*/
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262 __IO uint32_t CurrentQtd;
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264 /*---------- Overlay Area ----------*/
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265 __IO HCD_QTD Overlay;
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267 /*---------- HCD Area : 16 Bytes----------*/
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268 uint32_t inUse : 1;
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269 uint32_t Direction : 2;
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270 uint32_t Interval : 5;
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271 uint32_t ListIndex : 20;/* not support full period list */
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272 uint32_t : 0;/* Force next member on next storage unit */
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274 __IO uint32_t status; // TODO will remove __IO after remove all HcdQHD function
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275 uint32_t FirstQtd; /* used as TD head to clean up TD chain when transfer done */
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276 uint16_t *pActualTransferCount; /* total transferred bytes of a usb request */
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277 } ATTR_ALIGNED (32) HCD_QHD, *PHCD_QHD;
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279 typedef struct st_EHCD_ITD {
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280 /*---------- Word 1 ----------*/
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281 NextLinkPointer Horizontal;
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283 /*---------- Word 2-9 ----------*/
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285 __IO uint32_t Offset : 12;
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286 __IO uint32_t PageSelect : 3;
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287 uint32_t IntOnComplete : 1;
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288 __IO uint32_t Length : 12;
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289 /*-- status [31:28] --*/
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290 __IO uint32_t Error : 1;
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291 __IO uint32_t Babble : 1;
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292 __IO uint32_t BufferError : 1;
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293 __IO uint32_t Active : 1;
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296 /*---------- Word 10-16 ----------*/
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297 uint32_t BufferPointer[7];
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299 // FIXME: refractor to save memory HCD Area
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300 /*---------- HCD Area ----------*/
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303 uint32_t reserved[6];
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304 } ATTR_ALIGNED (32) HCD_HS_ITD, *PHCD_HS_ITD;
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306 typedef struct st_EHCD_SITD {
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307 NextLinkPointer Horizontal;
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309 /*---------- Word 2: static endpoint ----------*/
\r
310 uint32_t DeviceAddress : 7;
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312 uint32_t EndpointNumber : 4;
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314 uint32_t HubAddress : 7;
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316 uint32_t PortNumber : 7;
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317 uint32_t Direction : 1;
\r
318 uint32_t : 0;/* Force next member on next storage unit */
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319 /*---------- End Word 2 ----------*/
\r
321 /*---------- Word 3: Slipt Mask ----------*/
\r
322 uint8_t uFrameSMask;
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323 uint8_t uFrameCMask;
\r
324 uint16_t reserved; /* Force next member on next storage unit */
\r
325 /*---------- End Word 3 ----------*/
\r
327 /*---------- Word 4: ----------*/
\r
330 __IO uint32_t SplitXstate : 1;
\r
331 __IO uint32_t MissedUframe : 1;
\r
332 __IO uint32_t TransactionError : 1;
\r
333 __IO uint32_t Babble : 1;
\r
334 __IO uint32_t BufferError : 1;
\r
335 __IO uint32_t ERR : 1;
\r
336 __IO uint32_t Active : 1;
\r
338 __IO uint32_t uFrameCProgMask : 8;
\r
339 __IO uint32_t TotalBytesToTransfer : 10;
\r
341 __IO uint32_t PageSelect : 1;
\r
342 uint32_t IntOnComplete : 1;
\r
344 /*---------- End Word 4 ----------*/
\r
346 /*---------- Word 5-6 ----------*/
\r
347 uint32_t BufferPointer[2]; /*-- in BufferPointer[1] TP: Transaction Position - T-Count: Transaction Count --*/
\r
350 // uint32_t BufferPointer1;
\r
352 // __IO uint32_t TCount : 3;
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353 // __IO uint32_t TPosition : 2;
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357 /*---------- Word 7 ----------*/
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358 uint32_t BackPointer;
\r
360 /*-- HCD ARERA 4 bytes --*/
\r
363 uint8_t reserved2[2];
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364 } ATTR_ALIGNED (32) HCD_SITD, *PHCD_SITD;
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366 typedef struct st_EHCI_HOST_DATA {
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367 HCD_HS_ITD iTDs[HCD_MAX_HS_ITD]; /* Iso Transfer Descriptor */
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368 HCD_QHD AsyncHeadQhd; /* Serve as H-Queue Head in Async Schedule */
\r
369 HCD_QHD IntHeadQhd; /* Serve as Static 1ms Interrupt Heads */
\r
370 HCD_QHD qHDs[HCD_MAX_QHD]; /* Queue Head */
\r
371 HCD_QTD qTDs[HCD_MAX_QTD]; /* Queue Transfer Descriptor (Queue Element) */
\r
372 HCD_SITD siTDs[HCD_MAX_SITD]; /* Split Iso Transfer Descriptor */
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373 } EHCI_HOST_DATA_T;
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382 typedef struct st_PipeHandle {
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385 uint8_t PortNumber;
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389 typedef struct st_PipeStreamHandle {
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390 uint32_t BufferAddress;
\r
391 uint32_t RemainBytes;
\r
392 uint16_t PacketSize;
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393 uint8_t DataToggle;
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394 } Pipe_Stream_Handle_T;
\r
396 /*=======================================================================*/
\r
397 /* LOCAL S Y M B O L D E C L A R A T I O N S */
\r
398 /*=======================================================================*/
\r
399 extern EHCI_HOST_DATA_T ehci_data[MAX_USB_CORE];
\r
400 // extern EHCI_HOST_DATA_T ehci_data;
\r
401 extern NextLinkPointer PeriodFrameList0[FRAME_LIST_SIZE]; /* Period Frame List */
\r
402 extern NextLinkPointer PeriodFrameList1[FRAME_LIST_SIZE]; /* Period Frame List */
\r
403 #define EHCI_FRAME_LIST(HostID) ((HostID) ? PeriodFrameList1 : PeriodFrameList0 )
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405 /*=======================================================================*/
\r
406 /* G L O B A L S Y M B O L D E C L A R A T I O N S */
\r
407 /*=======================================================================*/
\r
408 void USB_Host_Enumerate (uint8_t HostID);
\r
410 void USB_Host_DeEnumerate(uint8_t HostID);
\r
412 /*=======================================================================*/
\r
413 /* L O C A L F U N C T I O N P R O T O T Y P E S */
\r
414 /*=======================================================================*/
\r
415 /********************************* HOST API *********************************/
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416 static INLINE HCD_STATUS EHciHostInit(uint8_t HostID);
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418 static INLINE HCD_STATUS EHciHostRun(uint8_t HostID);
\r
420 static INLINE HCD_STATUS EHciHostStop(uint8_t HostID);
\r
422 static INLINE HCD_STATUS EHciHostReset(uint8_t HostID);
\r
424 static void DisableAsyncSchedule(uint8_t HostID);
\r
426 static void EnableAsyncSchedule(uint8_t HostID);
\r
428 #if !defined(__ICCARM__)
\r
429 static void DisablePeriodSchedule(uint8_t HostID) __attribute__ ((unused)); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule
\r
431 static void EnablePeriodSchedule(uint8_t HostID) __attribute__ ((unused)); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule
\r
434 static void DisablePeriodSchedule(uint8_t HostID); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule
\r
436 static void EnablePeriodSchedule(uint8_t HostID); // TODO temporarily suppress unused warnnings for DisablePeriodSchedule & EnablePeriodSchedule
\r
439 static INLINE void DisableSchedule(uint8_t HostID, uint8_t isPeriod);
\r
441 static INLINE void EnableSchedule(uint8_t HostID, uint8_t isPeriod);
\r
443 /********************************* HELPER *********************************/
\r
444 static INLINE PHCD_QHD HcdAsyncHead(uint8_t HostID);
\r
446 static INLINE PHCD_QHD HcdIntHead(uint8_t HostID);
\r
448 static INLINE PHCD_QHD HcdQHD(uint8_t HostID, uint8_t idx);
\r
450 static INLINE PHCD_QTD HcdQTD(uint8_t HostID, uint8_t idx);
\r
452 static INLINE PHCD_HS_ITD HcdHsITD(uint8_t HostID, uint8_t idx);
\r
454 static INLINE PHCD_SITD HcdSITD(uint8_t HostID, uint8_t idx);
\r
456 static INLINE bool isValidLink(uint32_t link);
\r
458 static INLINE bool IsInterruptQhd (uint8_t HostID, uint8_t QhdIdx);
\r
460 /********************************* Queue Head & Queue TD *********************************/
\r
461 static void FreeQhd(uint8_t HostID, uint8_t QhdIdx);
\r
463 static HCD_STATUS AllocQhd(uint8_t HostID,
\r
464 uint8_t DeviceAddr,
\r
465 HCD_USB_SPEED DeviceSpeed,
\r
466 uint8_t EndpointNumber,
\r
467 HCD_TRANSFER_TYPE TransferType,
\r
468 HCD_TRANSFER_DIR TransferDir,
\r
469 uint16_t MaxPacketSize,
\r
472 uint8_t HSHubDevAddr,
\r
473 uint8_t HSHubPortNum,
\r
474 uint32_t *pQhdIdx);
\r
476 static HCD_STATUS InsertLinkPointer(NextLinkPointer *pList, NextLinkPointer *pNew, uint8_t type);
\r
478 static HCD_STATUS RemoveQueueHead(uint8_t HostID, uint8_t QhdIdx);
\r
480 static void FreeQtd(PHCD_QTD pQtd);
\r
482 static HCD_STATUS AllocQTD (uint8_t HostID,
\r
484 uint8_t *const BufferPointer,
\r
486 HCD_TRANSFER_DIR PIDCode,
\r
487 uint8_t DataToggle,
\r
490 static HCD_STATUS QueueQTDs (uint8_t HostID,
\r
494 HCD_TRANSFER_DIR PIDCode,
\r
495 uint8_t DataToggle);
\r
497 /********************************* ISO Head & ISO TD & Split ISO *********************************/
\r
498 static void FreeHsItd(PHCD_HS_ITD pItd);
\r
500 static HCD_STATUS AllocHsItd(uint8_t HostID,
\r
505 uint8_t XactPerITD,
\r
506 uint8_t IntOnComplete);
\r
508 static HCD_STATUS QueueITDs(uint8_t HostID, uint8_t IhdIdx, uint8_t *dataBuff, uint32_t xferLen);
\r
510 static void FreeSItd(PHCD_SITD pSItd);
\r
512 static HCD_STATUS AllocSItd(uint8_t HostID,
\r
517 uint8_t IntOnComplete);
\r
519 static HCD_STATUS QueueSITDs(uint8_t HostID, uint8_t HeadIdx, uint8_t *dataBuff, uint32_t xferLen);
\r
521 /********************************* Transfer Routines *********************************/
\r
522 static HCD_STATUS WaitForTransferComplete(uint8_t HostID, uint8_t EpIdx);
\r
524 static HCD_STATUS PipehandleParse(uint32_t Pipehandle, uint8_t *pHostID, HCD_TRANSFER_TYPE *XferType, uint8_t *pIdx);
\r
526 static void PipehandleCreate(uint32_t *pPipeHandle, uint8_t HostID, HCD_TRANSFER_TYPE XferType, uint8_t idx);
\r
528 /********************************* Interrupt Service Routines *********************************/
\r
529 static void AsyncScheduleIsr(uint8_t HostID);
\r
531 static void PeriodScheduleIsr(uint8_t HostID);
\r
533 static HCD_STATUS PortStatusChangeIsr(uint8_t HostID, uint32_t deviceConnect);
\r
535 static void AsyncAdvanceIsr(uint8_t HostID);
\r
537 static void UsbErrorIsr(uint8_t HostID);
\r
projects / freertos / blob