2 ******************************************************************************
\r
3 * @file stm32f7xx_hal_eth.c
\r
4 * @author MCD Application Team
\r
7 * @brief ETH HAL module driver.
\r
8 * This file provides firmware functions to manage the following
\r
9 * functionalities of the Ethernet (ETH) peripheral:
\r
10 * + Initialization and de-initialization functions
\r
11 * + IO operation functions
\r
12 * + Peripheral Control functions
\r
13 * + Peripheral State and Errors functions
\r
16 ==============================================================================
\r
17 ##### How to use this driver #####
\r
18 ==============================================================================
\r
20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
\r
21 ETH_HandleTypeDef heth;
\r
23 (#)Fill parameters of Init structure in heth handle
\r
25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
\r
27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
\r
28 (##) Enable the Ethernet interface clock using
\r
29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
\r
30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
\r
31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
\r
33 (##) Initialize the related GPIO clocks
\r
34 (##) Configure Ethernet pin-out
\r
35 (##) Configure Ethernet NVIC interrupt (IT mode)
\r
37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
\r
38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
\r
39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
\r
41 (#)Enable MAC and DMA transmission and reception:
\r
42 (##) HAL_ETH_Start();
\r
44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
\r
45 the frame to MAC TX FIFO:
\r
46 (##) HAL_ETH_TransmitFrame();
\r
48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
\r
50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
\r
52 (#) Get a received frame when an ETH RX interrupt occurs:
\r
53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
\r
55 (#) Communicate with external PHY device:
\r
56 (##) Read a specific register from the PHY
\r
57 HAL_ETH_ReadPHYRegister();
\r
58 (##) Write data to a specific RHY register:
\r
59 HAL_ETH_WritePHYRegister();
\r
61 (#) Configure the Ethernet MAC after ETH peripheral initialization
\r
62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
\r
64 (#) Configure the Ethernet DMA after ETH peripheral initialization
\r
65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
\r
67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
\r
71 ******************************************************************************
\r
74 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
\r
76 * Redistribution and use in source and binary forms, with or without modification,
\r
77 * are permitted provided that the following conditions are met:
\r
78 * 1. Redistributions of source code must retain the above copyright notice,
\r
79 * this list of conditions and the following disclaimer.
\r
80 * 2. Redistributions in binary form must reproduce the above copyright notice,
\r
81 * this list of conditions and the following disclaimer in the documentation
\r
82 * and/or other materials provided with the distribution.
\r
83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
\r
84 * may be used to endorse or promote products derived from this software
\r
85 * without specific prior written permission.
\r
87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
\r
88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
\r
89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
\r
90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
\r
91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
\r
92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
\r
93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
\r
94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
\r
95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
\r
96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\r
98 ******************************************************************************
\r
101 /* Includes ------------------------------------------------------------------*/
\r
102 #include "stm32f7xx_hal.h"
\r
105 int lUDPLoggingPrintf( const char *pcFormatString, ... );
\r
107 /** @addtogroup STM32F4xx_HAL_Driver
\r
111 /** @defgroup ETH ETH
\r
112 * @brief ETH HAL module driver
\r
116 #if !defined( ARRAY_SIZE )
\r
117 #define ARRAY_SIZE( x ) ( sizeof ( x ) / sizeof ( x )[ 0 ] )
\r
120 #ifdef HAL_ETH_MODULE_ENABLED
\r
122 #if defined(STM32F7xx)
\r
124 /* Private typedef -----------------------------------------------------------*/
\r
125 /* Private define ------------------------------------------------------------*/
\r
126 /** @defgroup ETH_Private_Constants ETH Private Constants
\r
129 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
\r
130 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
\r
135 /* Private macro -------------------------------------------------------------*/
\r
136 /* Private variables ---------------------------------------------------------*/
\r
137 /* Private function prototypes -----------------------------------------------*/
\r
138 /** @defgroup ETH_Private_Functions ETH Private Functions
\r
141 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
\r
142 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
\r
143 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
\r
144 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
\r
145 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
\r
146 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
\r
147 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
\r
148 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
\r
149 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
\r
150 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
\r
151 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
\r
156 /* Private functions ---------------------------------------------------------*/
\r
158 /** @defgroup ETH_Exported_Functions ETH Exported Functions
\r
162 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
\r
163 * @brief Initialization and Configuration functions
\r
166 ===============================================================================
\r
167 ##### Initialization and de-initialization functions #####
\r
168 ===============================================================================
\r
169 [..] This section provides functions allowing to:
\r
170 (+) Initialize and configure the Ethernet peripheral
\r
171 (+) De-initialize the Ethernet peripheral
\r
176 extern void vMACBProbePhy ( void );
\r
179 * @brief Initializes the Ethernet MAC and DMA according to default
\r
181 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
182 * the configuration information for ETHERNET module
\r
183 * @retval HAL status
\r
185 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
\r
187 uint32_t tmpreg = 0;
\r
188 uint32_t hclk = 60000000;
\r
189 uint32_t err = ETH_SUCCESS;
\r
191 /* Check the ETH peripheral state */
\r
197 /* Check parameters */
\r
198 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
\r
199 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
\r
200 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
\r
201 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
\r
203 if( heth->State == HAL_ETH_STATE_RESET )
\r
205 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
\r
206 HAL_ETH_MspInit( heth );
\r
209 /* Enable SYSCFG Clock */
\r
210 __HAL_RCC_SYSCFG_CLK_ENABLE();
\r
212 /* Select MII or RMII Mode*/
\r
213 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
\r
214 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
\r
216 /* Ethernet Software reset */
\r
217 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
\r
218 /* After reset all the registers holds their respective reset values */
\r
219 /* Also enable EDFE: Enhanced descriptor format enable. */
\r
220 // heth->Instance->DMABMR |= ETH_DMABMR_SR | ETH_DMABMR_EDE;
\r
221 heth->Instance->DMABMR |= ETH_DMABMR_SR;
\r
223 /* Wait for software reset */
\r
224 while ((heth->Instance->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
\r
228 /*-------------------------------- MAC Initialization ----------------------*/
\r
229 /* Get the ETHERNET MACMIIAR value */
\r
230 tmpreg = heth->Instance->MACMIIAR;
\r
231 /* Clear CSR Clock Range CR[2:0] bits */
\r
232 tmpreg &= ETH_MACMIIAR_CR_MASK;
\r
234 /* Get hclk frequency value (168,000,000) */
\r
235 hclk = HAL_RCC_GetHCLKFreq();
\r
237 /* Set CR bits depending on hclk value */
\r
238 if( ( hclk >= 20000000 ) && ( hclk < 35000000 ) )
\r
240 /* CSR Clock Range between 20-35 MHz */
\r
241 tmpreg |= (uint32_t) ETH_MACMIIAR_CR_Div16;
\r
243 else if( ( hclk >= 35000000 ) && ( hclk < 60000000 ) )
\r
245 /* CSR Clock Range between 35-60 MHz */
\r
246 tmpreg |= ( uint32_t ) ETH_MACMIIAR_CR_Div26;
\r
248 else if((hclk >= 60000000 ) && ( hclk < 100000000 ) )
\r
250 /* CSR Clock Range between 60-100 MHz */
\r
251 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
\r
253 else if((hclk >= 100000000 ) && ( hclk < 150000000))
\r
255 /* CSR Clock Range between 100-150 MHz */
\r
256 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
\r
258 else /* ((hclk >= 150000000 ) && ( hclk <= 168000000)) */
\r
260 /* CSR Clock Range between 150-168 MHz */
\r
261 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
\r
264 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
\r
265 heth->Instance->MACMIIAR = (uint32_t)tmpreg;
\r
267 /* Initialise the MACB and set all PHY properties */
\r
270 /* Config MAC and DMA */
\r
271 ETH_MACDMAConfig(heth, err);
\r
273 /* Set ETH HAL State to Ready */
\r
274 heth->State= HAL_ETH_STATE_READY;
\r
276 /* Return function status */
\r
281 * @brief De-Initializes the ETH peripheral.
\r
282 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
283 * the configuration information for ETHERNET module
\r
284 * @retval HAL status
\r
286 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
\r
288 /* Set the ETH peripheral state to BUSY */
\r
289 heth->State = HAL_ETH_STATE_BUSY;
\r
291 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
\r
292 HAL_ETH_MspDeInit( heth );
\r
294 /* Set ETH HAL state to Disabled */
\r
295 heth->State= HAL_ETH_STATE_RESET;
\r
298 __HAL_UNLOCK( heth );
\r
300 /* Return function status */
\r
305 * @brief Initializes the DMA Tx descriptors in chain mode.
\r
306 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
307 * the configuration information for ETHERNET module
\r
308 * @param DMATxDescTab: Pointer to the first Tx desc list
\r
309 * @param TxBuff: Pointer to the first TxBuffer list
\r
310 * @param TxBuffCount: Number of the used Tx desc in the list
\r
311 * @retval HAL status
\r
313 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)
\r
316 ETH_DMADescTypeDef *pxDMADescriptor;
\r
318 /* Process Locked */
\r
319 __HAL_LOCK( heth );
\r
321 /* Set the ETH peripheral state to BUSY */
\r
322 heth->State = HAL_ETH_STATE_BUSY;
\r
324 /* Set the TxDesc pointer with the first one of the pxDMATable list */
\r
325 heth->TxDesc = pxDMATable;
\r
327 /* Fill each DMA descriptor with the right values */
\r
328 for( i=0; i < ulBufferCount; i++ )
\r
330 /* Get the pointer on the ith member of the descriptor list */
\r
331 pxDMADescriptor = pxDMATable + i;
\r
333 /* Set Second Address Chained bit */
\r
334 pxDMADescriptor->Status = ETH_DMATXDESC_TCH;
\r
336 pxDMADescriptor->ControlBufferSize = 0;
\r
338 /* Set Buffer1 address pointer */
\r
339 if( ucDataBuffer != NULL )
\r
341 pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_TX_BUF_SIZE ] );
\r
345 /* Buffer space is not provided because it uses zero-copy transmissions. */
\r
346 pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;
\r
349 if (heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
\r
351 /* Set the DMA Tx descriptors checksum insertion for TCP, UDP, and ICMP */
\r
352 pxDMADescriptor->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
\r
355 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
\r
356 if(i < ( ulBufferCount - 1 ) )
\r
358 /* Set next descriptor address register with next descriptor base address */
\r
359 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) ( pxDMATable + i + 1 );
\r
363 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
\r
364 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;
\r
368 /* Set Transmit Descriptor List Address Register */
\r
369 heth->Instance->DMATDLAR = ( uint32_t ) pxDMATable;
\r
371 /* Set ETH HAL State to Ready */
\r
372 heth->State= HAL_ETH_STATE_READY;
\r
374 /* Process Unlocked */
\r
375 __HAL_UNLOCK( heth );
\r
377 /* Return function status */
\r
382 * @brief Initializes the DMA Rx descriptors in chain mode.
\r
383 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
384 * the configuration information for ETHERNET module
\r
385 * @param DMARxDescTab: Pointer to the first Rx desc list
\r
386 * @param RxBuff: Pointer to the first RxBuffer list
\r
387 * @param RxBuffCount: Number of the used Rx desc in the list
\r
388 * @retval HAL status
\r
390 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *pxDMATable, uint8_t *ucDataBuffer, uint32_t ulBufferCount)
\r
393 ETH_DMADescTypeDef *pxDMADescriptor;
\r
395 /* Process Locked */
\r
396 __HAL_LOCK( heth );
\r
398 /* Set the ETH peripheral state to BUSY */
\r
399 heth->State = HAL_ETH_STATE_BUSY;
\r
401 /* Set the RxDesc pointer with the first one of the pxDMATable list */
\r
402 heth->RxDesc = pxDMATable;
\r
404 /* Fill each DMA descriptor with the right values */
\r
405 for(i=0; i < ulBufferCount; i++)
\r
407 /* Get the pointer on the ith member of the descriptor list */
\r
408 pxDMADescriptor = pxDMATable+i;
\r
410 /* Set Own bit of the Rx descriptor Status */
\r
411 pxDMADescriptor->Status = ETH_DMARXDESC_OWN;
\r
413 /* Set Buffer1 size and Second Address Chained bit */
\r
414 pxDMADescriptor->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
\r
416 /* Set Buffer1 address pointer */
\r
417 if( ucDataBuffer != NULL )
\r
419 pxDMADescriptor->Buffer1Addr = ( uint32_t )( &ucDataBuffer[ i * ETH_RX_BUF_SIZE ] );
\r
423 /* Buffer space is not provided because it uses zero-copy reception. */
\r
424 pxDMADescriptor->Buffer1Addr = ( uint32_t )0u;
\r
427 if( heth->Init.RxMode == ETH_RXINTERRUPT_MODE )
\r
429 /* Enable Ethernet DMA Rx Descriptor interrupt */
\r
430 pxDMADescriptor->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
\r
433 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
\r
434 if(i < (ulBufferCount-1))
\r
436 /* Set next descriptor address register with next descriptor base address */
\r
437 pxDMADescriptor->Buffer2NextDescAddr = (uint32_t)(pxDMATable+i+1);
\r
441 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
\r
442 pxDMADescriptor->Buffer2NextDescAddr = ( uint32_t ) pxDMATable;
\r
446 /* Set Receive Descriptor List Address Register */
\r
447 heth->Instance->DMARDLAR = ( uint32_t ) pxDMATable;
\r
449 /* Set ETH HAL State to Ready */
\r
450 heth->State= HAL_ETH_STATE_READY;
\r
452 /* Process Unlocked */
\r
453 __HAL_UNLOCK( heth );
\r
455 /* Return function status */
\r
460 * @brief Initializes the ETH MSP.
\r
461 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
462 * the configuration information for ETHERNET module
\r
465 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
\r
467 /* NOTE : This function Should not be modified, when the callback is needed,
\r
468 the HAL_ETH_MspInit could be implemented in the user file
\r
473 * @brief DeInitializes ETH MSP.
\r
474 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
475 * the configuration information for ETHERNET module
\r
478 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
\r
480 /* NOTE : This function Should not be modified, when the callback is needed,
\r
481 the HAL_ETH_MspDeInit could be implemented in the user file
\r
489 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
\r
490 * @brief Data transfers functions
\r
493 ==============================================================================
\r
494 ##### IO operation functions #####
\r
495 ==============================================================================
\r
496 [..] This section provides functions allowing to:
\r
497 (+) Transmit a frame
\r
498 HAL_ETH_TransmitFrame();
\r
499 (+) Receive a frame
\r
500 HAL_ETH_GetReceivedFrame();
\r
501 HAL_ETH_GetReceivedFrame_IT();
\r
502 (+) Read from an External PHY register
\r
503 HAL_ETH_ReadPHYRegister();
\r
504 (+) Write to an External PHY register
\r
505 HAL_ETH_WritePHYRegister();
\r
513 * @brief Sends an Ethernet frame.
\r
514 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
515 * the configuration information for ETHERNET module
\r
516 * @param FrameLength: Amount of data to be sent
\r
517 * @retval HAL status
\r
519 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
\r
521 uint32_t bufcount = 0, size = 0, i = 0;
\r
522 __IO ETH_DMADescTypeDef *pxDmaTxDesc = heth->TxDesc;
\r
523 /* Process Locked */
\r
524 __HAL_LOCK( heth );
\r
526 /* Set the ETH peripheral state to BUSY */
\r
527 heth->State = HAL_ETH_STATE_BUSY;
\r
529 if( FrameLength == 0 )
\r
531 /* Set ETH HAL state to READY */
\r
532 heth->State = HAL_ETH_STATE_READY;
\r
534 /* Process Unlocked */
\r
535 __HAL_UNLOCK( heth );
\r
540 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
\r
541 if( ( pxDmaTxDesc->Status & ETH_DMATXDESC_OWN ) != ( uint32_t ) RESET )
\r
544 heth->State = HAL_ETH_STATE_BUSY_TX;
\r
546 /* Process Unlocked */
\r
547 __HAL_UNLOCK( heth );
\r
552 /* Get the number of needed Tx buffers for the current frame, rounding up. */
\r
553 bufcount = ( FrameLength + ETH_TX_BUF_SIZE - 1 ) / ETH_TX_BUF_SIZE;
\r
557 /* Set LAST and FIRST segment */
\r
558 pxDmaTxDesc->Status |= ETH_DMATXDESC_FS | ETH_DMATXDESC_LS;
\r
559 /* Set frame size */
\r
560 pxDmaTxDesc->ControlBufferSize = ( FrameLength & ETH_DMATXDESC_TBS1 );
\r
561 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
562 pxDmaTxDesc->Status |= ETH_DMATXDESC_OWN;
\r
563 /* Point to next descriptor */
\r
564 heth->TxDesc = ( ETH_DMADescTypeDef * ) ( heth->TxDesc->Buffer2NextDescAddr );
\r
568 for( i = 0; i < bufcount; i++ )
\r
570 /* Clear FIRST and LAST segment bits */
\r
571 uint32_t ulStatus = heth->TxDesc->Status & ~( ETH_DMATXDESC_FS | ETH_DMATXDESC_LS );
\r
575 /* Setting the first segment bit */
\r
576 heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_FS;
\r
580 if (i < (bufcount-1))
\r
582 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
\r
586 /* Setting the last segment bit */
\r
587 heth->TxDesc->Status = ulStatus | ETH_DMATXDESC_LS;
\r
588 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
\r
589 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
\r
592 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
\r
593 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
\r
594 /* point to next descriptor */
\r
595 heth->TxDesc = (ETH_DMADescTypeDef *)( heth->TxDesc->Buffer2NextDescAddr );
\r
601 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
\r
602 if( ( heth->Instance->DMASR & ETH_DMASR_TBUS ) != ( uint32_t )RESET )
\r
604 heth->Instance->DMACHTDR = ( uint32_t )pxDmaTxDesc;
\r
606 /* Clear TBUS ETHERNET DMA flag */
\r
607 heth->Instance->DMASR = ETH_DMASR_TBUS;
\r
608 /* Resume DMA transmission*/
\r
609 heth->Instance->DMATPDR = 0;
\r
612 /* Set ETH HAL State to Ready */
\r
613 heth->State = HAL_ETH_STATE_READY;
\r
615 /* Process Unlocked */
\r
616 __HAL_UNLOCK( heth );
\r
618 /* Return function status */
\r
623 * @brief Checks for received frames.
\r
624 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
625 * the configuration information for ETHERNET module
\r
626 * @retval HAL status
\r
628 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT( ETH_HandleTypeDef *heth )
\r
630 return HAL_ETH_GetReceivedFrame( heth );
\r
633 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame( ETH_HandleTypeDef *heth )
\r
635 uint32_t ulCounter = 0;
\r
636 ETH_DMADescTypeDef *pxDescriptor = heth->RxDesc;
\r
637 HAL_StatusTypeDef xResult = HAL_ERROR;
\r
639 /* Process Locked */
\r
640 __HAL_LOCK( heth );
\r
642 /* Check the ETH state to BUSY */
\r
643 heth->State = HAL_ETH_STATE_BUSY;
\r
645 /* Scan descriptors owned by CPU */
\r
646 while( ( ( pxDescriptor->Status & ETH_DMARXDESC_OWN ) == 0ul ) && ( ulCounter < ETH_RXBUFNB ) )
\r
648 uint32_t ulStatus = pxDescriptor->Status;
\r
650 /* Just for security. */
\r
653 if( ( ulStatus & ( ETH_DMARXDESC_FS | ETH_DMARXDESC_LS ) ) == ( uint32_t )ETH_DMARXDESC_FS )
\r
655 /* First segment in frame, but not the last. */
\r
656 heth->RxFrameInfos.FSRxDesc = pxDescriptor;
\r
657 heth->RxFrameInfos.LSRxDesc = ( ETH_DMADescTypeDef *)NULL;
\r
658 heth->RxFrameInfos.SegCount = 1;
\r
659 /* Point to next descriptor. */
\r
660 pxDescriptor = (ETH_DMADescTypeDef*) (pxDescriptor->Buffer2NextDescAddr);
\r
661 heth->RxDesc = pxDescriptor;
\r
663 else if( ( ulStatus & ( ETH_DMARXDESC_LS | ETH_DMARXDESC_FS ) ) == 0ul )
\r
665 /* This is an intermediate segment, not first, not last. */
\r
666 /* Increment segment count. */
\r
667 heth->RxFrameInfos.SegCount++;
\r
668 /* Move to the next descriptor. */
\r
669 pxDescriptor = ( ETH_DMADescTypeDef * ) ( pxDescriptor->Buffer2NextDescAddr );
\r
670 heth->RxDesc = pxDescriptor;
\r
672 /* Must be a last segment */
\r
675 /* This is the last segment. */
\r
676 /* Check if last segment is first segment: one segment contains the frame */
\r
677 if( heth->RxFrameInfos.SegCount == 0 )
\r
679 /* Remember the first segment. */
\r
680 heth->RxFrameInfos.FSRxDesc = pxDescriptor;
\r
683 /* Increment segment count */
\r
684 heth->RxFrameInfos.SegCount++;
\r
686 /* Remember the last segment. */
\r
687 heth->RxFrameInfos.LSRxDesc = pxDescriptor;
\r
689 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
\r
690 heth->RxFrameInfos.length =
\r
691 ( ( ulStatus & ETH_DMARXDESC_FL ) >> ETH_DMARXDESC_FRAMELENGTHSHIFT ) - 4;
\r
693 /* Get the address of the buffer start address */
\r
694 heth->RxFrameInfos.buffer = heth->RxFrameInfos.FSRxDesc->Buffer1Addr;
\r
696 /* Point to next descriptor */
\r
697 heth->RxDesc = ( ETH_DMADescTypeDef * ) pxDescriptor->Buffer2NextDescAddr;
\r
699 /* Return OK status: a packet was received. */
\r
705 /* Set ETH HAL State to Ready */
\r
706 heth->State = HAL_ETH_STATE_READY;
\r
708 /* Process Unlocked */
\r
709 __HAL_UNLOCK( heth );
\r
711 /* Return function status */
\r
715 #if( STM32_ETHERNET_STATS != 0 )
\r
717 volatile int rx_count, tx_count, int_count;
\r
719 * @brief This function handles ETH interrupt request.
\r
720 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
721 * the configuration information for ETHERNET module
\r
722 * @retval HAL status
\r
724 volatile int int_counts[32];
\r
725 volatile int tx_status[8];
\r
726 volatile unsigned sr_history[32];
\r
727 volatile int sr_head;
\r
728 #define STM32_STAT_INC( x ) do { ( x )++; } while( 0 )
\r
731 #define STM32_STAT_INC( x ) do { } while( 0 )
\r
732 #endif /* STM32_ETHERNET_STATS */
\r
734 #define ETH_DMA_ALL_INTS \
\r
735 ( ETH_DMA_IT_TST | ETH_DMA_IT_PMT | ETH_DMA_IT_MMC | ETH_DMA_IT_NIS | ETH_DMA_IT_AIS | ETH_DMA_IT_ER | \
\r
736 ETH_DMA_IT_FBE | ETH_DMA_IT_ET | ETH_DMA_IT_RWT | ETH_DMA_IT_RPS | ETH_DMA_IT_RBU | ETH_DMA_IT_R | \
\r
737 ETH_DMA_IT_TU | ETH_DMA_IT_RO | ETH_DMA_IT_TJT | ETH_DMA_IT_TPS | ETH_DMA_IT_T )
\r
739 //#define ETH_DMA_ALL_INTS ETH_DMA_IT_RBU | ETH_DMA_FLAG_T | ETH_DMA_FLAG_AIS
\r
741 #define INT_MASK ( ( uint32_t ) ~ ( ETH_DMA_IT_TBU ) )
\r
742 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
\r
746 STM32_STAT_INC( int_count );
\r
748 dmasr = heth->Instance->DMASR & ETH_DMA_ALL_INTS;
\r
749 heth->Instance->DMASR = dmasr;
\r
751 #if( STM32_ETHERNET_STATS != 0 )
\r
752 if( sr_head < ARRAY_SIZE( sr_history ) )
\r
754 sr_history[ sr_head++ ] = dmasr;
\r
759 for (i = 0; i < 32; i++) {
\r
760 if (dmasr & (1u << i)) {
\r
764 tx_status[ ( dmasr >> 20 ) & 0x07 ]++;
\r
768 /* Frame received */
\r
769 if( ( dmasr & ( ETH_DMA_FLAG_R | ETH_DMA_IT_RBU ) ) != 0 )
\r
771 /* Receive complete callback */
\r
772 HAL_ETH_RxCpltCallback( heth );
\r
773 STM32_STAT_INC( rx_count );
\r
775 /* Frame transmitted */
\r
776 if( ( dmasr & ( ETH_DMA_FLAG_T ) ) != 0 )
\r
778 /* Transfer complete callback */
\r
779 HAL_ETH_TxCpltCallback( heth );
\r
780 STM32_STAT_INC( tx_count );
\r
783 /* ETH DMA Error */
\r
784 if( ( dmasr & ( ETH_DMA_FLAG_AIS ) ) != 0 )
\r
786 /* Ethernet Error callback */
\r
787 HAL_ETH_ErrorCallback( heth );
\r
792 * @brief Tx Transfer completed callbacks.
\r
793 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
794 * the configuration information for ETHERNET module
\r
797 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
\r
799 /* NOTE : This function Should not be modified, when the callback is needed,
\r
800 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
805 * @brief Rx Transfer completed callbacks.
\r
806 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
807 * the configuration information for ETHERNET module
\r
810 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
\r
812 /* NOTE : This function Should not be modified, when the callback is needed,
\r
813 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
818 * @brief Ethernet transfer error callbacks
\r
819 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
820 * the configuration information for ETHERNET module
\r
823 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
\r
825 /* NOTE : This function Should not be modified, when the callback is needed,
\r
826 the HAL_ETH_TxCpltCallback could be implemented in the user file
\r
831 * @brief Reads a PHY register
\r
832 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
833 * the configuration information for ETHERNET module
\r
834 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
835 * This parameter can be one of the following values:
\r
836 * PHY_BCR: Transceiver Basic Control Register,
\r
837 * PHY_BSR: Transceiver Basic Status Register.
\r
838 * More PHY register could be read depending on the used PHY
\r
839 * @param RegValue: PHY register value
\r
840 * @retval HAL status
\r
842 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
\r
844 uint32_t tmpreg = 0;
\r
845 uint32_t tickstart = 0;
\r
846 HAL_StatusTypeDef xResult;
\r
848 /* Check parameters */
\r
849 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
\r
851 /* Check the ETH peripheral state */
\r
852 if( heth->State == HAL_ETH_STATE_BUSY_RD )
\r
854 xResult = HAL_BUSY;
\r
858 __HAL_LOCK( heth );
\r
860 /* Set ETH HAL State to BUSY_RD */
\r
861 heth->State = HAL_ETH_STATE_BUSY_RD;
\r
863 /* Get the ETHERNET MACMIIAR value */
\r
864 tmpreg = heth->Instance->MACMIIAR;
\r
866 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
867 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
869 /* Prepare the MII address register value */
\r
870 tmpreg |= ( ( ( uint32_t )heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
\r
871 tmpreg |= ( ( ( uint32_t )PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
\r
872 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
\r
873 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
875 /* Write the result value into the MII Address register */
\r
876 heth->Instance->MACMIIAR = tmpreg;
\r
879 tickstart = HAL_GetTick();
\r
881 /* Check for the Busy flag */
\r
884 tmpreg = heth->Instance->MACMIIAR;
\r
886 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )
\r
888 /* Get MACMIIDR value */
\r
889 *RegValue = ( uint32_t ) heth->Instance->MACMIIDR;
\r
893 /* Check for the Timeout */
\r
894 if( ( HAL_GetTick( ) - tickstart ) > PHY_READ_TO )
\r
896 xResult = HAL_TIMEOUT;
\r
902 /* Set ETH HAL State to READY */
\r
903 heth->State = HAL_ETH_STATE_READY;
\r
905 /* Process Unlocked */
\r
906 __HAL_UNLOCK( heth );
\r
909 if( xResult != HAL_OK )
\r
911 lUDPLoggingPrintf( "ReadPHY: %d\n", xResult );
\r
913 /* Return function status */
\r
918 * @brief Writes to a PHY register.
\r
919 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
920 * the configuration information for ETHERNET module
\r
921 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
\r
922 * This parameter can be one of the following values:
\r
923 * PHY_BCR: Transceiver Control Register.
\r
924 * More PHY register could be written depending on the used PHY
\r
925 * @param RegValue: the value to write
\r
926 * @retval HAL status
\r
928 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
\r
930 uint32_t tmpreg = 0;
\r
931 uint32_t tickstart = 0;
\r
932 HAL_StatusTypeDef xResult;
\r
934 /* Check parameters */
\r
935 assert_param( IS_ETH_PHY_ADDRESS( heth->Init.PhyAddress ) );
\r
937 /* Check the ETH peripheral state */
\r
938 if( heth->State == HAL_ETH_STATE_BUSY_WR )
\r
940 xResult = HAL_BUSY;
\r
944 __HAL_LOCK( heth );
\r
946 /* Set ETH HAL State to BUSY_WR */
\r
947 heth->State = HAL_ETH_STATE_BUSY_WR;
\r
949 /* Get the ETHERNET MACMIIAR value */
\r
950 tmpreg = heth->Instance->MACMIIAR;
\r
952 /* Keep only the CSR Clock Range CR[2:0] bits value */
\r
953 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
\r
955 /* Prepare the MII register address value */
\r
956 tmpreg |= ( ( ( uint32_t ) heth->Init.PhyAddress << 11 ) & ETH_MACMIIAR_PA ); /* Set the PHY device address */
\r
957 tmpreg |= ( ( ( uint32_t ) PHYReg << 6 ) & ETH_MACMIIAR_MR ); /* Set the PHY register address */
\r
958 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
\r
959 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
\r
961 /* Give the value to the MII data register */
\r
962 heth->Instance->MACMIIDR = ( uint16_t ) RegValue;
\r
964 /* Write the result value into the MII Address register */
\r
965 heth->Instance->MACMIIAR = tmpreg;
\r
968 tickstart = HAL_GetTick();
\r
970 /* Check for the Busy flag */
\r
973 tmpreg = heth->Instance->MACMIIAR;
\r
975 if( ( tmpreg & ETH_MACMIIAR_MB ) == 0ul )
\r
980 /* Check for the Timeout */
\r
981 if( ( HAL_GetTick( ) - tickstart ) > PHY_WRITE_TO )
\r
983 xResult = HAL_TIMEOUT;
\r
988 /* Set ETH HAL State to READY */
\r
989 heth->State = HAL_ETH_STATE_READY;
\r
990 /* Process Unlocked */
\r
991 __HAL_UNLOCK( heth );
\r
994 if( xResult != HAL_OK )
\r
996 lUDPLoggingPrintf( "WritePHY: %d\n", xResult );
\r
998 /* Return function status */
\r
1006 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
\r
1007 * @brief Peripheral Control functions
\r
1010 ===============================================================================
\r
1011 ##### Peripheral Control functions #####
\r
1012 ===============================================================================
\r
1013 [..] This section provides functions allowing to:
\r
1014 (+) Enable MAC and DMA transmission and reception.
\r
1016 (+) Disable MAC and DMA transmission and reception.
\r
1018 (+) Set the MAC configuration in runtime mode
\r
1019 HAL_ETH_ConfigMAC();
\r
1020 (+) Set the DMA configuration in runtime mode
\r
1021 HAL_ETH_ConfigDMA();
\r
1028 * @brief Enables Ethernet MAC and DMA reception/transmission
\r
1029 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1030 * the configuration information for ETHERNET module
\r
1031 * @retval HAL status
\r
1033 HAL_StatusTypeDef HAL_ETH_Start( ETH_HandleTypeDef *heth )
\r
1035 /* Process Locked */
\r
1036 __HAL_LOCK( heth );
\r
1038 /* Set the ETH peripheral state to BUSY */
\r
1039 heth->State = HAL_ETH_STATE_BUSY;
\r
1041 /* Enable transmit state machine of the MAC for transmission on the MII */
\r
1042 ETH_MACTransmissionEnable( heth );
\r
1044 /* Enable receive state machine of the MAC for reception from the MII */
\r
1045 ETH_MACReceptionEnable( heth );
\r
1047 /* Flush Transmit FIFO */
\r
1048 ETH_FlushTransmitFIFO( heth );
\r
1050 /* Start DMA transmission */
\r
1051 ETH_DMATransmissionEnable( heth );
\r
1053 /* Start DMA reception */
\r
1054 ETH_DMAReceptionEnable( heth );
\r
1056 /* Set the ETH state to READY*/
\r
1057 heth->State= HAL_ETH_STATE_READY;
\r
1059 /* Process Unlocked */
\r
1060 __HAL_UNLOCK( heth );
\r
1062 /* Return function status */
\r
1067 * @brief Stop Ethernet MAC and DMA reception/transmission
\r
1068 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1069 * the configuration information for ETHERNET module
\r
1070 * @retval HAL status
\r
1072 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
\r
1074 /* Process Locked */
\r
1075 __HAL_LOCK( heth );
\r
1077 /* Set the ETH peripheral state to BUSY */
\r
1078 heth->State = HAL_ETH_STATE_BUSY;
\r
1080 /* Stop DMA transmission */
\r
1081 ETH_DMATransmissionDisable( heth );
\r
1083 /* Stop DMA reception */
\r
1084 ETH_DMAReceptionDisable( heth );
\r
1086 /* Disable receive state machine of the MAC for reception from the MII */
\r
1087 ETH_MACReceptionDisable( heth );
\r
1089 /* Flush Transmit FIFO */
\r
1090 ETH_FlushTransmitFIFO( heth );
\r
1092 /* Disable transmit state machine of the MAC for transmission on the MII */
\r
1093 ETH_MACTransmissionDisable( heth );
\r
1095 /* Set the ETH state*/
\r
1096 heth->State = HAL_ETH_STATE_READY;
\r
1098 /* Process Unlocked */
\r
1099 __HAL_UNLOCK( heth );
\r
1101 /* Return function status */
\r
1105 static void prvWriteMACFCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1107 /* Enable the MAC transmission */
\r
1108 heth->Instance->MACFCR = ulValue;
\r
1110 /* Wait until the write operation will be taken into account:
\r
1111 at least four TX_CLK/RX_CLK clock cycles.
\r
1112 Read it back, wait a ms and */
\r
1113 ( void ) heth->Instance->MACFCR;
\r
1115 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1117 heth->Instance->MACFCR = ulValue;
\r
1120 static void prvWriteDMAOMR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1122 /* Enable the MAC transmission */
\r
1123 heth->Instance->DMAOMR = ulValue;
\r
1125 /* Wait until the write operation will be taken into account:
\r
1126 at least four TX_CLK/RX_CLK clock cycles.
\r
1127 Read it back, wait a ms and */
\r
1128 ( void ) heth->Instance->DMAOMR;
\r
1130 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1132 heth->Instance->DMAOMR = ulValue;
\r
1135 static void prvWriteMACCR( ETH_HandleTypeDef *heth, uint32_t ulValue)
\r
1137 /* Enable the MAC transmission */
\r
1138 heth->Instance->MACCR = ulValue;
\r
1140 /* Wait until the write operation will be taken into account:
\r
1141 at least four TX_CLK/RX_CLK clock cycles.
\r
1142 Read it back, wait a ms and */
\r
1143 ( void ) heth->Instance->MACCR;
\r
1145 HAL_Delay( ETH_REG_WRITE_DELAY );
\r
1147 heth->Instance->MACCR = ulValue;
\r
1151 * @brief Set ETH MAC Configuration.
\r
1152 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1153 * the configuration information for ETHERNET module
\r
1154 * @param macconf: MAC Configuration structure
\r
1155 * @retval HAL status
\r
1157 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
\r
1159 uint32_t tmpreg = 0;
\r
1161 /* Process Locked */
\r
1162 __HAL_LOCK( heth );
\r
1164 /* Set the ETH peripheral state to BUSY */
\r
1165 heth->State= HAL_ETH_STATE_BUSY;
\r
1167 assert_param(IS_ETH_SPEED(heth->Init.Speed));
\r
1168 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
\r
1170 if (macconf != NULL)
\r
1172 /* Check the parameters */
\r
1173 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
\r
1174 assert_param(IS_ETH_JABBER(macconf->Jabber));
\r
1175 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
\r
1176 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
\r
1177 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
\r
1178 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
\r
1179 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
\r
1180 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
\r
1181 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
\r
1182 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
\r
1183 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
\r
1184 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
\r
1185 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
\r
1186 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
\r
1187 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
\r
1188 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
\r
1189 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
\r
1190 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
\r
1191 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
\r
1192 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
\r
1193 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
\r
1194 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
\r
1195 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
\r
1196 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
\r
1197 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
\r
1198 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
\r
1199 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
\r
1201 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1202 /* Get the ETHERNET MACCR value */
\r
1203 tmpreg = heth->Instance->MACCR;
\r
1204 /* Clear WD, PCE, PS, TE and RE bits */
\r
1205 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1207 tmpreg |= (uint32_t)(
\r
1208 macconf->Watchdog |
\r
1210 macconf->InterFrameGap |
\r
1211 macconf->CarrierSense |
\r
1212 heth->Init.Speed |
\r
1213 macconf->ReceiveOwn |
\r
1214 macconf->LoopbackMode |
\r
1215 heth->Init.DuplexMode |
\r
1216 macconf->ChecksumOffload |
\r
1217 macconf->RetryTransmission |
\r
1218 macconf->AutomaticPadCRCStrip |
\r
1219 macconf->BackOffLimit |
\r
1220 macconf->DeferralCheck);
\r
1222 /* Write to ETHERNET MACCR */
\r
1223 prvWriteMACCR( heth, tmpreg );
\r
1225 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1226 /* Write to ETHERNET MACFFR */
\r
1227 heth->Instance->MACFFR = (uint32_t)(
\r
1228 macconf->ReceiveAll |
\r
1229 macconf->SourceAddrFilter |
\r
1230 macconf->PassControlFrames |
\r
1231 macconf->BroadcastFramesReception |
\r
1232 macconf->DestinationAddrFilter |
\r
1233 macconf->PromiscuousMode |
\r
1234 macconf->MulticastFramesFilter |
\r
1235 macconf->UnicastFramesFilter);
\r
1237 /* Wait until the write operation will be taken into account :
\r
1238 at least four TX_CLK/RX_CLK clock cycles */
\r
1239 tmpreg = heth->Instance->MACFFR;
\r
1240 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1241 heth->Instance->MACFFR = tmpreg;
\r
1243 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
\r
1244 /* Write to ETHERNET MACHTHR */
\r
1245 heth->Instance->MACHTHR = (uint32_t)macconf->HashTableHigh;
\r
1247 /* Write to ETHERNET MACHTLR */
\r
1248 heth->Instance->MACHTLR = (uint32_t)macconf->HashTableLow;
\r
1249 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
\r
1251 /* Get the ETHERNET MACFCR value */
\r
1252 tmpreg = heth->Instance->MACFCR;
\r
1253 /* Clear xx bits */
\r
1254 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1256 tmpreg |= (uint32_t)((
\r
1257 macconf->PauseTime << 16) |
\r
1258 macconf->ZeroQuantaPause |
\r
1259 macconf->PauseLowThreshold |
\r
1260 macconf->UnicastPauseFrameDetect |
\r
1261 macconf->ReceiveFlowControl |
\r
1262 macconf->TransmitFlowControl);
\r
1264 /* Write to ETHERNET MACFCR */
\r
1265 prvWriteMACFCR( heth, tmpreg );
\r
1267 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
\r
1268 heth->Instance->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
\r
1269 macconf->VLANTagIdentifier);
\r
1271 /* Wait until the write operation will be taken into account :
\r
1272 at least four TX_CLK/RX_CLK clock cycles */
\r
1273 tmpreg = heth->Instance->MACVLANTR;
\r
1274 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1275 heth->Instance->MACVLANTR = tmpreg;
\r
1277 else /* macconf == NULL : here we just configure Speed and Duplex mode */
\r
1279 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1280 /* Get the ETHERNET MACCR value */
\r
1281 tmpreg = heth->Instance->MACCR;
\r
1283 /* Clear FES and DM bits */
\r
1284 tmpreg &= ~((uint32_t)0x00004800);
\r
1286 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
\r
1288 /* Write to ETHERNET MACCR */
\r
1289 prvWriteMACCR( heth, tmpreg );
\r
1292 /* Set the ETH state to Ready */
\r
1293 heth->State= HAL_ETH_STATE_READY;
\r
1295 /* Process Unlocked */
\r
1296 __HAL_UNLOCK( heth );
\r
1298 /* Return function status */
\r
1303 * @brief Sets ETH DMA Configuration.
\r
1304 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1305 * the configuration information for ETHERNET module
\r
1306 * @param dmaconf: DMA Configuration structure
\r
1307 * @retval HAL status
\r
1309 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
\r
1311 uint32_t tmpreg = 0;
\r
1313 /* Process Locked */
\r
1314 __HAL_LOCK( heth );
\r
1316 /* Set the ETH peripheral state to BUSY */
\r
1317 heth->State= HAL_ETH_STATE_BUSY;
\r
1319 /* Check parameters */
\r
1320 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
\r
1321 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
\r
1322 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
\r
1323 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
\r
1324 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
\r
1325 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
\r
1326 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
\r
1327 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
\r
1328 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
\r
1329 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
\r
1330 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
\r
1331 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
\r
1332 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
\r
1333 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
\r
1334 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
\r
1335 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
\r
1337 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
\r
1338 /* Get the ETHERNET DMAOMR value */
\r
1339 tmpreg = heth->Instance->DMAOMR;
\r
1340 /* Clear xx bits */
\r
1341 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1343 tmpreg |= (uint32_t)(
\r
1344 dmaconf->DropTCPIPChecksumErrorFrame |
\r
1345 dmaconf->ReceiveStoreForward |
\r
1346 dmaconf->FlushReceivedFrame |
\r
1347 dmaconf->TransmitStoreForward |
\r
1348 dmaconf->TransmitThresholdControl |
\r
1349 dmaconf->ForwardErrorFrames |
\r
1350 dmaconf->ForwardUndersizedGoodFrames |
\r
1351 dmaconf->ReceiveThresholdControl |
\r
1352 dmaconf->SecondFrameOperate);
\r
1354 /* Write to ETHERNET DMAOMR */
\r
1355 prvWriteDMAOMR( heth, tmpreg );
\r
1357 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
\r
1358 heth->Instance->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
\r
1359 dmaconf->FixedBurst |
\r
1360 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1361 dmaconf->TxDMABurstLength |
\r
1362 dmaconf->EnhancedDescriptorFormat |
\r
1363 (dmaconf->DescriptorSkipLength << 2) |
\r
1364 dmaconf->DMAArbitration |
\r
1365 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1367 /* Wait until the write operation will be taken into account:
\r
1368 at least four TX_CLK/RX_CLK clock cycles */
\r
1369 tmpreg = heth->Instance->DMABMR;
\r
1370 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1371 heth->Instance->DMABMR = tmpreg;
\r
1373 /* Set the ETH state to Ready */
\r
1374 heth->State= HAL_ETH_STATE_READY;
\r
1376 /* Process Unlocked */
\r
1377 __HAL_UNLOCK( heth );
\r
1379 /* Return function status */
\r
1387 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
\r
1388 * @brief Peripheral State functions
\r
1391 ===============================================================================
\r
1392 ##### Peripheral State functions #####
\r
1393 ===============================================================================
\r
1395 This subsection permits to get in run-time the status of the peripheral
\r
1396 and the data flow.
\r
1397 (+) Get the ETH handle state:
\r
1398 HAL_ETH_GetState();
\r
1406 * @brief Return the ETH HAL state
\r
1407 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1408 * the configuration information for ETHERNET module
\r
1409 * @retval HAL state
\r
1411 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
\r
1413 /* Return ETH state */
\r
1414 return heth->State;
\r
1425 /** @addtogroup ETH_Private_Functions
\r
1430 * @brief Configures Ethernet MAC and DMA with default parameters.
\r
1431 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1432 * the configuration information for ETHERNET module
\r
1433 * @param err: Ethernet Init error
\r
1434 * @retval HAL status
\r
1436 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
\r
1438 ETH_MACInitTypeDef macinit;
\r
1439 ETH_DMAInitTypeDef dmainit;
\r
1440 uint32_t tmpreg = 0;
\r
1442 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
\r
1444 /* Set Ethernet duplex mode to Full-duplex */
\r
1445 heth->Init.DuplexMode = ETH_MODE_FULLDUPLEX;
\r
1447 /* Set Ethernet speed to 100M */
\r
1448 heth->Init.Speed = ETH_SPEED_100M;
\r
1451 /* Ethernet MAC default initialization **************************************/
\r
1452 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
\r
1453 macinit.Jabber = ETH_JABBER_ENABLE;
\r
1454 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
\r
1455 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
\r
1456 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
\r
1457 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
\r
1458 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
\r
1460 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
\r
1464 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
\r
1466 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
\r
1467 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
\r
1468 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
\r
1469 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
\r
1470 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
\r
1471 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
\r
1472 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
\r
1473 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
\r
1474 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
\r
1475 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
\r
1476 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
\r
1477 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
\r
1478 macinit.HashTableHigh = 0x0;
\r
1479 macinit.HashTableLow = 0x0;
\r
1480 macinit.PauseTime = 0x0;
\r
1481 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
\r
1482 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
\r
1483 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
\r
1484 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
\r
1485 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
\r
1486 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
\r
1487 macinit.VLANTagIdentifier = 0x0;
\r
1489 /*------------------------ ETHERNET MACCR Configuration --------------------*/
\r
1490 /* Get the ETHERNET MACCR value */
\r
1491 tmpreg = heth->Instance->MACCR;
\r
1492 /* Clear WD, PCE, PS, TE and RE bits */
\r
1493 tmpreg &= ETH_MACCR_CLEAR_MASK;
\r
1494 /* Set the WD bit according to ETH Watchdog value */
\r
1495 /* Set the JD: bit according to ETH Jabber value */
\r
1496 /* Set the IFG bit according to ETH InterFrameGap value */
\r
1497 /* Set the DCRS bit according to ETH CarrierSense value */
\r
1498 /* Set the FES bit according to ETH Speed value */
\r
1499 /* Set the DO bit according to ETH ReceiveOwn value */
\r
1500 /* Set the LM bit according to ETH LoopbackMode value */
\r
1501 /* Set the DM bit according to ETH Mode value */
\r
1502 /* Set the IPCO bit according to ETH ChecksumOffload value */
\r
1503 /* Set the DR bit according to ETH RetryTransmission value */
\r
1504 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
\r
1505 /* Set the BL bit according to ETH BackOffLimit value */
\r
1506 /* Set the DC bit according to ETH DeferralCheck value */
\r
1507 tmpreg |= (uint32_t)(macinit.Watchdog |
\r
1509 macinit.InterFrameGap |
\r
1510 macinit.CarrierSense |
\r
1511 heth->Init.Speed |
\r
1512 macinit.ReceiveOwn |
\r
1513 macinit.LoopbackMode |
\r
1514 heth->Init.DuplexMode |
\r
1515 macinit.ChecksumOffload |
\r
1516 macinit.RetryTransmission |
\r
1517 macinit.AutomaticPadCRCStrip |
\r
1518 macinit.BackOffLimit |
\r
1519 macinit.DeferralCheck);
\r
1521 /* Write to ETHERNET MACCR */
\r
1522 prvWriteMACCR( heth, tmpreg );
\r
1524 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
\r
1525 /* Set the RA bit according to ETH ReceiveAll value */
\r
1526 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
\r
1527 /* Set the PCF bit according to ETH PassControlFrames value */
\r
1528 /* Set the DBF bit according to ETH BroadcastFramesReception value */
\r
1529 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
\r
1530 /* Set the PR bit according to ETH PromiscuousMode value */
\r
1531 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
\r
1532 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
\r
1533 /* Write to ETHERNET MACFFR */
\r
1534 heth->Instance->MACFFR = (uint32_t)(macinit.ReceiveAll |
\r
1535 macinit.SourceAddrFilter |
\r
1536 macinit.PassControlFrames |
\r
1537 macinit.BroadcastFramesReception |
\r
1538 macinit.DestinationAddrFilter |
\r
1539 macinit.PromiscuousMode |
\r
1540 macinit.MulticastFramesFilter |
\r
1541 macinit.UnicastFramesFilter);
\r
1543 /* Wait until the write operation will be taken into account:
\r
1544 at least four TX_CLK/RX_CLK clock cycles */
\r
1545 tmpreg = heth->Instance->MACFFR;
\r
1546 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1547 heth->Instance->MACFFR = tmpreg;
\r
1549 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
\r
1550 /* Write to ETHERNET MACHTHR */
\r
1551 heth->Instance->MACHTHR = (uint32_t)macinit.HashTableHigh;
\r
1553 /* Write to ETHERNET MACHTLR */
\r
1554 heth->Instance->MACHTLR = (uint32_t)macinit.HashTableLow;
\r
1555 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
\r
1557 /* Get the ETHERNET MACFCR value */
\r
1558 tmpreg = heth->Instance->MACFCR;
\r
1559 /* Clear xx bits */
\r
1560 tmpreg &= ETH_MACFCR_CLEAR_MASK;
\r
1562 /* Set the PT bit according to ETH PauseTime value */
\r
1563 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
\r
1564 /* Set the PLT bit according to ETH PauseLowThreshold value */
\r
1565 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
\r
1566 /* Set the RFE bit according to ETH ReceiveFlowControl value */
\r
1567 /* Set the TFE bit according to ETH TransmitFlowControl value */
\r
1568 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
\r
1569 macinit.ZeroQuantaPause |
\r
1570 macinit.PauseLowThreshold |
\r
1571 macinit.UnicastPauseFrameDetect |
\r
1572 macinit.ReceiveFlowControl |
\r
1573 macinit.TransmitFlowControl);
\r
1575 /* Write to ETHERNET MACFCR */
\r
1576 prvWriteMACFCR( heth, tmpreg );
\r
1578 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
\r
1579 /* Set the ETV bit according to ETH VLANTagComparison value */
\r
1580 /* Set the VL bit according to ETH VLANTagIdentifier value */
\r
1581 heth->Instance->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
\r
1582 macinit.VLANTagIdentifier);
\r
1584 /* Wait until the write operation will be taken into account:
\r
1585 at least four TX_CLK/RX_CLK clock cycles */
\r
1586 tmpreg = heth->Instance->MACVLANTR;
\r
1587 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1588 heth->Instance->MACVLANTR = tmpreg;
\r
1590 /* Ethernet DMA default initialization ************************************/
\r
1591 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
\r
1592 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
\r
1593 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
\r
1594 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
\r
1595 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
\r
1596 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
\r
1597 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
\r
1598 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
\r
1599 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
\r
1600 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
\r
1601 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
\r
1602 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
\r
1603 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
\r
1604 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
\r
1605 dmainit.DescriptorSkipLength = 0x0;
\r
1606 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
\r
1608 /* Get the ETHERNET DMAOMR value */
\r
1609 tmpreg = heth->Instance->DMAOMR;
\r
1610 /* Clear xx bits */
\r
1611 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
\r
1613 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
\r
1614 /* Set the RSF bit according to ETH ReceiveStoreForward value */
\r
1615 /* Set the DFF bit according to ETH FlushReceivedFrame value */
\r
1616 /* Set the TSF bit according to ETH TransmitStoreForward value */
\r
1617 /* Set the TTC bit according to ETH TransmitThresholdControl value */
\r
1618 /* Set the FEF bit according to ETH ForwardErrorFrames value */
\r
1619 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
\r
1620 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
\r
1621 /* Set the OSF bit according to ETH SecondFrameOperate value */
\r
1622 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
\r
1623 dmainit.ReceiveStoreForward |
\r
1624 dmainit.FlushReceivedFrame |
\r
1625 dmainit.TransmitStoreForward |
\r
1626 dmainit.TransmitThresholdControl |
\r
1627 dmainit.ForwardErrorFrames |
\r
1628 dmainit.ForwardUndersizedGoodFrames |
\r
1629 dmainit.ReceiveThresholdControl |
\r
1630 dmainit.SecondFrameOperate);
\r
1632 /* Write to ETHERNET DMAOMR */
\r
1633 prvWriteDMAOMR( heth, tmpreg );
\r
1635 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
\r
1636 /* Set the AAL bit according to ETH AddressAlignedBeats value */
\r
1637 /* Set the FB bit according to ETH FixedBurst value */
\r
1638 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
\r
1639 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
\r
1640 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
\r
1641 /* Set the DSL bit according to ETH DesciptorSkipLength value */
\r
1642 /* Set the PR and DA bits according to ETH DMAArbitration value */
\r
1643 heth->Instance->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
\r
1644 dmainit.FixedBurst |
\r
1645 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
\r
1646 dmainit.TxDMABurstLength |
\r
1647 dmainit.EnhancedDescriptorFormat |
\r
1648 (dmainit.DescriptorSkipLength << 2) |
\r
1649 dmainit.DMAArbitration |
\r
1650 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
\r
1652 /* Wait until the write operation will be taken into account:
\r
1653 at least four TX_CLK/RX_CLK clock cycles */
\r
1654 tmpreg = heth->Instance->DMABMR;
\r
1655 HAL_Delay(ETH_REG_WRITE_DELAY);
\r
1656 heth->Instance->DMABMR = tmpreg;
\r
1658 if(heth->Init.RxMode == ETH_RXINTERRUPT_MODE)
\r
1660 /* Enable the Ethernet Rx Interrupt */
\r
1661 __HAL_ETH_DMA_ENABLE_IT(( heth ), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
\r
1664 /* Initialize MAC address in ethernet MAC */
\r
1665 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
\r
1669 * @brief Configures the selected MAC address.
\r
1670 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1671 * the configuration information for ETHERNET module
\r
1672 * @param MacAddr: The MAC address to configure
\r
1673 * This parameter can be one of the following values:
\r
1674 * @arg ETH_MAC_Address0: MAC Address0
\r
1675 * @arg ETH_MAC_Address1: MAC Address1
\r
1676 * @arg ETH_MAC_Address2: MAC Address2
\r
1677 * @arg ETH_MAC_Address3: MAC Address3
\r
1678 * @param Addr: Pointer to MAC address buffer data (6 bytes)
\r
1679 * @retval HAL status
\r
1681 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
\r
1685 /* Check the parameters */
\r
1686 assert_param( IS_ETH_MAC_ADDRESS0123( MacAddr ) );
\r
1688 /* Calculate the selected MAC address high register */
\r
1689 tmpreg = 0x80000000ul | ( ( uint32_t )Addr[ 5 ] << 8) | (uint32_t)Addr[ 4 ];
\r
1690 /* Load the selected MAC address high register */
\r
1691 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_HBASE + MacAddr ) ) ) = tmpreg;
\r
1692 /* Calculate the selected MAC address low register */
\r
1693 tmpreg = ( ( uint32_t )Addr[ 3 ] << 24 ) | ( ( uint32_t )Addr[ 2 ] << 16 ) | ( ( uint32_t )Addr[ 1 ] << 8 ) | Addr[ 0 ];
\r
1695 /* Load the selected MAC address low register */
\r
1696 ( * ( __IO uint32_t * ) ( ( uint32_t ) ( ETH_MAC_ADDR_LBASE + MacAddr ) ) ) = tmpreg;
\r
1700 * @brief Enables the MAC transmission.
\r
1701 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1702 * the configuration information for ETHERNET module
\r
1705 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
\r
1707 uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_TE;
\r
1709 prvWriteMACCR( heth, tmpreg );
\r
1713 * @brief Disables the MAC transmission.
\r
1714 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1715 * the configuration information for ETHERNET module
\r
1718 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
\r
1720 uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_TE );
\r
1722 prvWriteMACCR( heth, tmpreg );
\r
1726 * @brief Enables the MAC reception.
\r
1727 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1728 * the configuration information for ETHERNET module
\r
1731 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
\r
1733 __IO uint32_t tmpreg = heth->Instance->MACCR | ETH_MACCR_RE;
\r
1735 prvWriteMACCR( heth, tmpreg );
\r
1739 * @brief Disables the MAC reception.
\r
1740 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1741 * the configuration information for ETHERNET module
\r
1744 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
\r
1746 __IO uint32_t tmpreg = heth->Instance->MACCR & ~( ETH_MACCR_RE );
\r
1748 prvWriteMACCR( heth, tmpreg );
\r
1752 * @brief Enables the DMA transmission.
\r
1753 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1754 * the configuration information for ETHERNET module
\r
1757 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
\r
1759 /* Enable the DMA transmission */
\r
1760 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_ST;
\r
1762 prvWriteDMAOMR( heth, tmpreg );
\r
1766 * @brief Disables the DMA transmission.
\r
1767 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1768 * the configuration information for ETHERNET module
\r
1771 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
\r
1773 /* Disable the DMA transmission */
\r
1774 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_ST );
\r
1776 prvWriteDMAOMR( heth, tmpreg );
\r
1780 * @brief Enables the DMA reception.
\r
1781 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1782 * the configuration information for ETHERNET module
\r
1785 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
\r
1787 /* Enable the DMA reception */
\r
1788 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_SR;
\r
1790 prvWriteDMAOMR( heth, tmpreg );
\r
1794 * @brief Disables the DMA reception.
\r
1795 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1796 * the configuration information for ETHERNET module
\r
1799 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
\r
1801 /* Disable the DMA reception */
\r
1802 __IO uint32_t tmpreg = heth->Instance->DMAOMR & ~( ETH_DMAOMR_SR );
\r
1804 prvWriteDMAOMR( heth, tmpreg );
\r
1808 * @brief Clears the ETHERNET transmit FIFO.
\r
1809 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
\r
1810 * the configuration information for ETHERNET module
\r
1813 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
\r
1815 /* Set the Flush Transmit FIFO bit */
\r
1816 __IO uint32_t tmpreg = heth->Instance->DMAOMR | ETH_DMAOMR_FTF;
\r
1818 prvWriteDMAOMR( heth, tmpreg );
\r
1825 #endif /* STM32F7xx */
\r
1826 #endif /* HAL_ETH_MODULE_ENABLED */
\r
1835 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
\r