2 * FreeRTOS V202002.00
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://aws.amazon.com/freertos
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23 * http://www.FreeRTOS.org
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26 #include "FreeRTOS.h"
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31 /* FreeRTOS+TCP includes. */
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32 #include "FreeRTOS_IP.h"
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33 #include "FreeRTOS_Sockets.h"
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34 #include "FreeRTOS_IP_Private.h"
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35 #include "NetworkBufferManagement.h"
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37 #include "Zynq/x_emacpsif.h"
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38 #include "Zynq/x_topology.h"
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39 #include "xstatus.h"
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41 #include "xparameters.h"
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42 #include "xparameters_ps.h"
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43 #include "xil_exception.h"
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44 #include "xil_mmu.h"
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46 #include "uncached_memory.h"
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48 /* Two defines used to set or clear the EMAC interrupt */
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49 #define INTC_BASE_ADDR XPAR_SCUGIC_CPU_BASEADDR
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50 #define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR
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54 #if( ipconfigPACKET_FILLER_SIZE != 2 )
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55 #error Please define ipconfigPACKET_FILLER_SIZE as the value '2'
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57 #define TX_OFFSET ipconfigPACKET_FILLER_SIZE
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59 #define dmaRX_TX_BUFFER_SIZE 1536
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61 /* Defined in NetworkInterface.c */
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62 extern TaskHandle_t xEMACTaskHandle;
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65 pxDMA_tx_buffers: these are character arrays, each one is big enough to hold 1 MTU.
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66 The actual TX buffers are located in uncached RAM.
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68 static unsigned char *pxDMA_tx_buffers[ ipconfigNIC_N_TX_DESC ] = { NULL };
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71 pxDMA_rx_buffers: these are pointers to 'NetworkBufferDescriptor_t'.
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72 Once a message has been received by the EMAC, the descriptor can be passed
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73 immediately to the IP-task.
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75 static NetworkBufferDescriptor_t *pxDMA_rx_buffers[ ipconfigNIC_N_RX_DESC ] = { NULL };
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78 The FreeRTOS+TCP port is using a fixed 'topology', which is declared in
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79 ./portable/NetworkInterface/Zynq/NetworkInterface.c
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81 extern struct xtopology_t xXTopology;
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83 static SemaphoreHandle_t xTXDescriptorSemaphore = NULL;
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86 The FreeRTOS+TCP port does not make use of "src/xemacps_bdring.c".
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87 In stead 'struct xemacpsif_s' has a "head" and a "tail" index.
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88 "head" is the next index to be written, used.
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89 "tail" is the next index to be read, freed.
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92 int is_tx_space_available( xemacpsif_s *xemacpsif )
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96 if( xTXDescriptorSemaphore != NULL )
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98 uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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102 uxCount = ( UBaseType_t ) 0u;
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108 void emacps_check_tx( xemacpsif_s *xemacpsif )
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110 int tail = xemacpsif->txTail;
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111 int head = xemacpsif->txHead;
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112 size_t uxCount = ( ( UBaseType_t ) ipconfigNIC_N_TX_DESC ) - uxSemaphoreGetCount( xTXDescriptorSemaphore );
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114 /* uxCount is the number of TX descriptors that are in use by the DMA. */
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115 /* When done, "TXBUF_USED" will be set. */
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117 while( ( uxCount > 0 ) && ( ( xemacpsif->txSegments[ tail ].flags & XEMACPS_TXBUF_USED_MASK ) != 0 ) )
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119 if( ( tail == head ) && ( uxCount != ipconfigNIC_N_TX_DESC ) )
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124 void *pvBuffer = pxDMA_tx_buffers[ tail ];
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125 NetworkBufferDescriptor_t *pxBuffer;
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127 if( pvBuffer != NULL )
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129 pxDMA_tx_buffers[ tail ] = NULL;
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130 pxBuffer = pxPacketBuffer_to_NetworkBuffer( pvBuffer );
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131 if( pxBuffer != NULL )
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133 vReleaseNetworkBufferAndDescriptor( pxBuffer );
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137 FreeRTOS_printf( ( "emacps_check_tx: Can not find network buffer\n" ) );
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141 /* Clear all but the "used" and "wrap" bits. */
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142 if( tail < ipconfigNIC_N_TX_DESC - 1 )
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144 xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK;
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148 xemacpsif->txSegments[ tail ].flags = XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK;
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151 /* Tell the counting semaphore that one more TX descriptor is available. */
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152 xSemaphoreGive( xTXDescriptorSemaphore );
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153 if( ++tail == ipconfigNIC_N_TX_DESC )
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157 xemacpsif->txTail = tail;
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163 void emacps_send_handler(void *arg)
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165 xemacpsif_s *xemacpsif;
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166 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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168 xemacpsif = (xemacpsif_s *)(arg);
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170 /* This function is called from an ISR. The Xilinx ISR-handler has already
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171 cleared the TXCOMPL and TXSR_USEDREAD status bits in the XEMACPS_TXSR register.
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172 But it forgets to do a read-back. Do so now to avoid ever-returning ISR's. */
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173 ( void ) XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_TXSR_OFFSET);
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175 /* In this port for FreeRTOS+TCP, the EMAC interrupts will only set a bit in
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176 "isr_events". The task in NetworkInterface will wake-up and do the necessary work.
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178 xemacpsif->isr_events |= EMAC_IF_TX_EVENT;
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179 xemacpsif->txBusy = pdFALSE;
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181 if( xEMACTaskHandle != NULL )
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183 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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186 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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189 static BaseType_t xValidLength( BaseType_t xLength )
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191 BaseType_t xReturn;
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193 if( ( xLength >= ( BaseType_t ) sizeof( struct xARP_PACKET ) ) && ( ( ( uint32_t ) xLength ) <= dmaRX_TX_BUFFER_SIZE ) )
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205 XStatus emacps_send_message(xemacpsif_s *xemacpsif, NetworkBufferDescriptor_t *pxBuffer, int iReleaseAfterSend )
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207 int head = xemacpsif->txHead;
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209 uint32_t ulBaseAddress = xemacpsif->emacps.Config.BaseAddress;
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210 TickType_t xBlockTimeTicks = pdMS_TO_TICKS( 5000u );
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212 /* This driver wants to own all network buffers which are to be transmitted. */
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213 configASSERT( iReleaseAfterSend != pdFALSE );
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215 /* Open a do {} while ( 0 ) loop to be able to call break. */
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218 uint32_t ulFlags = 0;
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220 if( xValidLength( pxBuffer->xDataLength ) != pdTRUE )
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225 if( xTXDescriptorSemaphore == NULL )
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230 if( xSemaphoreTake( xTXDescriptorSemaphore, xBlockTimeTicks ) != pdPASS )
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232 FreeRTOS_printf( ( "emacps_send_message: Time-out waiting for TX buffer\n" ) );
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236 /* Pass the pointer (and its ownership) directly to DMA. */
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237 pxDMA_tx_buffers[ head ] = pxBuffer->pucEthernetBuffer;
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238 if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
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240 Xil_DCacheFlushRange( ( unsigned )pxBuffer->pucEthernetBuffer, pxBuffer->xDataLength );
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242 /* Buffer has been transferred, do not release it. */
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243 iReleaseAfterSend = pdFALSE;
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245 /* Packets will be sent one-by-one, so for each packet
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246 the TXBUF_LAST bit will be set. */
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247 ulFlags |= XEMACPS_TXBUF_LAST_MASK;
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248 ulFlags |= ( pxBuffer->xDataLength & XEMACPS_TXBUF_LEN_MASK );
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249 if( head == ( ipconfigNIC_N_TX_DESC - 1 ) )
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251 ulFlags |= XEMACPS_TXBUF_WRAP_MASK;
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254 /* Copy the address of the buffer and set the flags. */
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255 xemacpsif->txSegments[ head ].address = ( uint32_t )pxDMA_tx_buffers[ head ];
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256 xemacpsif->txSegments[ head ].flags = ulFlags;
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259 if( ++head == ipconfigNIC_N_TX_DESC )
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263 /* Update the TX-head index. These variable are declared volatile so they will be
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264 accessed as little as possible. */
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265 xemacpsif->txHead = head;
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266 } while( pdFALSE );
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268 if( iReleaseAfterSend != pdFALSE )
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270 vReleaseNetworkBufferAndDescriptor( pxBuffer );
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274 /* Data Synchronization Barrier */
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277 if( iHasSent != pdFALSE )
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279 /* Make STARTTX high */
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280 uint32_t ulValue = XEmacPs_ReadReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET);
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281 /* Start transmit */
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282 xemacpsif->txBusy = pdTRUE;
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283 XEmacPs_WriteReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET, ( ulValue | XEMACPS_NWCTRL_STARTTX_MASK ) );
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284 /* Read back the register to make sure the data is flushed. */
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285 ( void ) XEmacPs_ReadReg( ulBaseAddress, XEMACPS_NWCTRL_OFFSET );
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292 void emacps_recv_handler(void *arg)
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294 xemacpsif_s *xemacpsif;
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295 BaseType_t xHigherPriorityTaskWoken = pdFALSE;
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297 xemacpsif = (xemacpsif_s *)(arg);
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298 xemacpsif->isr_events |= EMAC_IF_RX_EVENT;
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300 /* The driver has already cleared the FRAMERX, BUFFNA and error bits
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301 in the XEMACPS_RXSR register,
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302 But it forgets to do a read-back. Do so now. */
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303 ( void ) XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET);
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305 if( xEMACTaskHandle != NULL )
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307 vTaskNotifyGiveFromISR( xEMACTaskHandle, &xHigherPriorityTaskWoken );
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310 portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
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313 static void prvPassEthMessages( NetworkBufferDescriptor_t *pxDescriptor )
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315 IPStackEvent_t xRxEvent;
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317 xRxEvent.eEventType = eNetworkRxEvent;
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318 xRxEvent.pvData = ( void * ) pxDescriptor;
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320 if( xSendEventStructToIPTask( &xRxEvent, ( TickType_t ) 1000 ) != pdPASS )
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322 /* The buffer could not be sent to the stack so must be released again.
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323 This is a deferred handler taskr, not a real interrupt, so it is ok to
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324 use the task level function here. */
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325 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
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329 NetworkBufferDescriptor_t *pxNext = pxDescriptor->pxNextBuffer;
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330 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
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331 pxDescriptor = pxNext;
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332 } while( pxDescriptor != NULL );
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336 vReleaseNetworkBufferAndDescriptor( pxDescriptor );
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338 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
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339 iptraceETHERNET_RX_EVENT_LOST();
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340 FreeRTOS_printf( ( "prvPassEthMessages: Can not queue return packet!\n" ) );
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344 int emacps_check_rx( xemacpsif_s *xemacpsif )
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346 NetworkBufferDescriptor_t *pxBuffer, *pxNewBuffer;
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348 volatile int msgCount = 0;
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349 int head = xemacpsif->rxHead;
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350 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
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351 NetworkBufferDescriptor_t *pxFirstDescriptor = NULL;
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352 NetworkBufferDescriptor_t *pxLastDescriptor = NULL;
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353 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
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355 /* There seems to be an issue (SI# 692601), see comments below. */
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356 resetrx_on_no_rxdata(xemacpsif);
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358 /* This FreeRTOS+TCP driver shall be compiled with the option
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359 "ipconfigUSE_LINKED_RX_MESSAGES" enabled. It allows the driver to send a
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360 chain of RX messages within one message to the IP-task. */
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363 if( ( ( xemacpsif->rxSegments[ head ].address & XEMACPS_RXBUF_NEW_MASK ) == 0 ) ||
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364 ( pxDMA_rx_buffers[ head ] == NULL ) )
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369 pxNewBuffer = pxGetNetworkBufferWithDescriptor( dmaRX_TX_BUFFER_SIZE, ( TickType_t ) 0 );
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370 if( pxNewBuffer == NULL )
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372 /* A packet has been received, but there is no replacement for this Network Buffer.
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373 The packet will be dropped, and it Network Buffer will stay in place. */
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374 FreeRTOS_printf( ("emacps_check_rx: unable to allocate a Network Buffer\n" ) );
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375 pxNewBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ];
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379 pxBuffer = ( NetworkBufferDescriptor_t * )pxDMA_rx_buffers[ head ];
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381 /* Just avoiding to use or refer to the same buffer again */
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382 pxDMA_rx_buffers[ head ] = pxNewBuffer;
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385 * Adjust the buffer size to the actual number of bytes received.
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387 rx_bytes = xemacpsif->rxSegments[ head ].flags & XEMACPS_RXBUF_LEN_MASK;
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389 pxBuffer->xDataLength = rx_bytes;
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391 if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
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393 Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, (unsigned)rx_bytes );
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396 /* store it in the receive queue, where it'll be processed by a
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397 different handler. */
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398 iptraceNETWORK_INTERFACE_RECEIVE();
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399 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
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401 pxBuffer->pxNextBuffer = NULL;
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403 if( pxFirstDescriptor == NULL )
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405 // Becomes the first message
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406 pxFirstDescriptor = pxBuffer;
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408 else if( pxLastDescriptor != NULL )
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411 pxLastDescriptor->pxNextBuffer = pxBuffer;
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414 pxLastDescriptor = pxBuffer;
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418 prvPassEthMessages( pxBuffer );
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420 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
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425 if( ucIsCachedMemory( pxNewBuffer->pucEthernetBuffer ) != 0 )
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427 Xil_DCacheInvalidateRange( ( ( uint32_t ) pxNewBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE, ( uint32_t ) dmaRX_TX_BUFFER_SIZE );
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430 uint32_t addr = ( ( uint32_t )pxNewBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK;
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431 if( head == ( ipconfigNIC_N_RX_DESC - 1 ) )
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433 addr |= XEMACPS_RXBUF_WRAP_MASK;
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435 /* Clearing 'XEMACPS_RXBUF_NEW_MASK' 0x00000001 *< Used bit.. */
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436 xemacpsif->rxSegments[ head ].flags = 0;
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437 xemacpsif->rxSegments[ head ].address = addr;
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438 /* Make sure that the value has reached the peripheral by reading it back. */
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439 ( void ) xemacpsif->rxSegments[ head ].address;
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443 if( ++head == ipconfigNIC_N_RX_DESC )
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447 xemacpsif->rxHead = head;
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450 #if( ipconfigUSE_LINKED_RX_MESSAGES != 0 )
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452 if( pxFirstDescriptor != NULL )
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454 prvPassEthMessages( pxFirstDescriptor );
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457 #endif /* ipconfigUSE_LINKED_RX_MESSAGES */
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462 void clean_dma_txdescs(xemacpsif_s *xemacpsif)
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465 unsigned char *ucTxBuffer;
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467 /* Clear all TX descriptors and assign uncached memory to each descriptor.
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468 "tx_space" points to the first available TX buffer. */
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469 ucTxBuffer = xemacpsif->tx_space;
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471 for( index = 0; index < ipconfigNIC_N_TX_DESC; index++ )
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473 xemacpsif->txSegments[ index ].address = ( uint32_t )ucTxBuffer;
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474 xemacpsif->txSegments[ index ].flags = XEMACPS_TXBUF_USED_MASK;
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475 pxDMA_tx_buffers[ index ] = ( unsigned char * )NULL;
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476 ucTxBuffer += xemacpsif->uTxUnitSize;
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478 xemacpsif->txSegments[ ipconfigNIC_N_TX_DESC - 1 ].flags =
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479 XEMACPS_TXBUF_USED_MASK | XEMACPS_TXBUF_WRAP_MASK;
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482 XStatus init_dma(xemacpsif_s *xemacpsif)
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484 NetworkBufferDescriptor_t *pxBuffer;
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487 UBaseType_t xRxSize;
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488 UBaseType_t xTxSize;
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489 struct xtopology_t *xtopologyp = &xXTopology;
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491 xRxSize = ipconfigNIC_N_RX_DESC * sizeof( xemacpsif->rxSegments[ 0 ] );
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493 xTxSize = ipconfigNIC_N_TX_DESC * sizeof( xemacpsif->txSegments[ 0 ] );
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495 xemacpsif->uTxUnitSize = dmaRX_TX_BUFFER_SIZE;
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497 * We allocate 65536 bytes for RX BDs which can accommodate a
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498 * maximum of 8192 BDs which is much more than any application
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501 xemacpsif->rxSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xRxSize ) );
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502 xemacpsif->txSegments = ( struct xBD_TYPE * )( pucGetUncachedMemory ( xTxSize ) );
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503 xemacpsif->tx_space = ( unsigned char * )( pucGetUncachedMemory ( ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize ) );
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505 /* These variables will be used in XEmacPs_Start (see src/xemacps.c). */
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506 xemacpsif->emacps.RxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->rxSegments;
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507 xemacpsif->emacps.TxBdRing.BaseBdAddr = ( uint32_t ) xemacpsif->txSegments;
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509 if( xTXDescriptorSemaphore == NULL )
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511 xTXDescriptorSemaphore = xSemaphoreCreateCounting( ( UBaseType_t ) ipconfigNIC_N_TX_DESC, ( UBaseType_t ) ipconfigNIC_N_TX_DESC );
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512 configASSERT( xTXDescriptorSemaphore );
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515 * Allocate RX descriptors, 1 RxBD at a time.
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517 for( iIndex = 0; iIndex < ipconfigNIC_N_RX_DESC; iIndex++ )
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519 pxBuffer = pxDMA_rx_buffers[ iIndex ];
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520 if( pxBuffer == NULL )
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522 pxBuffer = pxGetNetworkBufferWithDescriptor( dmaRX_TX_BUFFER_SIZE, ( TickType_t ) 0 );
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523 if( pxBuffer == NULL )
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525 FreeRTOS_printf( ("Unable to allocate a network buffer in recv_handler\n" ) );
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530 xemacpsif->rxSegments[ iIndex ].flags = 0;
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531 xemacpsif->rxSegments[ iIndex ].address = ( ( uint32_t )pxBuffer->pucEthernetBuffer ) & XEMACPS_RXBUF_ADD_MASK;
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533 pxDMA_rx_buffers[ iIndex ] = pxBuffer;
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534 /* Make sure this memory is not in cache for now. */
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535 if( ucIsCachedMemory( pxBuffer->pucEthernetBuffer ) != 0 )
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537 Xil_DCacheInvalidateRange( ( ( uint32_t )pxBuffer->pucEthernetBuffer ) - ipconfigPACKET_FILLER_SIZE,
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538 (unsigned)dmaRX_TX_BUFFER_SIZE );
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542 xemacpsif->rxSegments[ ipconfigNIC_N_RX_DESC - 1 ].address |= XEMACPS_RXBUF_WRAP_MASK;
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544 memset( xemacpsif->tx_space, '\0', ipconfigNIC_N_TX_DESC * xemacpsif->uTxUnitSize );
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546 clean_dma_txdescs( xemacpsif );
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550 value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET );
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552 // 1xxxx: Attempt to use INCR16 AHB bursts
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553 value = ( value & ~( XEMACPS_DMACR_BLENGTH_MASK ) ) | XEMACPS_DMACR_INCR16_AHB_BURST;
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554 #if( ipconfigDRIVER_INCLUDED_TX_IP_CHECKSUM != 0 )
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555 value |= XEMACPS_DMACR_TCPCKSUM_MASK;
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557 #warning Are you sure the EMAC should not calculate outgoing checksums?
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558 value &= ~XEMACPS_DMACR_TCPCKSUM_MASK;
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560 XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_DMACR_OFFSET, value );
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564 value = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET );
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566 /* Network buffers are 32-bit aligned + 2 bytes (because ipconfigPACKET_FILLER_SIZE = 2 ).
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567 Now tell the EMAC that received messages should be stored at "address + 2". */
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568 value = ( value & ~XEMACPS_NWCFG_RXOFFS_MASK ) | 0x8000;
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570 #if( ipconfigDRIVER_INCLUDED_RX_IP_CHECKSUM != 0 )
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571 value |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
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573 #warning Are you sure the EMAC should not calculate incoming checksums?
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574 value &= ~XEMACPS_NWCFG_RXCHKSUMEN_MASK;
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576 XEmacPs_WriteReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCFG_OFFSET, value );
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580 * Connect the device driver handler that will be called when an
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581 * interrupt for the device occurs, the handler defined above performs
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582 * the specific interrupt processing for the device.
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584 XScuGic_RegisterHandler(INTC_BASE_ADDR, xtopologyp->scugic_emac_intr,
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585 (Xil_ExceptionHandler)XEmacPs_IntrHandler,
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586 (void *)&xemacpsif->emacps);
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588 * Enable the interrupt for emacps.
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596 * resetrx_on_no_rxdata():
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598 * It is called at regular intervals through the API xemacpsif_resetrx_on_no_rxdata
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599 * called by the user.
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600 * The EmacPs has a HW bug (SI# 692601) on the Rx path for heavy Rx traffic.
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601 * Under heavy Rx traffic because of the HW bug there are times when the Rx path
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602 * becomes unresponsive. The workaround for it is to check for the Rx path for
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603 * traffic (by reading the stats registers regularly). If the stats register
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604 * does not increment for sometime (proving no Rx traffic), the function resets
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605 * the Rx data path.
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609 void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif)
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611 unsigned long regctrl;
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612 unsigned long tempcntr;
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614 tempcntr = XEmacPs_ReadReg( xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET );
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615 if ( ( tempcntr == 0 ) && ( xemacpsif->last_rx_frms_cntr == 0 ) )
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617 regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
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618 XEMACPS_NWCTRL_OFFSET);
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619 regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
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620 XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
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621 XEMACPS_NWCTRL_OFFSET, regctrl);
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622 regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
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623 regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
\r
624 XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
\r
626 xemacpsif->last_rx_frms_cntr = tempcntr;
\r
629 void EmacDisableIntr(void)
\r
631 XScuGic_DisableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr);
\r
634 void EmacEnableIntr(void)
\r
636 XScuGic_EnableIntr(INTC_DIST_BASE_ADDR, xXTopology.scugic_emac_intr);
\r