1 /*******************************************************************************
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2 * Trace Recorder Library for Tracealyzer v3.0.2
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3 * Percepio AB, www.percepio.com
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7 * The hardware abstraction layer for the trace recorder library.
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10 * This software (the "Tracealyzer Recorder Library") is the intellectual
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11 * property of Percepio AB and may not be sold or in other ways commercially
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12 * redistributed without explicit written permission by Percepio AB.
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14 * Separate conditions applies for the SEGGER branded source code included.
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16 * The recorder library is free for use together with Percepio products.
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17 * You may distribute the recorder library in its original form, but public
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18 * distribution of modified versions require approval by Percepio AB.
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21 * The trace tool and recorder library is being delivered to you AS IS and
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22 * Percepio AB makes no warranty as to its use or performance. Percepio AB does
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23 * not and cannot warrant the performance or results you may obtain by using the
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24 * software or documentation. Percepio AB make no warranties, express or
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25 * implied, as to noninfringement of third party rights, merchantability, or
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26 * fitness for any particular purpose. In no event will Percepio AB, its
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27 * technology partners, or distributors be liable to you for any consequential,
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28 * incidental or special damages, including any lost profits or lost savings,
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29 * even if a representative of Percepio AB has been advised of the possibility
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30 * of such damages, or for any claim by any third party. Some jurisdictions do
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31 * not allow the exclusion or limitation of incidental, consequential or special
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32 * damages, or the exclusion of implied warranties or limitations on how long an
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33 * implied warranty may last, so the above limitations may not apply to you.
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35 * Tabs are used for indent in this file (1 tab = 4 spaces)
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37 * Copyright Percepio AB, 2015.
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39 ******************************************************************************/
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41 #ifndef TRC_HARDWARE_PORT_H
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42 #define TRC_HARDWARE_PORT_H
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50 /******************************************************************************
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52 * To get accurate timestamping, a hardware timer is necessary. Below are the
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53 * available ports. Some of these are "unofficial", meaning that
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54 * they have not yet been verified by Percepio but have been contributed by
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55 * external developers. They should work, otherwise let us know by emailing
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56 * support@percepio.com. Some work on any OS platform, while other are specific
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57 * to a certain operating system.
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58 *****************************************************************************/
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61 /****** Port Name ***************************** Code */
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62 #define TRC_PORT_APPLICATION_DEFINED -1
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63 #define TRC_PORT_NOT_SET 0
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64 #define TRC_PORT_ARM_Cortex_M 1
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65 #define TRC_PORT_ARM_CORTEX_A9 2
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66 #define TRC_PORT_Renesas_RX600 3
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67 #define TRC_PORT_TEXAS_INSTRUMENTS_TMS570_RM48 4
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68 #define TRC_PORT_MICROCHIP_PIC32_MX_MZ 5
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70 /*******************************************************************************
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72 * HWTC Macros - Hardware Timer/Counter Isolation Layer
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74 * These two HWTC macros provides a hardware isolation layer representing a
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75 * generic hardware timer/counter used for the timestamping.
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77 * HWTC_COUNT: The current value of the counter. This is expected to be reset
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78 * a each tick interrupt. Thus, when the tick handler starts, the counter has
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81 * HWTC_TYPE: Defines the type of timer/counter used for HWTC_COUNT:
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83 * - FREE_RUNNING_32BIT_INCR:
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84 * Free-running 32-bit timer, counting upwards from 0 - > 0xFFFFFFFF
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86 * - FREE_RUNNING_32BIT_DECR
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87 * Free-running 32-bit counter, counting downwards from 0xFFFFFFFF -> 0
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90 * Interrupt timer, counts upwards from 0 until HWTC_PERIOD-1
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93 * Interrupt timer, counts downwards from HWTC_PERIOD-1 until 0
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95 *******************************************************************************
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97 * IRQ_PRIORITY_ORDER
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99 * Macro which should be defined as an integer of 0 or 1.
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101 * It is only used only to sort and colorize the interrupts in priority order,
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102 * in case you record interrupts using the vTraceStoreISRBegin and
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103 * vTraceStoreISREnd routines. 1 indicates higher value is more important.
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105 ******************************************************************************/
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107 #define TRC_FREE_RUNNING_32BIT_INCR 1
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108 #define TRC_FREE_RUNNING_32BIT_DECR 2
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109 #define TRC_OS_TIMER_INCR 3
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110 #define TRC_OS_TIMER_DECR 4
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112 #if (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_ARM_Cortex_M)
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114 #define HWTC_TYPE TRC_OS_TIMER_DECR
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115 #define HWTC_COUNT (*((uint32_t*)0xE000E018)) /* SysTick counter */
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116 #define IRQ_PRIORITY_ORDER 0
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118 #elif (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_Renesas_RX600)
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120 #include "iodefine.h"
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122 #define HWTC_TYPE TRC_OS_TIMER_INCR
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123 #define HWTC_COUNT (CMT0.CMCNT)
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124 #define IRQ_PRIORITY_ORDER 1
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126 #elif (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_MICROCHIP_PIC32_MX_MZ)
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128 #define HWTC_TYPE TRC_OS_TIMER_INCR
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129 #define HWTC_COUNT (TMR1)
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130 #define IRQ_PRIORITY_ORDER 0
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132 #elif (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_TEXAS_INSTRUMENTS_TMS570_RM48)
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134 #define RTIFRC0 *((uint32_t *)0xFFFFFC10)
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135 #define RTICOMP0 *((uint32_t *)0xFFFFFC50)
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136 #define RTIUDCP0 *((uint32_t *)0xFFFFFC54)
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138 #define HWTC_TYPE TRC_OS_TIMER_INCR
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139 #define HWTC_COUNT (RTIFRC0 - (RTICOMP0 - RTIUDCP0))
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140 #define IRQ_PRIORITY_ORDER 0
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142 #elif (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_ARM_CORTEX_A9)
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143 /* INPUT YOUR PERIPHERAL BASE ADDRESS HERE */
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144 #define CA9_MPCORE_PERIPHERAL_BASE_ADDRESS 0xSOMETHING
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146 #define CA9_MPCORE_PRIVATE_MEMORY_OFFSET 0x0600
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147 #define CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x00))
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148 #define CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x04))
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149 #define CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(CA9_MPCORE_PERIPHERAL_BASE_ADDRESS + CA9_MPCORE_PRIVATE_MEMORY_OFFSET + 0x08))
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151 #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
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152 #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
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153 #define CA9_MPCORE_PRIVCTR_PRESCALER (((CA9_MPCORE_PRIVCTR_CONTROL_REG & CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
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155 #define HWTC_TYPE TRC_OS_TIMER_DECR
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156 #define HWTC_COUNT CA9_MPCORE_PRIVCTR_COUNTER_REG
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157 #define IRQ_PRIORITY_ORDER 0
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159 #elif (TRC_RECORDER_HARDWARE_PORT == TRC_PORT_APPLICATION_DEFINED)
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161 #if !( defined (HWTC_TYPE) && defined (HWTC_COUNT) && defined (IRQ_PRIORITY_ORDER))
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162 #error RECORDER_HARDWARE_PORT is PORT_APPLICATION_DEFINED but not all of the necessary constants have been defined.
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165 #elif (TRC_RECORDER_HARDWARE_PORT != TRC_PORT_NOT_SET)
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167 #error "RECORDER_HARDWARE_PORT had unsupported value!"
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168 #define TRC_RECORDER_HARDWARE_PORT PORT_NOT_SET
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172 #if (TRC_RECORDER_HARDWARE_PORT != TRC_PORT_NOT_SET)
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175 #error "HWTC_COUNT is not set!"
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179 #error "HWTC_TYPE is not set!"
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182 #ifndef IRQ_PRIORITY_ORDER
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183 #error "IRQ_PRIORITY_ORDER is not set!"
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184 #elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
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185 #error "IRQ_PRIORITY_ORDER has bad value!"
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194 #endif /* TRC_HARDWARE_PORT_H */
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