1 /*******************************************************************************
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2 * Tracealyzer v2.7.7 Recorder Library
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3 * Percepio AB, www.percepio.com
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7 * Contains together with trcHardwarePort.c all hardware portability issues of
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8 * the trace recorder library.
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11 * This software is copyright Percepio AB. The recorder library is free for
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12 * use together with Percepio products. You may distribute the recorder library
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13 * in its original form, including modifications in trcPort.c and trcPort.h
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14 * given that these modification are clearly marked as your own modifications
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15 * and documented in the initial comment section of these source files.
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16 * This software is the intellectual property of Percepio AB and may not be
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17 * sold or in other ways commercially redistributed without explicit written
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18 * permission by Percepio AB.
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21 * The trace tool and recorder library is being delivered to you AS IS and
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22 * Percepio AB makes no warranty as to its use or performance. Percepio AB does
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23 * not and cannot warrant the performance or results you may obtain by using the
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24 * software or documentation. Percepio AB make no warranties, express or
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25 * implied, as to noninfringement of third party rights, merchantability, or
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26 * fitness for any particular purpose. In no event will Percepio AB, its
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27 * technology partners, or distributors be liable to you for any consequential,
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28 * incidental or special damages, including any lost profits or lost savings,
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29 * even if a representative of Percepio AB has been advised of the possibility
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30 * of such damages, or for any claim by any third party. Some jurisdictions do
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31 * not allow the exclusion or limitation of incidental, consequential or special
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32 * damages, or the exclusion of implied warranties or limitations on how long an
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33 * implied warranty may last, so the above limitations may not apply to you.
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35 * Tabs are used for indent in this file (1 tab = 4 spaces)
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37 * Copyright Percepio AB, 2012-2015.
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39 ******************************************************************************/
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49 #define _WIN32_WINNT 0x0600
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51 /* Standard includes. */
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53 #include <windows.h>
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56 /*******************************************************************************
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57 * The Win32 port by default saves the trace to file and then kills the
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58 * program when the recorder is stopped, to facilitate quick, simple tests
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60 ******************************************************************************/
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61 #define WIN32_PORT_SAVE_WHEN_STOPPED 1
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62 #define WIN32_PORT_EXIT_WHEN_STOPPED 1
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66 #define DIRECTION_INCREMENTING 1
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67 #define DIRECTION_DECREMENTING 2
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69 /******************************************************************************
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72 * PORT_HWIndependent
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73 * A hardware independent fallback option for event timestamping. Provides low
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74 * resolution timestamps based on the OS tick.
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75 * This may be used on the Win32 port, but may also be used on embedded hardware
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76 * platforms. All time durations will be truncated to the OS tick frequency,
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77 * typically 1 KHz. This means that a task or ISR that executes in less than
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78 * 1 ms get an execution time of zero.
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80 * PORT_APPLICATION_DEFINED
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81 * Allows for defining the port macros in other source code files.
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84 * "Accurate" timestamping based on the Windows performance counter for Win32
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85 * builds. Note that this gives the host machine time, not the kernel time.
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87 * Hardware specific ports
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88 * To get accurate timestamping, a hardware timer is necessary. Below are the
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89 * available ports. Some of these are "unofficial", meaning that
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90 * they have not yet been verified by Percepio but have been contributed by
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91 * external developers. They should work, otherwise let us know by emailing
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92 * support@percepio.com. Some work on any OS platform, while other are specific
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93 * to a certain operating system.
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94 *****************************************************************************/
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96 /****** Port Name ********************** Code ***** Official ** OS Platform *********/
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97 #define PORT_APPLICATION_DEFINED -2 /* - - */
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98 #define PORT_NOT_SET -1 /* - - */
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99 #define PORT_HWIndependent 0 /* Yes Any */
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100 #define PORT_Win32 1 /* Yes FreeRTOS on Win32 */
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101 #define PORT_Atmel_AT91SAM7 2 /* No Any */
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102 #define PORT_Atmel_UC3A0 3 /* No Any */
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103 #define PORT_ARM_CortexM 4 /* Yes Any */
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104 #define PORT_Renesas_RX600 5 /* Yes Any */
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105 #define PORT_Microchip_dsPIC_AND_PIC24 6 /* Yes Any */
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106 #define PORT_TEXAS_INSTRUMENTS_TMS570 7 /* No Any */
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107 #define PORT_TEXAS_INSTRUMENTS_MSP430 8 /* No Any */
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108 #define PORT_MICROCHIP_PIC32MX 9 /* Yes Any */
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109 #define PORT_XILINX_PPC405 10 /* No FreeRTOS */
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110 #define PORT_XILINX_PPC440 11 /* No FreeRTOS */
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111 #define PORT_XILINX_MICROBLAZE 12 /* No Any */
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112 #define PORT_NXP_LPC210X 13 /* No Any */
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113 #define PORT_MICROCHIP_PIC32MZ 14 /* Yes Any */
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114 #define PORT_ARM_CORTEX_A9 15 /* No Any */
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115 #define PORT_ARM_CORTEX_M0 16 /* Yes Any */
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117 #include "trcConfig.h"
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119 /*******************************************************************************
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120 * IRQ_PRIORITY_ORDER
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122 * Macro which should be defined as an integer of 0 or 1.
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124 * This should be 0 if lower IRQ priority values implies higher priority
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125 * levels, such as on ARM Cortex M. If the opposite scheme is used, i.e.,
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126 * if higher IRQ priority values means higher priority, this should be 1.
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128 * This setting is not critical. It is used only to sort and colorize the
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129 * interrupts in priority order, in case you record interrupts using
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130 * the vTraceStoreISRBegin and vTraceStoreISREnd routines.
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132 ******************************************************************************
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136 * These four HWTC macros provides a hardware isolation layer representing a
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137 * generic hardware timer/counter used for driving the operating system tick,
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138 * such as the SysTick feature of ARM Cortex M3/M4, or the PIT of the Atmel
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141 * HWTC_COUNT: The current value of the counter. This is expected to be reset
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142 * a each tick interrupt. Thus, when the tick handler starts, the counter has
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145 * HWTC_COUNT_DIRECTION: Should be one of:
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146 * - DIRECTION_INCREMENTING - for hardware timer/counters of incrementing type
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147 * such as the PIT on Atmel AT91SAM7X.
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148 * When the counter value reach HWTC_PERIOD, it is reset to zero and the
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149 * interrupt is signaled.
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150 * - DIRECTION_DECREMENTING - for hardware timer/counters of decrementing type
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151 * such as the SysTick on ARM Cortex M3/M4 chips.
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152 * When the counter value reach 0, it is reset to HWTC_PERIOD and the
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153 * interrupt is signaled.
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155 * HWTC_PERIOD: The number of increments or decrements of HWTC_COUNT between
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156 * two OS tick interrupts. This should preferably be mapped to the reload
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157 * register of the hardware timer, to make it more portable between chips in the
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158 * same family. The macro should in most cases be (reload register + 1).
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159 * For FreeRTOS, this can in most cases be defined as
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160 * #define HWTC_PERIOD (configCPU_CLOCK_HZ / configTICK_RATE_HZ)
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162 * HWTC_DIVISOR: If the timer frequency is very high, like on the Cortex M chips
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163 * (where the SysTick runs at the core clock frequency), the "differential
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164 * timestamping" used in the recorder will more frequently insert extra XTS
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165 * events to store the timestamps, which increases the event buffer usage.
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166 * In such cases, to reduce the number of XTS events and thereby get longer
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167 * traces, you use HWTC_DIVISOR to scale down the timestamps and frequency.
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168 * Assuming a OS tick rate of 1 KHz, it is suggested to keep the effective timer
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169 * frequency below 65 MHz to avoid an excessive amount of XTS events. Thus, a
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170 * Cortex M chip running at 72 MHZ should use a HWTC_DIVISOR of 2, while a
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171 * faster chip require a higher HWTC_DIVISOR value.
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173 * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
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174 * or the trace recorder library. Typically you should not need to change
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175 * the code of vTracePortGetTimeStamp if using the HWTC macros.
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177 ******************************************************************************/
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179 #if (SELECTED_PORT == PORT_Win32)
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180 // This can be used as a template for any free-running 32-bit counter
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181 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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182 #define HWTC_COUNT (ulGetRunTimeCounterValue())
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183 #define HWTC_PERIOD 0
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184 #define HWTC_DIVISOR 1
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186 // Please update according to your system...
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187 #define IRQ_PRIORITY_ORDER 1
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189 #elif (SELECTED_PORT == PORT_HWIndependent)
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190 // OS Tick only (typically 1 ms resolution)
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191 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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192 #define HWTC_COUNT 0
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193 #define HWTC_PERIOD 1
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194 #define HWTC_DIVISOR 1
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196 // Please update according to your system...
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197 #define IRQ_PRIORITY_ORDER NOT_SET
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200 #elif (SELECTED_PORT == PORT_ARM_CortexM)
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202 void prvTraceInitCortexM(void);
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204 #define REG_DEMCR (*(volatile unsigned int*)0xE000EDFC)
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205 #define REG_DWT_CTRL (*(volatile unsigned int*)0xE0001000)
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206 #define REG_DWT_CYCCNT (*(volatile unsigned int*)0xE0001004)
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207 #define REG_DWT_EXCCNT (*(volatile unsigned int*)0xE000100C)
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209 /* Bit mask for TRCENA bit in DEMCR - Global enable for DWT and ITM */
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210 #define DEMCR_TRCENA (1 << 24)
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212 /* Bit mask for NOPRFCNT bit in DWT_CTRL. If 1, DWT_EXCCNT is not supported */
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213 #define DWT_CTRL_NOPRFCNT (1 << 24)
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215 /* Bit mask for NOCYCCNT bit in DWT_CTRL. If 1, DWT_CYCCNT is not supported */
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216 #define DWT_CTRL_NOCYCCNT (1 << 25)
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218 /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_EXCCNT */
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219 #define DWT_CTRL_EXCEVTENA (1 << 18)
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221 /* Bit mask for EXCEVTENA_ bit in DWT_CTRL. Set to 1 to enable DWT_CYCCNT */
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222 #define DWT_CTRL_CYCCNTENA (1)
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224 #define PORT_SPECIFIC_INIT() prvTraceInitCortexM()
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226 extern uint32_t DWT_CYCLES_ADDED;
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228 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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229 #define HWTC_COUNT (REG_DWT_CYCCNT + DWT_CYCLES_ADDED)
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230 #define HWTC_PERIOD 0
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231 #define HWTC_DIVISOR 4
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233 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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235 #elif (SELECTED_PORT == PORT_ARM_CORTEX_M0)
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236 #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
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237 #define HWTC_COUNT (*((uint32_t*)0xE000E018))
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238 #define HWTC_PERIOD ((*(uint32_t*)0xE000E014) + 1)
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239 #define HWTC_DIVISOR 2
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241 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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243 #elif (SELECTED_PORT == PORT_Renesas_RX600)
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245 #include "iodefine.h"
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247 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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248 #define HWTC_COUNT (CMT0.CMCNT)
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249 #define HWTC_PERIOD (CMT0.CMCOR + 1)
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250 #define HWTC_DIVISOR 1
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251 #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
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253 #elif ((SELECTED_PORT == PORT_MICROCHIP_PIC32MX) || (SELECTED_PORT == PORT_MICROCHIP_PIC32MZ))
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255 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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256 #define HWTC_COUNT (TMR1)
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257 #define HWTC_PERIOD (PR1 + 1)
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258 #define HWTC_DIVISOR 1
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259 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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261 #elif (SELECTED_PORT == PORT_Microchip_dsPIC_AND_PIC24)
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263 /* For Microchip PIC24 and dsPIC (16 bit) */
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265 /* Note: The trace library is designed for 32-bit MCUs and is slower than
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266 intended on 16-bit MCUs. Storing an event on a PIC24 takes about 70 usec.
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267 In comparison, this is 10-20 times faster on a 32-bit MCU... */
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269 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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270 #define HWTC_COUNT (TMR1)
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271 #define HWTC_PERIOD (PR1+1)
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272 #define HWTC_DIVISOR 1
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273 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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275 #elif (SELECTED_PORT == PORT_Atmel_AT91SAM7)
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277 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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279 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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280 #define HWTC_COUNT ((uint32_t)(AT91C_BASE_PITC->PITC_PIIR & 0xFFFFF))
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281 #define HWTC_PERIOD ((uint32_t)(AT91C_BASE_PITC->PITC_PIMR + 1))
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282 #define HWTC_DIVISOR 1
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283 #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
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285 #elif (SELECTED_PORT == PORT_Atmel_UC3A0)
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287 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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288 /* For Atmel AVR32 (AT32UC3A).*/
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290 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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291 #define HWTC_COUNT ((uint32_t)sysreg_read(AVR32_COUNT))
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292 #define HWTC_PERIOD ((uint32_t)(sysreg_read(AVR32_COMPARE) + 1))
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293 #define HWTC_DIVISOR 1
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294 #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
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296 #elif (SELECTED_PORT == PORT_NXP_LPC210X)
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298 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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299 /* Tested with LPC2106, but should work with most LPC21XX chips. */
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301 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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302 #define HWTC_COUNT *((uint32_t *)0xE0004008 )
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303 #define HWTC_PERIOD *((uint32_t *)0xE0004018 )
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304 #define HWTC_DIVISOR 1
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305 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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307 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_TMS570)
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309 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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311 #define TRC_RTIFRC0 *((uint32_t *)0xFFFFFC10)
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312 #define TRC_RTICOMP0 *((uint32_t *)0xFFFFFC50)
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313 #define TRC_RTIUDCP0 *((uint32_t *)0xFFFFFC54)
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314 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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315 #define HWTC_COUNT (TRC_RTIFRC0 - (TRC_RTICOMP0 - TRC_RTIUDCP0))
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316 #define HWTC_PERIOD (RTIUDCP0)
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317 #define HWTC_DIVISOR 1
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319 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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321 #elif (SELECTED_PORT == PORT_TEXAS_INSTRUMENTS_MSP430)
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323 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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325 #define HWTC_COUNT_DIRECTION DIRECTION_INCREMENTING
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326 #define HWTC_COUNT (TA0R)
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327 #define HWTC_PERIOD (((uint16_t)TACCR0)+1)
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328 #define HWTC_DIVISOR 1
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329 #define IRQ_PRIORITY_ORDER 1 // higher IRQ priority values are more significant
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331 #elif (SELECTED_PORT == PORT_XILINX_PPC405)
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333 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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335 #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
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336 #define HWTC_COUNT mfspr(0x3db)
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337 #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
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338 /* For FreeRTOS only - found no generic OS independent solution for the PPC405 architecture. */
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339 #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC405
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341 /* Not defined for other operating systems yet */
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342 #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
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344 #define HWTC_DIVISOR 1
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345 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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347 #elif (SELECTED_PORT == PORT_XILINX_PPC440)
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349 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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350 /* This should work with most PowerPC chips */
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352 #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
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353 #define HWTC_COUNT mfspr(0x016)
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354 #if (defined configCPU_CLOCK_HZ && defined configTICK_RATE_HZ) // Check if FreeRTOS
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355 /* For FreeRTOS only - found no generic OS independent solution for the PPC440 architecture. */
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356 #define HWTC_PERIOD ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) // Same as in port.c for PPC440
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358 /* Not defined for other operating systems yet */
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359 #error HWTC_PERIOD must be defined to give the number of hardware timer ticks per OS tick.
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361 #define HWTC_DIVISOR 1
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362 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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364 #elif (SELECTED_PORT == PORT_XILINX_MICROBLAZE)
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366 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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368 /* This should work with most Microblaze configurations.
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369 * It uses the AXI Timer 0 - the tick interrupt source.
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370 * If an AXI Timer 0 peripheral is available on your hardware platform, no modifications are required.
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372 #include "xtmrctr_l.h"
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374 #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
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375 #define HWTC_COUNT XTmrCtr_GetTimerCounterReg( XPAR_TMRCTR_0_BASEADDR, 0 )
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376 #define HWTC_PERIOD (XTmrCtr_mGetLoadReg( XPAR_TMRCTR_0_BASEADDR, 0) + 1)
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377 #define HWTC_DIVISOR 16
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378 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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380 #elif (SELECTED_PORT == PORT_ARM_CORTEX_A9)
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382 /* UNOFFICIAL PORT - NOT YET VERIFIED BY PERCEPIO */
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384 #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK 0x0000FF00
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385 #define CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT 8
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387 #define CA9_MPCORE_PRIVCTR_PERIOD_REG (*(volatile uint32_t*)(0xF8F00600 + 0))
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388 #define CA9_MPCORE_PRIVCTR_COUNTER_REG (*(volatile uint32_t*)(0xF8F00600 + 4))
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389 #define CA9_MPCORE_PRIVCTR_CONTROL_REG (*(volatile uint32_t*)(0xF8F00600 + 8))
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391 #define CA9_MPCORE_PRIVCTR_PRESCALER (((CA9_MPCORE_PRIVCTR_CONTROL_REG & CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_MASK) >> CA9_MPCORE_PRIVCTR_CONTROL_PRESCALER_SHIFT) + 1)
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394 #define HWTC_COUNT_DIRECTION DIRECTION_DECREMENTING
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395 #define HWTC_COUNT CA9_MPCORE_PRIVCTR_COUNTER_REG
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396 #define HWTC_PERIOD ((CA9_MPCORE_PRIVCTR_PERIOD_REG * CA9_MPCORE_PRIVCTR_PRESCALER) + 1)
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398 //NOTE: The private timer ticks with a very high frequency (half the core-clock usually),
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399 //but offers the possibility to apply a prescaler. Depending on the prescaler you set the
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400 //HWTC_DIVISOR may need to be raised. Refer to the notes at the beginning of this file
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401 //for more information.
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402 #define HWTC_DIVISOR 1
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404 #define IRQ_PRIORITY_ORDER 0 // lower IRQ priority values are more significant
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406 #elif (SELECTED_PORT == PORT_APPLICATION_DEFINED)
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408 #if !( defined (HWTC_COUNT_DIRECTION) && defined (HWTC_COUNT) && defined (HWTC_PERIOD) && defined (HWTC_DIVISOR) && defined (IRQ_PRIORITY_ORDER) )
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409 #error SELECTED_PORT is PORT_APPLICATION_DEFINED but not all of the necessary constants have been defined.
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412 #elif (SELECTED_PORT != PORT_NOT_SET)
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414 #error "SELECTED_PORT had unsupported value!"
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415 #define SELECTED_PORT PORT_NOT_SET
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419 #if (SELECTED_PORT != PORT_NOT_SET)
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421 #ifndef HWTC_COUNT_DIRECTION
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422 #error "HWTC_COUNT_DIRECTION is not set!"
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426 #error "HWTC_COUNT is not set!"
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429 #ifndef HWTC_PERIOD
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430 #error "HWTC_PERIOD is not set!"
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433 #ifndef HWTC_DIVISOR
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434 #error "HWTC_DIVISOR is not set!"
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437 #ifndef IRQ_PRIORITY_ORDER
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438 #error "IRQ_PRIORITY_ORDER is not set!"
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439 #elif (IRQ_PRIORITY_ORDER != 0) && (IRQ_PRIORITY_ORDER != 1)
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440 #error "IRQ_PRIORITY_ORDER has bad value!"
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443 #if (HWTC_DIVISOR < 1)
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444 #error "HWTC_DIVISOR must be a non-zero positive value!"
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448 /*******************************************************************************
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449 * vTraceConsoleMessage
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451 * A wrapper for your system-specific console "printf" console output function.
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452 * This needs to be correctly defined to see status reports from the trace
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453 * status monitor task (this is defined in trcUser.c).
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454 ******************************************************************************/
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455 #define vTraceConsoleMessage(x)
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457 /*******************************************************************************
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458 * vTracePortGetTimeStamp
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460 * Returns the current time based on the HWTC macros which provide a hardware
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461 * isolation layer towards the hardware timer/counter.
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463 * The HWTC macros and vTracePortGetTimeStamp is the main porting issue
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464 * or the trace recorder library. Typically you should not need to change
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465 * the code of vTracePortGetTimeStamp if using the HWTC macros.
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467 ******************************************************************************/
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468 void vTracePortGetTimeStamp(uint32_t *puiTimestamp);
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