2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
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30 * running on your hardware - or even write all or part of your application*
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31 * for you? See http://www.OpenRTOS.com for details. *
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33 ***************************************************************************
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34 ***************************************************************************
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36 Please ensure to read the configuration and relevant port sections of the
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37 online documentation.
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39 http://www.FreeRTOS.org - Documentation, latest information, license and
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42 http://www.SafeRTOS.com - A version that is certified for use in safety
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45 http://www.OpenRTOS.com - Commercial support, development, porting,
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46 licensing and training services.
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50 /*-----------------------------------------------------------
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51 * Implementation of functions defined in portable.h for the Atmel AT91R40008
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54 * Components that can be compiled to either ARM or THUMB mode are
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55 * contained in this file. The ISR routines, which can only be compiled
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56 * to ARM mode are contained in portISR.c.
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57 *----------------------------------------------------------*/
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59 /* Standard includes. */
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62 /* Scheduler includes. */
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63 #include "FreeRTOS.h"
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66 /* Hardware specific definitions. */
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67 #include "AT91R40008.h"
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72 /* Constants required to setup the task context. */
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73 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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74 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
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75 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
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76 #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )
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77 #define portTICK_PRIORITY_6 ( 6 )
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78 /*-----------------------------------------------------------*/
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80 /* Setup the timer to generate the tick interrupts. */
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81 static void prvSetupTimerInterrupt( void );
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84 * The scheduler can only be started from ARM mode, so
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85 * vPortISRStartFirstSTask() is defined in portISR.c.
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87 extern void vPortISRStartFirstTask( void );
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89 /*-----------------------------------------------------------*/
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92 * Initialise the stack of a task to look exactly as if a call to
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93 * portSAVE_CONTEXT had been called.
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95 * See header file for description.
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97 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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99 portSTACK_TYPE *pxOriginalTOS;
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101 pxOriginalTOS = pxTopOfStack;
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103 /* Setup the initial stack of the task. The stack is set exactly as
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104 expected by the portRESTORE_CONTEXT() macro. */
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106 /* First on the stack is the return address - which in this case is the
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107 start of the task. The offset is added to make the return address appear
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108 as it would within an IRQ ISR. */
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109 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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112 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
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114 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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116 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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118 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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120 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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122 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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124 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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126 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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128 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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130 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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132 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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134 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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136 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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138 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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141 /* When the task starts is will expect to find the function parameter in
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143 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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146 /* The last thing onto the stack is the status register, which is set for
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147 system mode, with interrupts enabled. */
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148 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
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150 #ifdef THUMB_INTERWORK
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152 /* We want the task to start in thumb mode. */
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153 *pxTopOfStack |= portTHUMB_MODE_BIT;
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159 /* Some optimisation levels use the stack differently to others. This
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160 means the interrupt flags cannot always be stored on the stack and will
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161 instead be stored in a variable, which is then saved as part of the
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163 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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165 return pxTopOfStack;
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167 /*-----------------------------------------------------------*/
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169 portBASE_TYPE xPortStartScheduler( void )
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171 /* Start the timer that generates the tick ISR. Interrupts are disabled
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173 prvSetupTimerInterrupt();
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175 /* Start the first task. */
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176 vPortISRStartFirstTask();
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178 /* Should not get here! */
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181 /*-----------------------------------------------------------*/
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183 void vPortEndScheduler( void )
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185 /* It is unlikely that the ARM port will require this function as there
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186 is nothing to return to. */
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188 /*-----------------------------------------------------------*/
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191 * Setup the tick timer to generate the tick interrupts at the required frequency.
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193 static void prvSetupTimerInterrupt( void )
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195 volatile unsigned portLONG ulDummy;
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197 /* Enable clock to the tick timer... */
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198 AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
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200 /* Stop the tick timer... */
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201 portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
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203 /* Start with tick timer interrupts disabled... */
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204 portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
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206 /* Clear any pending tick timer interrupts... */
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207 ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
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209 /* Store interrupt handler function address in tick timer vector register...
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210 The ISR installed depends on whether the preemptive or cooperative
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211 scheduler is being used. */
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212 #if configUSE_PREEMPTION == 1
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214 extern void ( vPreemptiveTick )( void );
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215 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vPreemptiveTick;
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217 #else // else use cooperative scheduler
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219 extern void ( vNonPreemptiveTick )( void );
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220 AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( unsigned portLONG ) vNonPreemptiveTick;
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224 /* Tick timer interrupt level-sensitive, priority 6... */
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225 AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
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227 /* Enable the tick timer interrupt...
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229 First at timer level */
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230 portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
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232 /* Then at the AIC level. */
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233 AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
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235 /* Calculate timer compare value to achieve the desired tick rate... */
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236 if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
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238 /* The tick rate is fast enough for us to use the faster timer input
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239 clock (main clock / 2). */
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240 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
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241 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
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245 /* We must use a slower timer input clock (main clock / 8) because the
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246 tick rate is too slow for the faster input clock. */
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247 portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
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248 portTIMER_REG_BASE_PTR->TC_RC = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
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251 /* Start tick timer... */
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252 portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
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254 /*-----------------------------------------------------------*/
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