2 FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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37 /*-----------------------------------------------------------
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38 * Implementation of functions defined in portable.h for the ARM7 port.
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40 * Components that can be compiled to either ARM or THUMB mode are
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41 * contained in this file. The ISR routines, which can only be compiled
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42 * to ARM mode are contained in portISR.c.
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43 *----------------------------------------------------------*/
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48 + ulCriticalNesting is now saved as part of the task context, as is
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49 therefore added to the initial task stack during pxPortInitialiseStack.
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53 /* Standard includes. */
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56 /* Scheduler includes. */
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57 #include "FreeRTOS.h"
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60 /* Processor constants. */
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61 #include "AT91SAM7X256.h"
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63 /* Constants required to setup the task context. */
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64 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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65 #define portTHUMB_MODE_BIT ( ( portSTACK_TYPE ) 0x20 )
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66 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
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67 #define portNO_CRITICAL_SECTION_NESTING ( ( portSTACK_TYPE ) 0 )
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69 /* Constants required to setup the tick ISR. */
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70 #define portENABLE_TIMER ( ( unsigned portCHAR ) 0x01 )
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71 #define portPRESCALE_VALUE 0x00
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72 #define portINTERRUPT_ON_MATCH ( ( unsigned portLONG ) 0x01 )
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73 #define portRESET_COUNT_ON_MATCH ( ( unsigned portLONG ) 0x02 )
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75 /* Constants required to setup the PIT. */
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76 #define portPIT_CLOCK_DIVISOR ( ( unsigned portLONG ) 16 )
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77 #define portPIT_COUNTER_VALUE ( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_RATE_MS )
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79 #define portINT_LEVEL_SENSITIVE 0
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80 #define portPIT_ENABLE ( ( unsigned portSHORT ) 0x1 << 24 )
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81 #define portPIT_INT_ENABLE ( ( unsigned portSHORT ) 0x1 << 25 )
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82 /*-----------------------------------------------------------*/
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84 /* Setup the timer to generate the tick interrupts. */
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85 static void prvSetupTimerInterrupt( void );
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88 * The scheduler can only be started from ARM mode, so
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89 * vPortISRStartFirstSTask() is defined in portISR.c.
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91 extern void vPortISRStartFirstTask( void );
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93 /*-----------------------------------------------------------*/
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96 * Initialise the stack of a task to look exactly as if a call to
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97 * portSAVE_CONTEXT had been called.
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99 * See header file for description.
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101 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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103 portSTACK_TYPE *pxOriginalTOS;
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105 pxOriginalTOS = pxTopOfStack;
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107 /* Setup the initial stack of the task. The stack is set exactly as
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108 expected by the portRESTORE_CONTEXT() macro. */
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110 /* First on the stack is the return address - which in this case is the
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111 start of the task. The offset is added to make the return address appear
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112 as it would within an IRQ ISR. */
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113 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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116 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
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118 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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120 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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122 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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124 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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126 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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128 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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130 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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132 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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134 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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136 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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138 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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140 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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142 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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145 /* When the task starts is will expect to find the function parameter in
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147 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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150 /* The last thing onto the stack is the status register, which is set for
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151 system mode, with interrupts enabled. */
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152 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
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154 #ifdef THUMB_INTERWORK
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156 /* We want the task to start in thumb mode. */
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157 *pxTopOfStack |= portTHUMB_MODE_BIT;
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163 /* Some optimisation levels use the stack differently to others. This
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164 means the interrupt flags cannot always be stored on the stack and will
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165 instead be stored in a variable, which is then saved as part of the
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167 *pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
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169 return pxTopOfStack;
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171 /*-----------------------------------------------------------*/
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173 portBASE_TYPE xPortStartScheduler( void )
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175 /* Start the timer that generates the tick ISR. Interrupts are disabled
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177 prvSetupTimerInterrupt();
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179 /* Start the first task. */
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180 vPortISRStartFirstTask();
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182 /* Should not get here! */
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185 /*-----------------------------------------------------------*/
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187 void vPortEndScheduler( void )
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189 /* It is unlikely that the ARM port will require this function as there
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190 is nothing to return to. */
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192 /*-----------------------------------------------------------*/
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195 * Setup the timer 0 to generate the tick interrupts at the required frequency.
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197 static void prvSetupTimerInterrupt( void )
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199 AT91PS_PITC pxPIT = AT91C_BASE_PITC;
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201 /* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
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202 on whether the preemptive or cooperative scheduler is being used. */
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203 #if configUSE_PREEMPTION == 0
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205 extern void ( vNonPreemptiveTick ) ( void );
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206 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
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210 extern void ( vPreemptiveTick )( void );
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211 AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
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215 /* Configure the PIT period. */
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216 pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
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218 /* Enable the interrupt. Global interrupts are disables at this point so
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220 AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
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222 /*-----------------------------------------------------------*/
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