2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
\r
4 This file is part of the FreeRTOS.org distribution.
\r
6 FreeRTOS.org is free software; you can redistribute it and/or modify
\r
7 it under the terms of the GNU General Public License as published by
\r
8 the Free Software Foundation; either version 2 of the License, or
\r
9 (at your option) any later version.
\r
11 FreeRTOS.org is distributed in the hope that it will be useful,
\r
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 GNU General Public License for more details.
\r
16 You should have received a copy of the GNU General Public License
\r
17 along with FreeRTOS.org; if not, write to the Free Software
\r
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
20 A special exception to the GPL can be applied should you wish to distribute
\r
21 a combined work that includes FreeRTOS.org, without being obliged to provide
\r
22 the source code for any proprietary components. See the licensing section
\r
23 of http://www.FreeRTOS.org for full details of how and when the exception
\r
26 ***************************************************************************
\r
27 ***************************************************************************
\r
29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
\r
30 * running on your hardware - or even write all or part of your application*
\r
31 * for you? See http://www.OpenRTOS.com for details. *
\r
33 ***************************************************************************
\r
34 ***************************************************************************
\r
36 Please ensure to read the configuration and relevant port sections of the
\r
37 online documentation.
\r
39 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
42 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
45 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
46 licensing and training services.
\r
50 /*-----------------------------------------------------------
\r
51 * Components that can be compiled to either ARM or THUMB mode are
\r
52 * contained in port.c The ISR routines, which can only be compiled
\r
53 * to ARM mode, are contained in this file.
\r
54 *----------------------------------------------------------*/
\r
59 + The assembler statements are now included in a single asm block rather
\r
60 than each line having its own asm block.
\r
63 /* Scheduler includes. */
\r
64 #include "FreeRTOS.h"
\r
67 #include "AT91SAM7X256.h"
\r
69 /* Constants required to handle interrupts. */
\r
70 #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
\r
71 #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
\r
73 /* Constants required to handle critical sections. */
\r
74 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
\r
75 volatile unsigned portLONG ulCriticalNesting = 9999UL;
\r
77 /*-----------------------------------------------------------*/
\r
79 /* ISR to handle manual context switches (from a call to taskYIELD()). */
\r
80 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
\r
83 * The scheduler can only be started from ARM mode, hence the inclusion of this
\r
86 void vPortISRStartFirstTask( void );
\r
87 /*-----------------------------------------------------------*/
\r
89 void vPortISRStartFirstTask( void )
\r
91 /* Simply start the scheduler. This is included here as it can only be
\r
92 called from ARM mode. */
\r
93 portRESTORE_CONTEXT();
\r
95 /*-----------------------------------------------------------*/
\r
98 * Called by portYIELD() or taskYIELD() to manually force a context switch.
\r
100 * When a context switch is performed from the task level the saved task
\r
101 * context is made to look as if it occurred from within the tick ISR. This
\r
102 * way the same restore context function can be used when restoring the context
\r
103 * saved from the ISR or that saved from a call to vPortYieldProcessor.
\r
105 void vPortYieldProcessor( void )
\r
107 /* Within an IRQ ISR the link register has an offset from the true return
\r
108 address, but an SWI ISR does not. Add the offset manually so the same
\r
109 ISR return code can be used in both cases. */
\r
110 asm volatile ( "ADD LR, LR, #4" );
\r
112 /* Perform the context switch. First save the context of the current task. */
\r
113 portSAVE_CONTEXT();
\r
115 /* Find the highest priority task that is ready to run. */
\r
116 vTaskSwitchContext();
\r
118 /* Restore the context of the new task. */
\r
119 portRESTORE_CONTEXT();
\r
121 /*-----------------------------------------------------------*/
\r
124 * The ISR used for the scheduler tick depends on whether the cooperative or
\r
125 * the preemptive scheduler is being used.
\r
128 #if configUSE_PREEMPTION == 0
\r
130 /* The cooperative scheduler requires a normal IRQ service routine to
\r
131 simply increment the system tick. */
\r
132 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
\r
133 void vNonPreemptiveTick( void )
\r
135 unsigned portLONG ulDummy;
\r
137 /* Increment the tick count - which may wake some tasks but as the
\r
138 preemptive scheduler is not being used any woken task is not given
\r
139 processor time no matter what its priority. */
\r
140 vTaskIncrementTick();
\r
142 /* Clear the PIT interrupt. */
\r
143 ulDummy = AT91C_BASE_PITC->PITC_PIVR;
\r
145 /* End the interrupt in the AIC. */
\r
146 AT91C_BASE_AIC->AIC_EOICR = ulDummy;
\r
151 /* The preemptive scheduler is defined as "naked" as the full context is
\r
152 saved on entry as part of the context switch. */
\r
153 void vPreemptiveTick( void ) __attribute__((naked));
\r
154 void vPreemptiveTick( void )
\r
156 /* Save the context of the current task. */
\r
157 portSAVE_CONTEXT();
\r
159 /* Increment the tick count - this may wake a task. */
\r
160 vTaskIncrementTick();
\r
162 /* Find the highest priority task that is ready to run. */
\r
163 vTaskSwitchContext();
\r
165 /* End the interrupt in the AIC. */
\r
166 AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
\r
168 portRESTORE_CONTEXT();
\r
172 /*-----------------------------------------------------------*/
\r
175 * The interrupt management utilities can only be called from ARM mode. When
\r
176 * THUMB_INTERWORK is defined the utilities are defined as functions here to
\r
177 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
\r
178 * the utilities are defined as macros in portmacro.h - as per other ports.
\r
180 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
181 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
\r
183 void vPortDisableInterruptsFromThumb( void )
\r
186 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
187 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
188 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
189 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
190 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
191 "BX R14" ); /* Return back to thumb. */
\r
194 void vPortEnableInterruptsFromThumb( void )
\r
197 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
198 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
199 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
200 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
201 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
\r
202 "BX R14" ); /* Return back to thumb. */
\r
206 /* The code generated by the GCC compiler uses the stack in different ways at
\r
207 different optimisation levels. The interrupt flags can therefore not always
\r
208 be saved to the stack. Instead the critical section nesting level is stored
\r
209 in a variable, which is then saved as part of the stack context. */
\r
210 void vPortEnterCritical( void )
\r
212 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
\r
214 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
215 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
216 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
\r
217 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
218 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r
220 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
221 directly. Increment ulCriticalNesting to keep a count of how many times
\r
222 portENTER_CRITICAL() has been called. */
\r
223 ulCriticalNesting++;
\r
226 void vPortExitCritical( void )
\r
228 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
230 /* Decrement the nesting count as we are leaving a critical section. */
\r
231 ulCriticalNesting--;
\r
233 /* If the nesting level has reached zero then interrupts should be
\r
235 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
237 /* Enable interrupts as per portEXIT_CRITICAL(). */
\r
239 "STMDB SP!, {R0} \n\t" /* Push R0. */
\r
240 "MRS R0, CPSR \n\t" /* Get CPSR. */
\r
241 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
\r
242 "MSR CPSR, R0 \n\t" /* Write back modified value. */
\r
243 "LDMIA SP!, {R0}" ); /* Pop R0. */
\r