2 FreeRTOS V6.0.4 - Copyright (C) 2010 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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9 * + Wanting to learn FreeRTOS or multitasking in general quickly *
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10 * + Looking for basic training, *
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11 * + Wanting to improve your FreeRTOS skills and productivity *
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13 * then take a look at the FreeRTOS eBook *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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18 * A pdf reference manual is also available. Both are usually delivered *
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19 * to your inbox within 20 minutes to two hours when purchased between 8am *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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55 /*-----------------------------------------------------------
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56 * Components that can be compiled to either ARM or THUMB mode are
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57 * contained in port.c The ISR routines, which can only be compiled
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58 * to ARM mode, are contained in this file.
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59 *----------------------------------------------------------*/
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64 + The assembler statements are now included in a single asm block rather
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65 than each line having its own asm block.
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68 /* Scheduler includes. */
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69 #include "FreeRTOS.h"
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72 #include "AT91SAM7X256.h"
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74 /* Constants required to handle interrupts. */
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75 #define portTIMER_MATCH_ISR_BIT ( ( unsigned char ) 0x01 )
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76 #define portCLEAR_VIC_INTERRUPT ( ( unsigned long ) 0 )
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78 /* Constants required to handle critical sections. */
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79 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
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80 volatile unsigned long ulCriticalNesting = 9999UL;
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82 /*-----------------------------------------------------------*/
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84 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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85 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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88 * The scheduler can only be started from ARM mode, hence the inclusion of this
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91 void vPortISRStartFirstTask( void );
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92 /*-----------------------------------------------------------*/
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94 void vPortISRStartFirstTask( void )
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96 /* Simply start the scheduler. This is included here as it can only be
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97 called from ARM mode. */
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98 portRESTORE_CONTEXT();
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100 /*-----------------------------------------------------------*/
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103 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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105 * When a context switch is performed from the task level the saved task
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106 * context is made to look as if it occurred from within the tick ISR. This
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107 * way the same restore context function can be used when restoring the context
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108 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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110 void vPortYieldProcessor( void )
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112 /* Within an IRQ ISR the link register has an offset from the true return
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113 address, but an SWI ISR does not. Add the offset manually so the same
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114 ISR return code can be used in both cases. */
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115 asm volatile ( "ADD LR, LR, #4" );
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117 /* Perform the context switch. First save the context of the current task. */
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118 portSAVE_CONTEXT();
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120 /* Find the highest priority task that is ready to run. */
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121 vTaskSwitchContext();
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123 /* Restore the context of the new task. */
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124 portRESTORE_CONTEXT();
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126 /*-----------------------------------------------------------*/
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129 * The ISR used for the scheduler tick depends on whether the cooperative or
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130 * the preemptive scheduler is being used.
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133 #if configUSE_PREEMPTION == 0
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135 /* The cooperative scheduler requires a normal IRQ service routine to
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136 simply increment the system tick. */
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137 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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138 void vNonPreemptiveTick( void )
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140 unsigned long ulDummy;
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142 /* Increment the tick count - which may wake some tasks but as the
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143 preemptive scheduler is not being used any woken task is not given
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144 processor time no matter what its priority. */
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145 vTaskIncrementTick();
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147 /* Clear the PIT interrupt. */
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148 ulDummy = AT91C_BASE_PITC->PITC_PIVR;
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150 /* End the interrupt in the AIC. */
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151 AT91C_BASE_AIC->AIC_EOICR = ulDummy;
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156 /* The preemptive scheduler is defined as "naked" as the full context is
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157 saved on entry as part of the context switch. */
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158 void vPreemptiveTick( void ) __attribute__((naked));
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159 void vPreemptiveTick( void )
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161 /* Save the context of the current task. */
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162 portSAVE_CONTEXT();
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164 /* Increment the tick count - this may wake a task. */
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165 vTaskIncrementTick();
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167 /* Find the highest priority task that is ready to run. */
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168 vTaskSwitchContext();
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170 /* End the interrupt in the AIC. */
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171 AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
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173 portRESTORE_CONTEXT();
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177 /*-----------------------------------------------------------*/
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180 * The interrupt management utilities can only be called from ARM mode. When
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181 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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182 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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183 * the utilities are defined as macros in portmacro.h - as per other ports.
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185 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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186 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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188 void vPortDisableInterruptsFromThumb( void )
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191 "STMDB SP!, {R0} \n\t" /* Push R0. */
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192 "MRS R0, CPSR \n\t" /* Get CPSR. */
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193 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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194 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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195 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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196 "BX R14" ); /* Return back to thumb. */
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199 void vPortEnableInterruptsFromThumb( void )
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202 "STMDB SP!, {R0} \n\t" /* Push R0. */
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203 "MRS R0, CPSR \n\t" /* Get CPSR. */
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204 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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205 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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206 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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207 "BX R14" ); /* Return back to thumb. */
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211 /* The code generated by the GCC compiler uses the stack in different ways at
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212 different optimisation levels. The interrupt flags can therefore not always
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213 be saved to the stack. Instead the critical section nesting level is stored
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214 in a variable, which is then saved as part of the stack context. */
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215 void vPortEnterCritical( void )
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217 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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219 "STMDB SP!, {R0} \n\t" /* Push R0. */
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220 "MRS R0, CPSR \n\t" /* Get CPSR. */
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221 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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222 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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223 "LDMIA SP!, {R0}" ); /* Pop R0. */
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225 /* Now interrupts are disabled ulCriticalNesting can be accessed
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226 directly. Increment ulCriticalNesting to keep a count of how many times
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227 portENTER_CRITICAL() has been called. */
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228 ulCriticalNesting++;
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231 void vPortExitCritical( void )
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233 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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235 /* Decrement the nesting count as we are leaving a critical section. */
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236 ulCriticalNesting--;
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238 /* If the nesting level has reached zero then interrupts should be
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240 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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242 /* Enable interrupts as per portEXIT_CRITICAL(). */
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244 "STMDB SP!, {R0} \n\t" /* Push R0. */
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245 "MRS R0, CPSR \n\t" /* Get CPSR. */
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246 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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247 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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248 "LDMIA SP!, {R0}" ); /* Pop R0. */
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