2 FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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37 /*-----------------------------------------------------------
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38 * Components that can be compiled to either ARM or THUMB mode are
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39 * contained in port.c The ISR routines, which can only be compiled
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40 * to ARM mode, are contained in this file.
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41 *----------------------------------------------------------*/
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46 + The assembler statements are now included in a single asm block rather
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47 than each line having its own asm block.
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50 /* Scheduler includes. */
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51 #include "FreeRTOS.h"
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54 #include "AT91SAM7X256.h"
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56 /* Constants required to handle interrupts. */
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57 #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
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58 #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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60 /* Constants required to handle critical sections. */
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61 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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62 volatile unsigned portLONG ulCriticalNesting = 9999UL;
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64 /*-----------------------------------------------------------*/
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66 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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67 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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70 * The scheduler can only be started from ARM mode, hence the inclusion of this
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73 void vPortISRStartFirstTask( void );
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74 /*-----------------------------------------------------------*/
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76 void vPortISRStartFirstTask( void )
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78 /* Simply start the scheduler. This is included here as it can only be
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79 called from ARM mode. */
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80 portRESTORE_CONTEXT();
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82 /*-----------------------------------------------------------*/
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85 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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87 * When a context switch is performed from the task level the saved task
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88 * context is made to look as if it occurred from within the tick ISR. This
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89 * way the same restore context function can be used when restoring the context
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90 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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92 void vPortYieldProcessor( void )
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94 /* Within an IRQ ISR the link register has an offset from the true return
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95 address, but an SWI ISR does not. Add the offset manually so the same
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96 ISR return code can be used in both cases. */
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97 asm volatile ( "ADD LR, LR, #4" );
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99 /* Perform the context switch. First save the context of the current task. */
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100 portSAVE_CONTEXT();
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102 /* Find the highest priority task that is ready to run. */
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103 vTaskSwitchContext();
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105 /* Restore the context of the new task. */
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106 portRESTORE_CONTEXT();
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108 /*-----------------------------------------------------------*/
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111 * The ISR used for the scheduler tick depends on whether the cooperative or
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112 * the preemptive scheduler is being used.
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115 #if configUSE_PREEMPTION == 0
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117 /* The cooperative scheduler requires a normal IRQ service routine to
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118 simply increment the system tick. */
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119 void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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120 void vNonPreemptiveTick( void )
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122 unsigned portLONG ulDummy;
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124 /* Increment the tick count - which may wake some tasks but as the
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125 preemptive scheduler is not being used any woken task is not given
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126 processor time no matter what its priority. */
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127 vTaskIncrementTick();
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129 /* Clear the PIT interrupt. */
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130 ulDummy = AT91C_BASE_PITC->PITC_PIVR;
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132 /* End the interrupt in the AIC. */
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133 AT91C_BASE_AIC->AIC_EOICR = ulDummy;
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138 /* The preemptive scheduler is defined as "naked" as the full context is
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139 saved on entry as part of the context switch. */
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140 void vPreemptiveTick( void ) __attribute__((naked));
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141 void vPreemptiveTick( void )
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143 /* Save the context of the current task. */
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144 portSAVE_CONTEXT();
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146 /* Increment the tick count - this may wake a task. */
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147 vTaskIncrementTick();
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149 /* Find the highest priority task that is ready to run. */
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150 vTaskSwitchContext();
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152 /* End the interrupt in the AIC. */
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153 AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
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155 portRESTORE_CONTEXT();
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159 /*-----------------------------------------------------------*/
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162 * The interrupt management utilities can only be called from ARM mode. When
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163 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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164 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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165 * the utilities are defined as macros in portmacro.h - as per other ports.
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167 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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168 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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170 void vPortDisableInterruptsFromThumb( void )
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173 "STMDB SP!, {R0} \n\t" /* Push R0. */
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174 "MRS R0, CPSR \n\t" /* Get CPSR. */
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175 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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176 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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177 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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178 "BX R14" ); /* Return back to thumb. */
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181 void vPortEnableInterruptsFromThumb( void )
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184 "STMDB SP!, {R0} \n\t" /* Push R0. */
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185 "MRS R0, CPSR \n\t" /* Get CPSR. */
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186 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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187 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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188 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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189 "BX R14" ); /* Return back to thumb. */
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193 /* The code generated by the GCC compiler uses the stack in different ways at
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194 different optimisation levels. The interrupt flags can therefore not always
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195 be saved to the stack. Instead the critical section nesting level is stored
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196 in a variable, which is then saved as part of the stack context. */
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197 void vPortEnterCritical( void )
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199 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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201 "STMDB SP!, {R0} \n\t" /* Push R0. */
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202 "MRS R0, CPSR \n\t" /* Get CPSR. */
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203 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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204 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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205 "LDMIA SP!, {R0}" ); /* Pop R0. */
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207 /* Now interrupts are disabled ulCriticalNesting can be accessed
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208 directly. Increment ulCriticalNesting to keep a count of how many times
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209 portENTER_CRITICAL() has been called. */
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210 ulCriticalNesting++;
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213 void vPortExitCritical( void )
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215 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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217 /* Decrement the nesting count as we are leaving a critical section. */
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218 ulCriticalNesting--;
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220 /* If the nesting level has reached zero then interrupts should be
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222 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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224 /* Enable interrupts as per portEXIT_CRITICAL(). */
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226 "STMDB SP!, {R0} \n\t" /* Push R0. */
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227 "MRS R0, CPSR \n\t" /* Get CPSR. */
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228 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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229 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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230 "LDMIA SP!, {R0}" ); /* Pop R0. */
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