2 FreeRTOS.org V5.0.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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30 * and even write all or part of your application on your behalf. *
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31 * See http://www.OpenRTOS.com for details of the services we provide to *
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32 * expedite your project. *
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34 ***************************************************************************
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35 ***************************************************************************
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37 Please ensure to read the configuration and relevant port sections of the
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38 online documentation.
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40 http://www.FreeRTOS.org - Documentation, latest information, license and
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43 http://www.SafeRTOS.com - A version that is certified for use in safety
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46 http://www.OpenRTOS.com - Commercial support, development, porting,
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47 licensing and training services.
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51 /*-----------------------------------------------------------
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52 * Components that can be compiled to either ARM or THUMB mode are
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53 * contained in port.c The ISR routines, which can only be compiled
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54 * to ARM mode, are contained in this file.
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55 *----------------------------------------------------------*/
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60 + The critical section management functions have been changed. These no
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61 longer modify the stack and are safe to use at all optimisation levels.
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62 The functions are now also the same for both ARM and THUMB modes.
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66 + Removed the 'static' from the definition of vNonPreemptiveTick() to
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67 allow the demo to link when using the cooperative scheduler.
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71 + The assembler statements are now included in a single asm block rather
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72 than each line having its own asm block.
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76 /* Scheduler includes. */
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77 #include "FreeRTOS.h"
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80 /* Constants required to handle interrupts. */
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81 #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
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82 #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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84 /* Constants required to handle critical sections. */
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85 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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86 volatile unsigned portLONG ulCriticalNesting = 9999UL;
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88 /*-----------------------------------------------------------*/
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90 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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91 void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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94 * The scheduler can only be started from ARM mode, hence the inclusion of this
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97 void vPortISRStartFirstTask( void );
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98 /*-----------------------------------------------------------*/
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100 void vPortISRStartFirstTask( void )
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102 /* Simply start the scheduler. This is included here as it can only be
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103 called from ARM mode. */
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104 portRESTORE_CONTEXT();
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106 /*-----------------------------------------------------------*/
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109 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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111 * When a context switch is performed from the task level the saved task
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112 * context is made to look as if it occurred from within the tick ISR. This
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113 * way the same restore context function can be used when restoring the context
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114 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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116 void vPortYieldProcessor( void )
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118 /* Within an IRQ ISR the link register has an offset from the true return
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119 address, but an SWI ISR does not. Add the offset manually so the same
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120 ISR return code can be used in both cases. */
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121 asm volatile ( "ADD LR, LR, #4" );
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123 /* Perform the context switch. First save the context of the current task. */
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124 portSAVE_CONTEXT();
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126 /* Find the highest priority task that is ready to run. */
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127 vTaskSwitchContext();
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129 /* Restore the context of the new task. */
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130 portRESTORE_CONTEXT();
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132 /*-----------------------------------------------------------*/
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135 * The ISR used for the scheduler tick.
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137 void vTickISR( void ) __attribute__((naked));
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138 void vTickISR( void )
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140 /* Save the context of the interrupted task. */
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141 portSAVE_CONTEXT();
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143 /* Increment the RTOS tick count, then look for the highest priority
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144 task that is ready to run. */
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145 vTaskIncrementTick();
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147 #if configUSE_PREEMPTION == 1
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148 vTaskSwitchContext();
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151 /* Ready for the next interrupt. */
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152 T0_IR = portTIMER_MATCH_ISR_BIT;
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153 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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155 /* Restore the context of the new task. */
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156 portRESTORE_CONTEXT();
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158 /*-----------------------------------------------------------*/
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161 * The interrupt management utilities can only be called from ARM mode. When
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162 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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163 * ensure a switch to ARM mode. When THUMB_INTERWORK is not defined then
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164 * the utilities are defined as macros in portmacro.h - as per other ports.
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166 #ifdef THUMB_INTERWORK
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168 void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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169 void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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171 void vPortDisableInterruptsFromThumb( void )
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174 "STMDB SP!, {R0} \n\t" /* Push R0. */
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175 "MRS R0, CPSR \n\t" /* Get CPSR. */
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176 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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177 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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178 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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179 "BX R14" ); /* Return back to thumb. */
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182 void vPortEnableInterruptsFromThumb( void )
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185 "STMDB SP!, {R0} \n\t" /* Push R0. */
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186 "MRS R0, CPSR \n\t" /* Get CPSR. */
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187 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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188 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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189 "LDMIA SP!, {R0} \n\t" /* Pop R0. */
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190 "BX R14" ); /* Return back to thumb. */
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193 #endif /* THUMB_INTERWORK */
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195 /* The code generated by the GCC compiler uses the stack in different ways at
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196 different optimisation levels. The interrupt flags can therefore not always
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197 be saved to the stack. Instead the critical section nesting level is stored
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198 in a variable, which is then saved as part of the stack context. */
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199 void vPortEnterCritical( void )
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201 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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203 "STMDB SP!, {R0} \n\t" /* Push R0. */
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204 "MRS R0, CPSR \n\t" /* Get CPSR. */
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205 "ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */
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206 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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207 "LDMIA SP!, {R0}" ); /* Pop R0. */
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209 /* Now interrupts are disabled ulCriticalNesting can be accessed
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210 directly. Increment ulCriticalNesting to keep a count of how many times
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211 portENTER_CRITICAL() has been called. */
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212 ulCriticalNesting++;
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215 void vPortExitCritical( void )
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217 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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219 /* Decrement the nesting count as we are leaving a critical section. */
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220 ulCriticalNesting--;
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222 /* If the nesting level has reached zero then interrupts should be
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224 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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226 /* Enable interrupts as per portEXIT_CRITICAL(). */
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228 "STMDB SP!, {R0} \n\t" /* Push R0. */
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229 "MRS R0, CPSR \n\t" /* Get CPSR. */
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230 "BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */
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231 "MSR CPSR, R0 \n\t" /* Write back modified value. */
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232 "LDMIA SP!, {R0}" ); /* Pop R0. */
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