git.sur5r.net Git - freertos/blob - Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2     FreeRTOS V6.1.0 - Copyright (C) 2010 Real Time Engineers Ltd.\r
   3 \r
   4     ***************************************************************************\r
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  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
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  37     License and the FreeRTOS license exception along with FreeRTOS; if not it \r
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  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
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  44     http://www.FreeRTOS.org - Documentation, latest information, license and\r
  45     contact details.\r
  46 \r
  47     http://www.SafeRTOS.com - A version that is certified for use in safety\r
  48     critical systems.\r
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  50     http://www.OpenRTOS.com - Commercial support, development, porting,\r
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  52 */\r
  53 \r
  54 /*-----------------------------------------------------------\r
  55  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  56  *----------------------------------------------------------*/\r
  57 \r
  58 /* Scheduler includes. */\r
  59 #include "FreeRTOS.h"\r
  60 #include "task.h"\r
  61 \r
  62 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is\r
  63 defined.  The value should also ensure backward compatibility.\r
  64 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  65 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  66         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  67 #endif\r
  68 \r
  69 /* Constants required to manipulate the NVIC. */\r
  70 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned long *) 0xe000e010 )\r
  71 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned long *) 0xe000e014 )\r
  72 #define portNVIC_INT_CTRL                       ( ( volatile unsigned long *) 0xe000ed04 )\r
  73 #define portNVIC_SYSPRI2                        ( ( volatile unsigned long *) 0xe000ed20 )\r
  74 #define portNVIC_SYSTICK_CLK            0x00000004\r
  75 #define portNVIC_SYSTICK_INT            0x00000002\r
  76 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  77 #define portNVIC_PENDSVSET                      0x10000000\r
  78 #define portNVIC_PENDSV_PRI                     ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
  79 #define portNVIC_SYSTICK_PRI            ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
  80 \r
  81 /* Constants required to set up the initial stack. */\r
  82 #define portINITIAL_XPSR                        ( 0x01000000 )\r
  83 \r
  84 /* The priority used by the kernel is assigned to a variable to make access\r
  85 from inline assembler easier. */\r
  86 const unsigned long ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
  87 \r
  88 /* Each task maintains its own interrupt status in the critical nesting\r
  89 variable. */\r
  90 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
  91 \r
  92 /*\r
  93  * Setup the timer to generate the tick interrupts.\r
  94  */\r
  95 static void prvSetupTimerInterrupt( void );\r
  96 \r
  97 /*\r
  98  * Exception handlers.\r
  99  */\r
 100 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
 101 void xPortSysTickHandler( void );\r
 102 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
 103 \r
 104 /*\r
 105  * Start first task is a separate function so it can be tested in isolation.\r
 106  */\r
 107 void vPortStartFirstTask( void ) __attribute__ (( naked ));\r
 108 \r
 109 /*-----------------------------------------------------------*/\r
 110 \r
 111 /*\r
 112  * See header file for description.\r
 113  */\r
 114 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 115 {\r
 116         /* Simulate the stack frame as it would be created by a context switch\r
 117         interrupt. */\r
 118         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 119         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 120         pxTopOfStack--;\r
 121         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 122         pxTopOfStack--;\r
 123         *pxTopOfStack = 0;      /* LR */\r
 124         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 125         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 126         pxTopOfStack -= 8;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 127 \r
 128         return pxTopOfStack;\r
 129 }\r
 130 /*-----------------------------------------------------------*/\r
 131 \r
 132 void vPortSVCHandler( void )\r
 133 {\r
 134         __asm volatile (\r
 135                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 136                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 137                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 138                                         "       ldmia r0!, {r4-r11}                             \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 139                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 140                                         "       mov r0, #0                                              \n"\r
 141                                         "       msr     basepri, r0                                     \n"\r
 142                                         "       orr r14, #0xd                                   \n"\r
 143                                         "       bx r14                                                  \n"\r
 144                                         "                                                                       \n"\r
 145                                         "       .align 2                                                \n"\r
 146                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 147                                 );\r
 148 }\r
 149 /*-----------------------------------------------------------*/\r
 150 \r
 151 void vPortStartFirstTask( void )\r
 152 {\r
 153         __asm volatile(\r
 154                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 155                                         " ldr r0, [r0]                  \n"\r
 156                                         " ldr r0, [r0]                  \n"\r
 157                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 158                                         " svc 0                                 \n" /* System call to start first task. */\r
 159                                 );\r
 160 }\r
 161 /*-----------------------------------------------------------*/\r
 162 \r
 163 /*\r
 164  * See header file for description.\r
 165  */\r
 166 portBASE_TYPE xPortStartScheduler( void )\r
 167 {\r
 168         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 169         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 170         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 171 \r
 172         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 173         here already. */\r
 174         prvSetupTimerInterrupt();\r
 175 \r
 176         /* Initialise the critical nesting count ready for the first task. */\r
 177         uxCriticalNesting = 0;\r
 178 \r
 179         /* Start the first task. */\r
 180         vPortStartFirstTask();\r
 181 \r
 182         /* Should not get here! */\r
 183         return 0;\r
 184 }\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 void vPortEndScheduler( void )\r
 188 {\r
 189         /* It is unlikely that the CM3 port will require this function as there\r
 190         is nothing to return to.  */\r
 191 }\r
 192 /*-----------------------------------------------------------*/\r
 193 \r
 194 void vPortYieldFromISR( void )\r
 195 {\r
 196         /* Set a PendSV to request a context switch. */\r
 197         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 198 }\r
 199 /*-----------------------------------------------------------*/\r
 200 \r
 201 void vPortEnterCritical( void )\r
 202 {\r
 203         portDISABLE_INTERRUPTS();\r
 204         uxCriticalNesting++;\r
 205 }\r
 206 /*-----------------------------------------------------------*/\r
 207 \r
 208 void vPortExitCritical( void )\r
 209 {\r
 210         uxCriticalNesting--;\r
 211         if( uxCriticalNesting == 0 )\r
 212         {\r
 213                 portENABLE_INTERRUPTS();\r
 214         }\r
 215 }\r
 216 /*-----------------------------------------------------------*/\r
 217 \r
 218 void xPortPendSVHandler( void )\r
 219 {\r
 220         /* This is a naked function. */\r
 221 \r
 222         __asm volatile\r
 223         (\r
 224         "       mrs r0, psp                                                     \n"\r
 225         "                                                                               \n"\r
 226         "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 227         "       ldr     r2, [r3]                                                \n"\r
 228         "                                                                               \n"\r
 229         "       stmdb r0!, {r4-r11}                                     \n" /* Save the remaining registers. */\r
 230         "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 231         "                                                                               \n"\r
 232         "       stmdb sp!, {r3, r14}                            \n"\r
 233         "       mov r0, %0                                                      \n"\r
 234         "       msr basepri, r0                                         \n"\r
 235         "       bl vTaskSwitchContext                           \n"\r
 236         "       mov r0, #0                                                      \n"\r
 237         "       msr basepri, r0                                         \n"\r
 238         "       ldmia sp!, {r3, r14}                            \n"\r
 239         "                                                                               \n"     /* Restore the context, including the critical nesting count. */\r
 240         "       ldr r1, [r3]                                            \n"\r
 241         "       ldr r0, [r1]                                            \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 242         "       ldmia r0!, {r4-r11}                                     \n" /* Pop the registers. */\r
 243         "       msr psp, r0                                                     \n"\r
 244         "       bx r14                                                          \n"\r
 245         "                                                                               \n"\r
 246         "       .align 2                                                        \n"\r
 247         "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 248         ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 249         );\r
 250 }\r
 251 /*-----------------------------------------------------------*/\r
 252 \r
 253 void xPortSysTickHandler( void )\r
 254 {\r
 255 unsigned long ulDummy;\r
 256 \r
 257         /* If using preemption, also force a context switch. */\r
 258         #if configUSE_PREEMPTION == 1\r
 259                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 260         #endif\r
 261 \r
 262         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 263         {\r
 264                 vTaskIncrementTick();\r
 265         }\r
 266         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 267 }\r
 268 /*-----------------------------------------------------------*/\r
 269 \r
 270 /*\r
 271  * Setup the systick timer to generate the tick interrupts at the required\r
 272  * frequency.\r
 273  */\r
 274 void prvSetupTimerInterrupt( void )\r
 275 {\r
 276         /* Configure SysTick to interrupt at the requested rate. */\r
 277         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 278         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 279 }\r
 280 /*-----------------------------------------------------------*/\r
 281 \r