git.sur5r.net Git - freertos/blob - Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2         FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.\r
   3 \r
   4         This file is part of the FreeRTOS.org distribution.\r
   5 \r
   6         FreeRTOS.org is free software; you can redistribute it and/or modify\r
   7         it under the terms of the GNU General Public License as published by\r
   8         the Free Software Foundation; either version 2 of the License, or\r
   9         (at your option) any later version.\r
  10 \r
  11         FreeRTOS.org is distributed in the hope that it will be useful,\r
  12         but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14         GNU General Public License for more details.\r
  15 \r
  16         You should have received a copy of the GNU General Public License\r
  17         along with FreeRTOS.org; if not, write to the Free Software\r
  18         Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
  19 \r
  20         A special exception to the GPL can be applied should you wish to distribute\r
  21         a combined work that includes FreeRTOS.org, without being obliged to provide\r
  22         the source code for any proprietary components.  See the licensing section \r
  23         of http://www.FreeRTOS.org for full details of how and when the exception\r
  24         can be applied.\r
  25 \r
  26     ***************************************************************************\r
  27     ***************************************************************************\r
  28     *                                                                         *\r
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  32     * expedite your project.                                                  *\r
  33     *                                                                         *\r
  34     ***************************************************************************\r
  35     ***************************************************************************\r
  36 \r
  37         Please ensure to read the configuration and relevant port sections of the\r
  38         online documentation.\r
  39 \r
  40         http://www.FreeRTOS.org - Documentation, latest information, license and \r
  41         contact details.\r
  42 \r
  43         http://www.SafeRTOS.com - A version that is certified for use in safety \r
  44         critical systems.\r
  45 \r
  46         http://www.OpenRTOS.com - Commercial support, development, porting, \r
  47         licensing and training services.\r
  48 */\r
  49 \r
  50 /*-----------------------------------------------------------\r
  51  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  52  *----------------------------------------------------------*/\r
  53 \r
  54 /* Scheduler includes. */\r
  55 #include "FreeRTOS.h"\r
  56 #include "task.h"\r
  57 \r
  58 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is \r
  59 defined.  The value should also ensure backward compatibility.  \r
  60 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  61 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  62         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  63 #endif\r
  64 \r
  65 /* Constants required to manipulate the NVIC. */\r
  66 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned portLONG *) 0xe000e010 )\r
  67 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned portLONG *) 0xe000e014 )\r
  68 #define portNVIC_INT_CTRL                       ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
  69 #define portNVIC_SYSPRI2                        ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
  70 #define portNVIC_SYSTICK_CLK            0x00000004\r
  71 #define portNVIC_SYSTICK_INT            0x00000002\r
  72 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  73 #define portNVIC_PENDSVSET                      0x10000000\r
  74 #define portNVIC_PENDSV_PRI                     ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
  75 #define portNVIC_SYSTICK_PRI            ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
  76 \r
  77 /* Constants required to set up the initial stack. */\r
  78 #define portINITIAL_XPSR                        ( 0x01000000 )\r
  79 \r
  80 /* The priority used by the kernel is assigned to a variable to make access\r
  81 from inline assembler easier. */\r
  82 const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
  83 \r
  84 /* Each task maintains its own interrupt status in the critical nesting\r
  85 variable. */\r
  86 unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
  87 \r
  88 /* \r
  89  * Setup the timer to generate the tick interrupts.\r
  90  */\r
  91 static void prvSetupTimerInterrupt( void );\r
  92 \r
  93 /*\r
  94  * Exception handlers.\r
  95  */\r
  96 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
  97 void xPortSysTickHandler( void );\r
  98 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
  99 \r
 100 /*\r
 101  * Start first task is a separate function so it can be tested in isolation.\r
 102  */\r
 103 void vPortStartFirstTask( unsigned long ulValue ) __attribute__ (( naked ));\r
 104 \r
 105 /*-----------------------------------------------------------*/\r
 106 \r
 107 /* \r
 108  * See header file for description. \r
 109  */\r
 110 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 111 {\r
 112         /* Simulate the stack frame as it would be created by a context switch\r
 113         interrupt. */\r
 114         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 115         pxTopOfStack--;\r
 116         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 117         pxTopOfStack--;\r
 118         *pxTopOfStack = 0;      /* LR */\r
 119         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 120         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 121         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 122         *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
 123 \r
 124         return pxTopOfStack;\r
 125 }\r
 126 /*-----------------------------------------------------------*/\r
 127 \r
 128 void vPortSVCHandler( void )\r
 129 {\r
 130         asm volatile (\r
 131                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 132                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 133                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 134                                         "       ldmia r0!, {r1, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 135                                         "       ldr r2, uxCriticalNestingConst2 \n" /* Restore the critical nesting count used by the task. */\r
 136                                         "       str r1, [r2]                                    \n"\r
 137                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 138                                         "       mov r0, #0                                              \n"\r
 139                                         "       msr     basepri, r0                                     \n"                     \r
 140                                         "       orr r14, #0xd                                   \n"\r
 141                                         "       bx r14                                                  \n"\r
 142                                         "                                                                       \n"\r
 143                                         "       .align 2                                                \n"\r
 144                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 145                                         "uxCriticalNestingConst2: .word uxCriticalNesting       \n"\r
 146                                 );\r
 147 }\r
 148 /*-----------------------------------------------------------*/\r
 149 \r
 150 void vPortStartFirstTask( unsigned long ulValue )\r
 151 {\r
 152         /* ulValue is used from the asm code, but the compiler does not know\r
 153         this so remove the warning. */\r
 154         ( void ) ulValue;\r
 155         \r
 156         asm volatile( \r
 157                                         "       msr msp, r0                                                             \n" /* Set the msp back to the start of the stack. */\r
 158                                         "       svc 0                                                                   \n" /* System call to start first task. */\r
 159                                 );\r
 160 }\r
 161 /*-----------------------------------------------------------*/\r
 162 \r
 163 /* \r
 164  * See header file for description. \r
 165  */\r
 166 portBASE_TYPE xPortStartScheduler( void )\r
 167 {\r
 168         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 169         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 170         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 171 \r
 172         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 173         here already. */\r
 174         prvSetupTimerInterrupt();\r
 175         \r
 176         /* Start the first task. */\r
 177         vPortStartFirstTask( *((unsigned portLONG *) 0 ) );\r
 178 \r
 179         /* Should not get here! */\r
 180         return 0;\r
 181 }\r
 182 /*-----------------------------------------------------------*/\r
 183 \r
 184 void vPortEndScheduler( void )\r
 185 {\r
 186         /* It is unlikely that the CM3 port will require this function as there\r
 187         is nothing to return to.  */\r
 188 }\r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 void vPortYieldFromISR( void )\r
 192 {\r
 193         /* Set a PendSV to request a context switch. */\r
 194         *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
 195 \r
 196         /* This function is also called in response to a Yield(), so we want\r
 197         the yield to occur immediately. */\r
 198         portENABLE_INTERRUPTS();\r
 199 }\r
 200 /*-----------------------------------------------------------*/\r
 201 \r
 202 void vPortEnterCritical( void )\r
 203 {\r
 204         portDISABLE_INTERRUPTS();\r
 205         uxCriticalNesting++;\r
 206 }\r
 207 /*-----------------------------------------------------------*/\r
 208 \r
 209 void vPortExitCritical( void )\r
 210 {\r
 211         uxCriticalNesting--;\r
 212         if( uxCriticalNesting == 0 )\r
 213         {\r
 214                 portENABLE_INTERRUPTS();\r
 215         }\r
 216 }\r
 217 /*-----------------------------------------------------------*/\r
 218 \r
 219 void xPortPendSVHandler( void )\r
 220 {\r
 221         /* This is a naked function. */\r
 222 \r
 223         __asm volatile\r
 224         ( \r
 225         "       mrs r0, psp                                             \n" \r
 226         "                                                                       \n"\r
 227         "       ldr     r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */\r
 228         "       ldr     r2, [r3]                                        \n"     \r
 229         "                                                                       \n"     \r
 230         "       ldr r1, uxCriticalNestingConst  \n" /* Save the remaining registers and the critical nesting count onto the task stack. */\r
 231         "       ldr r1, [r1]                                    \n"\r
 232         "       stmdb r0!, {r1,r4-r11}                  \n"\r
 233         "       str r0, [r2]                                    \n" /* Save the new top of stack into the first member of the TCB. */\r
 234         "                                                                       \n"\r
 235         "       stmdb sp!, {r3, r14}                    \n" \r
 236         "       bl vTaskSwitchContext                   \n"\r
 237         "       ldmia sp!, {r3, r14}                    \n"\r
 238         "                                                                       \n"     /* Restore the context, including the critical nesting count. */\r
 239         "       ldr r1, [r3]                                    \n" \r
 240         "       ldr r2, uxCriticalNestingConst  \n"\r
 241         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 242         "       ldmia r0!, {r1, r4-r11}                 \n" /* Pop the registers and the critical nesting count. */\r
 243         "       str r1, [r2]                                    \n" /* Save the new critical nesting value into ulCriticalNesting. */ \r
 244         "       msr psp, r0                                             \n" \r
 245         "       orr r14, #0xd                                   \n"\r
 246         "                                                                       \n"     /* Exit with interrupts in the state required by the task. */   \r
 247         "       cbnz r1, sv_disable_interrupts  \n" /* If the nesting count is greater than 0 we need to exit with interrupts masked. */\r
 248         "       bx r14                                                  \n"\r
 249         "                                                                       \n"\r
 250         "sv_disable_interrupts:                         \n" \r
 251         "       ldr r1, =ulKernelPriority               \n"\r
 252         "       ldr r1, [r1]                                    \n"\r
 253         "       msr     basepri, r1                                     \n"\r
 254         "       bx r14                                                  \n"\r
 255         "                                                                       \n"\r
 256         "       .align 2                                                \n"\r
 257         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 258         "uxCriticalNestingConst: .word uxCriticalNesting        \n"\r
 259         );\r
 260 }\r
 261 /*-----------------------------------------------------------*/\r
 262 \r
 263 void xPortSysTickHandler( void )\r
 264 {\r
 265         /* If using preemption, also force a context switch. */\r
 266         #if configUSE_PREEMPTION == 1\r
 267                 *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;     \r
 268         #endif\r
 269 \r
 270         vTaskIncrementTick();\r
 271 }\r
 272 /*-----------------------------------------------------------*/\r
 273 \r
 274 /*\r
 275  * Setup the systick timer to generate the tick interrupts at the required\r
 276  * frequency.\r
 277  */\r
 278 void prvSetupTimerInterrupt( void )\r
 279 {\r
 280         /* Configure SysTick to interrupt at the requested rate. */\r
 281         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 282         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 283 }\r
 284 /*-----------------------------------------------------------*/\r
 285 \r