git.sur5r.net Git - freertos/blob - Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2         FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.\r
   3 \r
   4         This file is part of the FreeRTOS.org distribution.\r
   5 \r
   6         FreeRTOS.org is free software; you can redistribute it and/or modify\r
   7         it under the terms of the GNU General Public License as published by\r
   8         the Free Software Foundation; either version 2 of the License, or\r
   9         (at your option) any later version.\r
  10 \r
  11         FreeRTOS.org is distributed in the hope that it will be useful,\r
  12         but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14         GNU General Public License for more details.\r
  15 \r
  16         You should have received a copy of the GNU General Public License\r
  17         along with FreeRTOS.org; if not, write to the Free Software\r
  18         Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
  19 \r
  20         A special exception to the GPL can be applied should you wish to distribute\r
  21         a combined work that includes FreeRTOS.org, without being obliged to provide\r
  22         the source code for any proprietary components.  See the licensing section \r
  23         of http://www.FreeRTOS.org for full details of how and when the exception\r
  24         can be applied.\r
  25 \r
  26         ***************************************************************************\r
  27         See http://www.FreeRTOS.org for documentation, latest information, license \r
  28         and contact details.  Please ensure to read the configuration and relevant \r
  29         port sections of the online documentation.\r
  30         ***************************************************************************\r
  31 */\r
  32 \r
  33 /*\r
  34         Changes between V4.0.0 and V4.0.1\r
  35 \r
  36         + Reduced the code used to setup the initial stack frame.\r
  37         + The kernel no longer has to install or handle the fault interrupt.\r
  38 */\r
  39 \r
  40 \r
  41 /*-----------------------------------------------------------\r
  42  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  43  *----------------------------------------------------------*/\r
  44 \r
  45 /* Scheduler includes. */\r
  46 #include "FreeRTOS.h"\r
  47 #include "task.h"\r
  48 \r
  49 /* Constants required to manipulate the NVIC. */\r
  50 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned portLONG *) 0xe000e010 )\r
  51 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned portLONG *) 0xe000e014 )\r
  52 #define portNVIC_INT_CTRL                       ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
  53 #define portNVIC_SYSPRI2                        ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
  54 #define portNVIC_SYSPRI1                        ( ( volatile unsigned portLONG *) 0xe000ed1c )\r
  55 #define portNVIC_SYSTICK_CLK            0x00000004\r
  56 #define portNVIC_SYSTICK_INT            0x00000002\r
  57 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  58 #define portNVIC_PENDSVSET                      0x10000000\r
  59 #define portNVIC_PENDSV_PRI                     0x00ff0000\r
  60 #define portNVIC_SVCALL_PRI                     0xff000000\r
  61 #define portNVIC_SYSTICK_PRI            0xff000000\r
  62 \r
  63 /* Constants required to set up the initial stack. */\r
  64 #define portINITIAL_XPSR                        ( 0x01000000 )\r
  65 \r
  66 /* Each task maintains its own interrupt status in the critical nesting\r
  67 variable. */\r
  68 unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
  69 \r
  70 /* \r
  71  * Setup the timer to generate the tick interrupts.\r
  72  */\r
  73 static void prvSetupTimerInterrupt( void );\r
  74 \r
  75 /*\r
  76  * Exception handlers.\r
  77  */\r
  78 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
  79 void xPortSysTickHandler( void ) __attribute__ (( naked ));\r
  80 \r
  81 /*\r
  82  * Set the MSP/PSP to a known value.\r
  83  */\r
  84 void prvSetMSP( unsigned long ulValue ) __attribute__ (( naked ));\r
  85 void prvSetPSP( unsigned long ulValue ) __attribute__ (( naked )); \r
  86 \r
  87 /*-----------------------------------------------------------*/\r
  88 \r
  89 /* \r
  90  * See header file for description. \r
  91  */\r
  92 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
  93 {\r
  94         /* Simulate the stack frame as it would be created by a context switch\r
  95         interrupt. */\r
  96         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
  97         pxTopOfStack--;\r
  98         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
  99         pxTopOfStack--;\r
 100         *pxTopOfStack = 0xfffffffd;     /* LR */\r
 101         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 102         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 103         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 104         *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
 105 \r
 106         return pxTopOfStack;\r
 107 }\r
 108 /*-----------------------------------------------------------*/\r
 109 \r
 110 void prvSetPSP( unsigned long ulValue )\r
 111 {\r
 112         asm volatile( "msr psp, r0" );\r
 113         asm volatile( "bx lr" );\r
 114 }\r
 115 /*-----------------------------------------------------------*/\r
 116 \r
 117 void prvSetMSP( unsigned long ulValue )\r
 118 {\r
 119         asm volatile( "msr msp, r0" );\r
 120         asm volatile( "bx lr" );\r
 121 }\r
 122 /*-----------------------------------------------------------*/\r
 123 \r
 124 /* \r
 125  * See header file for description. \r
 126  */\r
 127 portBASE_TYPE xPortStartScheduler( void )\r
 128 {\r
 129         /* Make PendSV, CallSV and SysTick the lowest priority interrupts. */\r
 130         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 131         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 132 \r
 133         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 134         here already. */\r
 135         prvSetupTimerInterrupt();\r
 136         \r
 137         /* Start the first task. */\r
 138         prvSetPSP( 0 );\r
 139         prvSetMSP( *((unsigned portLONG *) 0 ) );\r
 140         *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
 141 \r
 142         /* Enable interrupts */\r
 143         portENABLE_INTERRUPTS();\r
 144 \r
 145         /* Should not get here! */\r
 146         return 0;\r
 147 }\r
 148 /*-----------------------------------------------------------*/\r
 149 \r
 150 void vPortEndScheduler( void )\r
 151 {\r
 152         /* It is unlikely that the CM3 port will require this function as there\r
 153         is nothing to return to.  */\r
 154 }\r
 155 /*-----------------------------------------------------------*/\r
 156 \r
 157 void vPortYieldFromISR( void )\r
 158 {\r
 159         /* Set a PendSV to request a context switch. */\r
 160         *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
 161 \r
 162         /* This function is also called in response to a Yield(), so we want\r
 163         the yield to occur immediately. */\r
 164         portENABLE_INTERRUPTS();\r
 165 }\r
 166 /*-----------------------------------------------------------*/\r
 167 \r
 168 void vPortEnterCritical( void )\r
 169 {\r
 170         portDISABLE_INTERRUPTS();\r
 171         uxCriticalNesting++;\r
 172 }\r
 173 /*-----------------------------------------------------------*/\r
 174 \r
 175 void vPortExitCritical( void )\r
 176 {\r
 177         uxCriticalNesting--;\r
 178         if( uxCriticalNesting == 0 )\r
 179         {\r
 180                 portENABLE_INTERRUPTS();\r
 181         }\r
 182 }\r
 183 /*-----------------------------------------------------------*/\r
 184 \r
 185 void xPortPendSVHandler( void )\r
 186 {\r
 187         /* Start first task if the stack has not yet been setup. */\r
 188         __asm volatile\r
 189         ( \r
 190         "       mrs r0, psp                                             \n"\r
 191         "       cbz r0, no_save                                 \n"\r
 192         "                                                                       \n"     /* Save the context into the TCB. */                                    \r
 193         "       sub r0, #0x20                                   \n"\r
 194         "       stm r0, {r4-r11}                                \n"\r
 195         "       nop                                                             \n"\r
 196         "       sub r0, #0x04                                   \n"\r
 197         "       ldr r1, uxCriticalNestingConst  \n"\r
 198         "       ldr r1, [r1]                                    \n"\r
 199         "       stm r0, {r1}                                    \n"\r
 200         "       ldr r1, pxCurrentTCBConst               \n"\r
 201         "       ldr r1, [r1]                                    \n"\r
 202         "       str r0, [r1]                                    \n"\r
 203         "                                                                       \n"\r
 204         "no_save:\n"    \r
 205         "       ldr r0, vTaskSwitchContextConst \n"     /* Find the task to execute. */\r
 206         "       push {r14}                                              \n"\r
 207         "       cpsid i                                                 \n"\r
 208         "       blx r0                                                  \n"\r
 209         "       cpsie i                                                 \n"\r
 210         "       pop {r14}                                               \n"\r
 211         "                                                                       \n"     /* Restore the context. */      \r
 212         "       ldr r1, pxCurrentTCBConst               \n"\r
 213         "       ldr r1, [r1]                                    \n"\r
 214         "       ldr r0, [r1]                                    \n"\r
 215         "       ldm r0, {r1, r4-r11}                    \n"\r
 216         "       nop                                                             \n"\r
 217         "       ldr r2, uxCriticalNestingConst  \n"\r
 218         "       str r1, [r2]                                    \n"\r
 219         "       add r0, #0x24                                   \n"\r
 220         "       msr psp, r0                                             \n"\r
 221         "       orr r14, #0xd                                   \n"\r
 222         "                                                                       \n"     /* Exit with interrupts in the state required by the task. */   \r
 223         "       cbnz r1, sv_disable_interrupts  \n"\r
 224         "       bx r14                                                  \n"\r
 225         "                                                                       \n"\r
 226         "sv_disable_interrupts:                         \n"\r
 227         "       cpsid i                                                 \n"\r
 228         "       bx r14                                                  \n"\r
 229         "                                                                       \n"\r
 230         "       .align 2                                                \n"\r
 231         "vTaskSwitchContextConst: .word vTaskSwitchContext      \n"\r
 232         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 233         "uxCriticalNestingConst: .word uxCriticalNesting        \n"\r
 234         );\r
 235 }\r
 236 /*-----------------------------------------------------------*/\r
 237 \r
 238 void xPortSysTickHandler( void )\r
 239 {\r
 240         extern void vTaskIncrementTick( void );\r
 241         extern void vPortYieldFromISR( void );\r
 242 \r
 243         /* Call the scheduler tick function. */\r
 244         __asm volatile\r
 245         ( \r
 246         "       ldr r0, vTaskIncrementTickConst         \n"\r
 247         "       push {r14}                                                      \n"\r
 248         "       cpsid i                                                         \n"\r
 249         "       blx r0                                                          \n"\r
 250         "       cpsie i                                                         \n"\r
 251         "       pop {r14}" \r
 252         );\r
 253 \r
 254         /* If using preemption, also force a context switch. */\r
 255         #if configUSE_PREEMPTION == 1\r
 256         __asm volatile\r
 257         ( \r
 258         "       push {r14}                                                      \n"\r
 259         "       ldr r0, vPortYieldFromISRConst2         \n"\r
 260         "       blx r0                                                          \n"\r
 261         "       pop {r14}" \r
 262         );\r
 263         #endif\r
 264 \r
 265         /* Exit with interrupts in the correct state. */\r
 266         __asm volatile\r
 267         (\r
 268         "    ldr r2, uxCriticalNestingConst2    \n" \r
 269         "    ldr r2, [r2]                                               \n"\r
 270         "    cbnz r2, tick_disable_interrupts   \n"\r
 271         "    bx r14" \r
 272         );\r
 273 \r
 274    __asm volatile\r
 275    (\r
 276         "tick_disable_interrupts:                               \n"\r
 277         "    cpsid i                                                    \n"\r
 278         "    bx r14                                                             \n"\r
 279         "                                                                               \n"\r
 280         "       .align 2                                                        \n"\r
 281         "vPortYieldFromISRConst2: .word vPortYieldFromISR\n"\r
 282         "vTaskIncrementTickConst: .word vTaskIncrementTick\n" \r
 283         "uxCriticalNestingConst2: .word uxCriticalNesting"\r
 284         );\r
 285 }\r
 286 /*-----------------------------------------------------------*/\r
 287 \r
 288 /*\r
 289  * Setup the systick timer to generate the tick interrupts at the required\r
 290  * frequency.\r
 291  */\r
 292 void prvSetupTimerInterrupt( void )\r
 293 {\r
 294         /* Configure SysTick to interrupt at the requested rate. */\r
 295         *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
 296         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 297 }\r
 298 \r
 299 \r