git.sur5r.net Git - freertos/blob - Source/portable/GCC/ARM_CM3/port.c

   1 /*\r
   2         FreeRTOS.org V4.7.2 - Copyright (C) 2003-2008 Richard Barry.\r
   3 \r
   4         This file is part of the FreeRTOS.org distribution.\r
   5 \r
   6         FreeRTOS.org is free software; you can redistribute it and/or modify\r
   7         it under the terms of the GNU General Public License as published by\r
   8         the Free Software Foundation; either version 2 of the License, or\r
   9         (at your option) any later version.\r
  10 \r
  11         FreeRTOS.org is distributed in the hope that it will be useful,\r
  12         but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14         GNU General Public License for more details.\r
  15 \r
  16         You should have received a copy of the GNU General Public License\r
  17         along with FreeRTOS.org; if not, write to the Free Software\r
  18         Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
  19 \r
  20         A special exception to the GPL can be applied should you wish to distribute\r
  21         a combined work that includes FreeRTOS.org, without being obliged to provide\r
  22         the source code for any proprietary components.  See the licensing section \r
  23         of http://www.FreeRTOS.org for full details of how and when the exception\r
  24         can be applied.\r
  25 \r
  26         ***************************************************************************\r
  27 \r
  28         Please ensure to read the configuration and relevant port sections of the \r
  29         online documentation.\r
  30 \r
  31         +++ http://www.FreeRTOS.org +++\r
  32         Documentation, latest information, license and contact details.  \r
  33 \r
  34         +++ http://www.SafeRTOS.com +++\r
  35         A version that is certified for use in safety critical systems.\r
  36 \r
  37         +++ http://www.OpenRTOS.com +++\r
  38         Commercial support, development, porting, licensing and training services.\r
  39 \r
  40         ***************************************************************************\r
  41 */\r
  42 \r
  43 /*-----------------------------------------------------------\r
  44  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  45  *----------------------------------------------------------*/\r
  46 \r
  47 /* Scheduler includes. */\r
  48 #include "FreeRTOS.h"\r
  49 #include "task.h"\r
  50 \r
  51 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is \r
  52 defined.  The value should also ensure backward compatibility.  \r
  53 FreeRTOS.org versions prior to V4.4.0 did not include this definition. */\r
  54 #ifndef configKERNEL_INTERRUPT_PRIORITY\r
  55         #define configKERNEL_INTERRUPT_PRIORITY 255\r
  56 #endif\r
  57 \r
  58 /* Constants required to manipulate the NVIC. */\r
  59 #define portNVIC_SYSTICK_CTRL           ( ( volatile unsigned portLONG *) 0xe000e010 )\r
  60 #define portNVIC_SYSTICK_LOAD           ( ( volatile unsigned portLONG *) 0xe000e014 )\r
  61 #define portNVIC_INT_CTRL                       ( ( volatile unsigned portLONG *) 0xe000ed04 )\r
  62 #define portNVIC_SYSPRI2                        ( ( volatile unsigned portLONG *) 0xe000ed20 )\r
  63 #define portNVIC_SYSTICK_CLK            0x00000004\r
  64 #define portNVIC_SYSTICK_INT            0x00000002\r
  65 #define portNVIC_SYSTICK_ENABLE         0x00000001\r
  66 #define portNVIC_PENDSVSET                      0x10000000\r
  67 #define portNVIC_PENDSV_PRI                     ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )\r
  68 #define portNVIC_SYSTICK_PRI            ( ( ( unsigned portLONG ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )\r
  69 \r
  70 /* Constants required to set up the initial stack. */\r
  71 #define portINITIAL_XPSR                        ( 0x01000000 )\r
  72 \r
  73 /* The priority used by the kernel is assigned to a variable to make access\r
  74 from inline assembler easier. */\r
  75 const unsigned portLONG ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;\r
  76 \r
  77 /* Each task maintains its own interrupt status in the critical nesting\r
  78 variable. */\r
  79 unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
  80 \r
  81 /* \r
  82  * Setup the timer to generate the tick interrupts.\r
  83  */\r
  84 static void prvSetupTimerInterrupt( void );\r
  85 \r
  86 /*\r
  87  * Exception handlers.\r
  88  */\r
  89 void xPortPendSVHandler( void ) __attribute__ (( naked ));\r
  90 void xPortSysTickHandler( void );\r
  91 void vPortSVCHandler( void ) __attribute__ (( naked ));\r
  92 \r
  93 /*\r
  94  * Start first task is a separate function so it can be tested in isolation.\r
  95  */\r
  96 void vPortStartFirstTask( unsigned long ulValue ) __attribute__ (( naked ));\r
  97 \r
  98 /*-----------------------------------------------------------*/\r
  99 \r
 100 /* \r
 101  * See header file for description. \r
 102  */\r
 103 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 104 {\r
 105         /* Simulate the stack frame as it would be created by a context switch\r
 106         interrupt. */\r
 107         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 108         pxTopOfStack--;\r
 109         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 110         pxTopOfStack--;\r
 111         *pxTopOfStack = 0;      /* LR */\r
 112         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 113         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 114         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 115         *pxTopOfStack = 0x00000000; /* uxCriticalNesting. */\r
 116 \r
 117         return pxTopOfStack;\r
 118 }\r
 119 /*-----------------------------------------------------------*/\r
 120 \r
 121 void vPortSVCHandler( void )\r
 122 {\r
 123         asm volatile (\r
 124                                         "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 125                                         "       ldr r1, [r3]                                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\r
 126                                         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 127                                         "       ldmia r0!, {r1, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\r
 128                                         "       ldr r2, uxCriticalNestingConst2 \n" /* Restore the critical nesting count used by the task. */\r
 129                                         "       str r1, [r2]                                    \n"\r
 130                                         "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 131                                         "       orr r14, #0xd                                   \n"\r
 132                                         "       bx r14                                                  \n"\r
 133                                         "                                                                       \n"\r
 134                                         "       .align 2                                                \n"\r
 135                                         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 136                                         "uxCriticalNestingConst2: .word uxCriticalNesting       \n"\r
 137                                 );\r
 138 }\r
 139 /*-----------------------------------------------------------*/\r
 140 \r
 141 void vPortStartFirstTask( unsigned long ulValue )\r
 142 {\r
 143         /* ulValue is used from the asm code, but the compiler does not know\r
 144         this so remove the warning. */\r
 145         ( void ) ulValue;\r
 146         \r
 147         asm volatile( \r
 148                                         "       msr msp, r0                                                             \n" /* Set the msp back to the start of the stack. */\r
 149                                         "       svc 0                                                                   \n" /* System call to start first task. */\r
 150                                 );\r
 151 }\r
 152 /*-----------------------------------------------------------*/\r
 153 \r
 154 /* \r
 155  * See header file for description. \r
 156  */\r
 157 portBASE_TYPE xPortStartScheduler( void )\r
 158 {\r
 159         /* Make PendSV, CallSV and SysTick the same priroity as the kernel. */\r
 160         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 161         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 162 \r
 163         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 164         here already. */\r
 165         prvSetupTimerInterrupt();\r
 166         \r
 167         /* Start the first task. */\r
 168         vPortStartFirstTask( *((unsigned portLONG *) 0 ) );\r
 169 \r
 170         /* Should not get here! */\r
 171         return 0;\r
 172 }\r
 173 /*-----------------------------------------------------------*/\r
 174 \r
 175 void vPortEndScheduler( void )\r
 176 {\r
 177         /* It is unlikely that the CM3 port will require this function as there\r
 178         is nothing to return to.  */\r
 179 }\r
 180 /*-----------------------------------------------------------*/\r
 181 \r
 182 void vPortYieldFromISR( void )\r
 183 {\r
 184         /* Set a PendSV to request a context switch. */\r
 185         *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;\r
 186 \r
 187         /* This function is also called in response to a Yield(), so we want\r
 188         the yield to occur immediately. */\r
 189         portENABLE_INTERRUPTS();\r
 190 }\r
 191 /*-----------------------------------------------------------*/\r
 192 \r
 193 void vPortEnterCritical( void )\r
 194 {\r
 195         portDISABLE_INTERRUPTS();\r
 196         uxCriticalNesting++;\r
 197 }\r
 198 /*-----------------------------------------------------------*/\r
 199 \r
 200 void vPortExitCritical( void )\r
 201 {\r
 202         uxCriticalNesting--;\r
 203         if( uxCriticalNesting == 0 )\r
 204         {\r
 205                 portENABLE_INTERRUPTS();\r
 206         }\r
 207 }\r
 208 /*-----------------------------------------------------------*/\r
 209 \r
 210 void xPortPendSVHandler( void )\r
 211 {\r
 212         /* This is a naked function. */\r
 213 \r
 214         __asm volatile\r
 215         ( \r
 216         "       mrs r0, psp                                             \n" \r
 217         "                                                                       \n"\r
 218         "       ldr     r3, pxCurrentTCBConst           \n" /* Get the location of the current TCB. */\r
 219         "       ldr     r2, [r3]                                        \n"     \r
 220         "                                                                       \n"     \r
 221         "       ldr r1, uxCriticalNestingConst  \n" /* Save the remaining registers and the critical nesting count onto the task stack. */\r
 222         "       ldr r1, [r1]                                    \n"\r
 223         "       stmdb r0!, {r1,r4-r11}                  \n"\r
 224         "       str r0, [r2]                                    \n" /* Save the new top of stack into the first member of the TCB. */\r
 225         "                                                                       \n"\r
 226         "       stmdb sp!, {r3, r14}                    \n" \r
 227         "       bl vTaskSwitchContext                   \n"\r
 228         "       ldmia sp!, {r3, r14}                    \n"\r
 229         "                                                                       \n"     /* Restore the context, including the critical nesting count. */\r
 230         "       ldr r1, [r3]                                    \n" \r
 231         "       ldr r2, uxCriticalNestingConst  \n"\r
 232         "       ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. */\r
 233         "       ldmia r0!, {r1, r4-r11}                 \n" /* Pop the registers and the critical nesting count. */\r
 234         "       str r1, [r2]                                    \n" /* Save the new critical nesting value into ulCriticalNesting. */ \r
 235         "       msr psp, r0                                             \n" \r
 236         "       orr r14, #0xd                                   \n"\r
 237         "                                                                       \n"     /* Exit with interrupts in the state required by the task. */   \r
 238         "       cbnz r1, sv_disable_interrupts  \n" /* If the nesting count is greater than 0 we need to exit with interrupts masked. */\r
 239         "       bx r14                                                  \n"\r
 240         "                                                                       \n"\r
 241         "sv_disable_interrupts:                         \n" \r
 242         "       ldr r1, =ulKernelPriority               \n"\r
 243         "       ldr r1, [r1]                                    \n"\r
 244         "       msr     basepri, r1                                     \n"\r
 245         "       bx r14                                                  \n"\r
 246         "                                                                       \n"\r
 247         "       .align 2                                                \n"\r
 248         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 249         "uxCriticalNestingConst: .word uxCriticalNesting        \n"\r
 250         );\r
 251 }\r
 252 /*-----------------------------------------------------------*/\r
 253 \r
 254 void xPortSysTickHandler( void )\r
 255 {\r
 256         vTaskIncrementTick();\r
 257         \r
 258         /* If using preemption, also force a context switch. */\r
 259         #if configUSE_PREEMPTION == 1\r
 260                 *(portNVIC_INT_CTRL) |= portNVIC_PENDSVSET;     \r
 261         #endif\r
 262 }\r
 263 /*-----------------------------------------------------------*/\r
 264 \r
 265 /*\r
 266  * Setup the systick timer to generate the tick interrupts at the required\r
 267  * frequency.\r
 268  */\r
 269 void prvSetupTimerInterrupt( void )\r
 270 {\r
 271         /* Configure SysTick to interrupt at the requested rate. */\r
 272         *(portNVIC_SYSTICK_LOAD) = configCPU_CLOCK_HZ / configTICK_RATE_HZ;\r
 273         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 274 }\r
 275 /*-----------------------------------------------------------*/\r
 276 \r