git.sur5r.net Git - freertos/blob - Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.\r
   3 \r
   4     ***************************************************************************\r
   5     *                                                                         *\r
   6     * If you are:                                                             *\r
   7     *                                                                         *\r
   8     *    + New to FreeRTOS,                                                   *\r
   9     *    + Wanting to learn FreeRTOS or multitasking in general quickly       *\r
  10     *    + Looking for basic training,                                        *\r
  11     *    + Wanting to improve your FreeRTOS skills and productivity           *\r
  12     *                                                                         *\r
  13     * then take a look at the FreeRTOS eBook                                  *\r
  14     *                                                                         *\r
  15     *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *\r
  16     *                  http://www.FreeRTOS.org/Documentation                  *\r
  17     *                                                                         *\r
  18     * A pdf reference manual is also available.  Both are usually delivered   *\r
  19     * to your inbox within 20 minutes to two hours when purchased between 8am *\r
  20     * and 8pm GMT (although please allow up to 24 hours in case of            *\r
  21     * exceptional circumstances).  Thank you for your support!                *\r
  22     *                                                                         *\r
  23     ***************************************************************************\r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     ***NOTE*** The exception to the GPL is included to allow you to distribute\r
  31     a combined work that includes FreeRTOS without being obliged to provide the\r
  32     source code for proprietary components outside of the FreeRTOS kernel.\r
  33     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT\r
  34     ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  35     FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public \r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it \r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained \r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43 \r
  44     http://www.FreeRTOS.org - Documentation, latest information, license and\r
  45     contact details.\r
  46 \r
  47     http://www.SafeRTOS.com - A version that is certified for use in safety\r
  48     critical systems.\r
  49 \r
  50     http://www.OpenRTOS.com - Commercial support, development, porting,\r
  51     licensing and training services.\r
  52 */\r
  53 \r
  54 /*-----------------------------------------------------------\r
  55  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  56  *----------------------------------------------------------*/\r
  57 \r
  58 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  59 all the API functions to use the MPU wrappers.  That should only be done when\r
  60 task.h is included from an application file. */\r
  61 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  62 \r
  63 /* Scheduler includes. */\r
  64 #include "FreeRTOS.h"\r
  65 #include "task.h"\r
  66 #include "queue.h"\r
  67 \r
  68 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  69 \r
  70 /* Constants required to access and manipulate the NVIC. */\r
  71 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile unsigned long * ) 0xe000e010 )\r
  72 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile unsigned long * ) 0xe000e014 )\r
  73 #define portNVIC_SYSPRI2                                                ( ( volatile unsigned long * ) 0xe000ed20 )\r
  74 #define portNVIC_SYSPRI1                                                ( ( volatile unsigned long * ) 0xe000ed1c )\r
  75 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile unsigned long * ) 0xe000ed24 )\r
  76 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  77 \r
  78 /* Constants required to access and manipulate the MPU. */\r
  79 #define portMPU_TYPE                                                    ( ( volatile unsigned long * ) 0xe000ed90 )\r
  80 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile unsigned long * ) 0xe000ed9C )\r
  81 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile unsigned long * ) 0xe000edA0 )\r
  82 #define portMPU_CTRL                                                    ( ( volatile unsigned long * ) 0xe000ed94 )\r
  83 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  84 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  85 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  86 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  87 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  88 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  89 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  90 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  91 \r
  92 /* Constants required to access and manipulate the SysTick. */\r
  93 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
  94 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  95 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  96 #define portNVIC_PENDSV_PRI                                             ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  97 #define portNVIC_SYSTICK_PRI                                    ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  98 #define portNVIC_SVC_PRI                                                ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  99 \r
 100 /* Constants required to set up the initial stack. */\r
 101 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 102 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 103 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 104 \r
 105 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 106 #define portOFFSET_TO_PC                                                ( 6 )\r
 107 \r
 108 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 109 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " )\r
 110 \r
 111 /* Each task maintains its own interrupt status in the critical nesting\r
 112 variable.  Note this is not saved as part of the task context as context\r
 113 switches can only occur when uxCriticalNesting is zero. */\r
 114 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;\r
 115 \r
 116 /*\r
 117  * Setup the timer to generate the tick interrupts.\r
 118  */\r
 119 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 120 \r
 121 /*\r
 122  * Configure a number of standard MPU regions that are used by all tasks.\r
 123  */\r
 124 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 125 \r
 126 /* \r
 127  * Return the smallest MPU region size that a given number of bytes will fit\r
 128  * into.  The region size is returned as the value that should be programmed\r
 129  * into the region attribute register for that region.\r
 130  */\r
 131 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 132 \r
 133 /* \r
 134  * Checks to see if being called from the context of an unprivileged task, and\r
 135  * if so raises the privilege level and returns false - otherwise does nothing\r
 136  * other than return true.\r
 137  */\r
 138 static portBASE_TYPE prvRaisePrivilege( void ) __attribute__(( naked ));\r
 139 \r
 140 /*\r
 141  * Standard FreeRTOS exception handlers.\r
 142  */\r
 143 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 144 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 145 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 146 \r
 147 /*\r
 148  * Starts the scheduler by restoring the context of the first task to run.\r
 149  */\r
 150 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 151 \r
 152 /*\r
 153  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 154  * and a C wrapper for simplicity of coding and maintenance.\r
 155  */\r
 156 static void prvSVCHandler( unsigned long *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 157 \r
 158 /*-----------------------------------------------------------*/\r
 159 \r
 160 /*\r
 161  * See header file for description.\r
 162  */\r
 163 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters, portBASE_TYPE xRunPrivileged )\r
 164 {\r
 165         /* Simulate the stack frame as it would be created by a context switch\r
 166         interrupt. */\r
 167         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 168         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 169         pxTopOfStack--;\r
 170         *pxTopOfStack = ( portSTACK_TYPE ) pxCode;      /* PC */\r
 171         pxTopOfStack--;\r
 172         *pxTopOfStack = 0;      /* LR */\r
 173         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 174         *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;        /* R0 */\r
 175         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 176 \r
 177         if( xRunPrivileged == pdTRUE )\r
 178         {\r
 179                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 180         }\r
 181         else\r
 182         {\r
 183                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 184         }\r
 185 \r
 186         return pxTopOfStack;\r
 187 }\r
 188 /*-----------------------------------------------------------*/\r
 189 \r
 190 void vPortSVCHandler( void )\r
 191 {\r
 192         /* Assumes psp was in use. */\r
 193         __asm volatile \r
 194         (\r
 195                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 196                         "       tst lr, #4                                              \n"\r
 197                         "       ite eq                                                  \n"\r
 198                         "       mrseq r0, msp                                   \n"\r
 199                         "       mrsne r0, psp                                   \n"\r
 200                 #else\r
 201                         "       mrs r0, psp                                             \n"\r
 202                 #endif\r
 203                         "       b prvSVCHandler                                 \n"\r
 204                         :::"r0"\r
 205         );\r
 206 \r
 207         /* This will never get executed, but is required to prevent prvSVCHandler\r
 208         being removed by the optimiser. */\r
 209         prvSVCHandler( NULL );\r
 210 }\r
 211 /*-----------------------------------------------------------*/\r
 212 \r
 213 static void prvSVCHandler(      unsigned long *pulParam )\r
 214 {\r
 215 unsigned char ucSVCNumber;\r
 216 \r
 217         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 218         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 219         ucSVCNumber = ( ( unsigned char * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 220         switch( ucSVCNumber )\r
 221         {\r
 222                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 223                                                                                         prvRestoreContextOfFirstTask();\r
 224                                                                                         break;\r
 225 \r
 226                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 227                                                                                         break;\r
 228 \r
 229                 case portSVC_prvRaisePrivilege  :       __asm volatile \r
 230                                                                                         (\r
 231                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 232                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 233                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 234                                                                                                 :::"r1"\r
 235                                                                                         );\r
 236                                                                                         break;\r
 237 \r
 238                 default                                                 :       /* Unknown SVC call. */\r
 239                                                                                         break;\r
 240         }\r
 241 }\r
 242 /*-----------------------------------------------------------*/\r
 243 \r
 244 static void prvRestoreContextOfFirstTask( void )\r
 245 {\r
 246         __asm volatile \r
 247         (\r
 248                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 249                 "       ldr r0, [r0]                                    \n"\r
 250                 "       ldr r0, [r0]                                    \n"\r
 251                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 252                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 253                 "       ldr r1, [r3]                                    \n"\r
 254                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 255                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 256                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 257                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 258                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 259                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 260                 "       msr control, r3                                 \n"\r
 261                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 262                 "       mov r0, #0                                              \n"\r
 263                 "       msr     basepri, r0                                     \n"\r
 264                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 265                 "       bx r14                                                  \n"\r
 266                 "                                                                       \n"\r
 267                 "       .align 2                                                \n"\r
 268                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 269         );\r
 270 }\r
 271 /*-----------------------------------------------------------*/\r
 272 \r
 273 /*\r
 274  * See header file for description.\r
 275  */\r
 276 portBASE_TYPE xPortStartScheduler( void )\r
 277 {\r
 278         /* Make PendSV and SysTick the same priroity as the kernel. */\r
 279         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 280         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 281 \r
 282         /* Configure the regions in the MPU that are common to all tasks. */\r
 283         prvSetupMPU();\r
 284 \r
 285         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 286         here already. */\r
 287         prvSetupTimerInterrupt();\r
 288 \r
 289         /* Initialise the critical nesting count ready for the first task. */\r
 290         uxCriticalNesting = 0;\r
 291 \r
 292         /* Start the first task. */\r
 293         __asm volatile( "       svc %0                  \n"\r
 294                                         :: "i" (portSVC_START_SCHEDULER) );\r
 295 \r
 296         /* Should not get here! */\r
 297         return 0;\r
 298 }\r
 299 /*-----------------------------------------------------------*/\r
 300 \r
 301 void vPortEndScheduler( void )\r
 302 {\r
 303         /* It is unlikely that the CM3 port will require this function as there\r
 304         is nothing to return to.  */\r
 305 }\r
 306 /*-----------------------------------------------------------*/\r
 307 \r
 308 void vPortEnterCritical( void )\r
 309 {\r
 310 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 311 \r
 312         portDISABLE_INTERRUPTS();\r
 313         uxCriticalNesting++;\r
 314 \r
 315         portRESET_PRIVILEGE( xRunningPrivileged );\r
 316 }\r
 317 /*-----------------------------------------------------------*/\r
 318 \r
 319 void vPortExitCritical( void )\r
 320 {\r
 321 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 322 \r
 323         uxCriticalNesting--;\r
 324         if( uxCriticalNesting == 0 )\r
 325         {\r
 326                 portENABLE_INTERRUPTS();\r
 327         }\r
 328         portRESET_PRIVILEGE( xRunningPrivileged );\r
 329 }\r
 330 /*-----------------------------------------------------------*/\r
 331 \r
 332 void xPortPendSVHandler( void )\r
 333 {\r
 334         /* This is a naked function. */\r
 335 \r
 336         __asm volatile\r
 337         (\r
 338                 "       mrs r0, psp                                                     \n"\r
 339                 "                                                                               \n"\r
 340                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 341                 "       ldr     r2, [r3]                                                \n"\r
 342                 "                                                                               \n"\r
 343                 "       mrs r1, control                                         \n"\r
 344                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 345                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 346                 "                                                                               \n"\r
 347                 "       stmdb sp!, {r3, r14}                            \n"\r
 348                 "       mov r0, %0                                                      \n"\r
 349                 "       msr basepri, r0                                         \n"\r
 350                 "       bl vTaskSwitchContext                           \n"\r
 351                 "       mov r0, #0                                                      \n"\r
 352                 "       msr basepri, r0                                         \n"\r
 353                 "       ldmia sp!, {r3, r14}                            \n"\r
 354                 "                                                                               \n"     /* Restore the context. */\r
 355                 "       ldr r1, [r3]                                            \n"\r
 356                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 357                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 358                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 359                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 360                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 361                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 362                 "       msr control, r3                                         \n"\r
 363                 "                                                                               \n"\r
 364                 "       msr psp, r0                                                     \n"\r
 365                 "       bx r14                                                          \n"\r
 366                 "                                                                               \n"\r
 367                 "       .align 2                                                        \n"\r
 368                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 369                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 370         );\r
 371 }\r
 372 /*-----------------------------------------------------------*/\r
 373 \r
 374 void xPortSysTickHandler( void )\r
 375 {\r
 376 unsigned long ulDummy;\r
 377 \r
 378         /* If using preemption, also force a context switch. */\r
 379         #if configUSE_PREEMPTION == 1\r
 380                 *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 381         #endif\r
 382 \r
 383         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 384         {\r
 385                 vTaskIncrementTick();\r
 386         }\r
 387         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 388 }\r
 389 /*-----------------------------------------------------------*/\r
 390 \r
 391 /*\r
 392  * Setup the systick timer to generate the tick interrupts at the required\r
 393  * frequency.\r
 394  */\r
 395 static void prvSetupTimerInterrupt( void )\r
 396 {\r
 397         /* Configure SysTick to interrupt at the requested rate. */\r
 398         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 399         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 400 }\r
 401 /*-----------------------------------------------------------*/\r
 402 \r
 403 static void prvSetupMPU( void )\r
 404 {\r
 405 extern unsigned long __privileged_functions_end__[];\r
 406 extern unsigned long __FLASH_segment_start__[];\r
 407 extern unsigned long __FLASH_segment_end__[];\r
 408 extern unsigned long __privileged_data_start__[];\r
 409 extern unsigned long __privileged_data_end__[];\r
 410 \r
 411         /* Check the expected MPU is present. */\r
 412         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 413         {\r
 414                 /* First setup the entire flash for unprivileged read only access. */\r
 415         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 416                                                                                 ( portMPU_REGION_VALID ) |\r
 417                                                                                 ( portUNPRIVILEGED_FLASH_REGION ); \r
 418 \r
 419                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 420                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 421                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __FLASH_segment_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) |\r
 422                                                                                 ( portMPU_REGION_ENABLE );\r
 423 \r
 424                 /* Setup the first 16K for privileged only access (even though less \r
 425                 than 10K is actually being used).  This is where the kernel code is\r
 426                 placed. */\r
 427         *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __FLASH_segment_start__ ) | /* Base address. */\r
 428                                                                                 ( portMPU_REGION_VALID ) |\r
 429                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 430 \r
 431                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 432                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) | \r
 433                                                                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_functions_end__ - ( unsigned long ) __FLASH_segment_start__ ) ) | \r
 434                                                                                 ( portMPU_REGION_ENABLE );\r
 435 \r
 436                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 437                 is placed. */\r
 438                 *portMPU_REGION_BASE_ADDRESS =  ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 439                                                                                 ( portMPU_REGION_VALID ) |\r
 440                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 441 \r
 442                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 443                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 444                                                                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 445                                                                                 ( portMPU_REGION_ENABLE );\r
 446 \r
 447                 /* By default allow everything to access the general peripherals.  The\r
 448                 system peripherals and registers are protected. */\r
 449                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 450                                                                                 ( portMPU_REGION_VALID ) |\r
 451                                                                                 ( portGENERAL_PERIPHERALS_REGION ); \r
 452 \r
 453                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 454                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 455                                                                                 ( portMPU_REGION_ENABLE );\r
 456 \r
 457                 /* Enable the memory fault exception. */\r
 458                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 459 \r
 460                 /* Enable the MPU with the background region configured. */\r
 461                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 462         }\r
 463 }\r
 464 /*-----------------------------------------------------------*/\r
 465 \r
 466 static unsigned long prvGetMPURegionSizeSetting( unsigned long ulActualSizeInBytes )\r
 467 {\r
 468 unsigned long ulRegionSize, ulReturnValue = 4;\r
 469 \r
 470         /* 32 is the smallest region size, 31 is the largest valid value for\r
 471         ulReturnValue. */\r
 472         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 473         {\r
 474                 if( ulActualSizeInBytes <= ulRegionSize )\r
 475                 {\r
 476                         break;\r
 477                 }\r
 478                 else\r
 479                 {\r
 480                         ulReturnValue++;\r
 481                 }\r
 482         }\r
 483 \r
 484         /* Shift the code by one before returning so it can be written directly\r
 485         into the the correct bit position of the attribute register. */\r
 486         return ( ulReturnValue << 1UL );\r
 487 }\r
 488 /*-----------------------------------------------------------*/\r
 489 \r
 490 static portBASE_TYPE prvRaisePrivilege( void )\r
 491 {\r
 492         __asm volatile\r
 493         ( \r
 494                 "       mrs r0, control                                         \n"\r
 495                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 496                 "       itte ne                                                         \n"\r
 497                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 498                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 499                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 500                 "       bx lr                                                           \n"\r
 501                 :: "i" (portSVC_prvRaisePrivilege) : "r0" \r
 502         );\r
 503 \r
 504         return 0;\r
 505 }\r
 506 /*-----------------------------------------------------------*/\r
 507 \r
 508 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, portSTACK_TYPE *pxBottomOfStack, unsigned short usStackDepth )\r
 509 {\r
 510 extern unsigned long __SRAM_segment_start__[];\r
 511 extern unsigned long __SRAM_segment_end__[];\r
 512 extern unsigned long __privileged_data_start__[];\r
 513 extern unsigned long __privileged_data_end__[];\r
 514 long lIndex;\r
 515 unsigned long ul;\r
 516 \r
 517         if( xRegions == NULL )\r
 518         {\r
 519                 /* No MPU regions are specified so allow access to all RAM. */\r
 520         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =        \r
 521                                 ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base address. */\r
 522                                 ( portMPU_REGION_VALID ) |\r
 523                                 ( portSTACK_REGION );\r
 524 \r
 525                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =  \r
 526                                 ( portMPU_REGION_READ_WRITE ) | \r
 527                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 528                                 ( prvGetMPURegionSizeSetting( ( unsigned long ) __SRAM_segment_end__ - ( unsigned long ) __SRAM_segment_start__ ) ) |\r
 529                                 ( portMPU_REGION_ENABLE );\r
 530 \r
 531                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 532                 just removed the privileged only parameters. */\r
 533                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =        \r
 534                                 ( ( unsigned long ) __privileged_data_start__ ) | /* Base address. */\r
 535                                 ( portMPU_REGION_VALID ) |\r
 536                                 ( portSTACK_REGION + 1 );\r
 537 \r
 538                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =          \r
 539                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 540                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 541                                 prvGetMPURegionSizeSetting( ( unsigned long ) __privileged_data_end__ - ( unsigned long ) __privileged_data_start__ ) |\r
 542                                 ( portMPU_REGION_ENABLE );\r
 543                                 \r
 544                 /* Invalidate all other regions. */\r
 545                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 546                 { \r
 547                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;     \r
 548                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 549                 }\r
 550         }\r
 551         else\r
 552         {\r
 553                 /* This function is called automatically when the task is created - in\r
 554                 which case the stack region parameters will be valid.  At all other\r
 555                 times the stack parameters will not be valid and it is assumed that the\r
 556                 stack region has already been configured. */\r
 557                 if( usStackDepth > 0 )\r
 558                 {\r
 559                         /* Define the region that allows access to the stack. */\r
 560                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =        \r
 561                                         ( ( unsigned long ) pxBottomOfStack ) | \r
 562                                         ( portMPU_REGION_VALID ) |\r
 563                                         ( portSTACK_REGION ); /* Region number. */\r
 564 \r
 565                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =  \r
 566                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 567                                         ( prvGetMPURegionSizeSetting( ( unsigned long ) usStackDepth * ( unsigned long ) sizeof( portSTACK_TYPE ) ) ) |\r
 568                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 569                                         ( portMPU_REGION_ENABLE );\r
 570                 }\r
 571 \r
 572                 lIndex = 0;\r
 573 \r
 574                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 575                 {\r
 576                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 577                         {\r
 578                                 /* Translate the generic region definition contained in \r
 579                                 xRegions into the CM3 specific MPU settings that are then \r
 580                                 stored in xMPUSettings. */\r
 581                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =       \r
 582                                                 ( ( unsigned long ) xRegions[ lIndex ].pvBaseAddress ) | \r
 583                                                 ( portMPU_REGION_VALID ) |\r
 584                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 585 \r
 586                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = \r
 587                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) | \r
 588                                                 ( xRegions[ lIndex ].ulParameters ) | \r
 589                                                 ( portMPU_REGION_ENABLE ); \r
 590                         }\r
 591                         else\r
 592                         {\r
 593                                 /* Invalidate the region. */\r
 594                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;     \r
 595                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 596                         }\r
 597 \r
 598                         lIndex++;\r
 599                 }\r
 600         }\r
 601 }\r
 602 /*-----------------------------------------------------------*/\r
 603 \r
 604 signed portBASE_TYPE MPU_xTaskGenericCreate( pdTASK_CODE pvTaskCode, const signed char * const pcName, unsigned short usStackDepth, void *pvParameters, unsigned portBASE_TYPE uxPriority, xTaskHandle *pxCreatedTask, portSTACK_TYPE *puxStackBuffer, const xMemoryRegion * const xRegions )\r
 605 {\r
 606 signed portBASE_TYPE xReturn;\r
 607 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 608 \r
 609         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 610         portRESET_PRIVILEGE( xRunningPrivileged );\r
 611         return xReturn;\r
 612 }\r
 613 /*-----------------------------------------------------------*/\r
 614 \r
 615 void MPU_vTaskAllocateMPURegions( xTaskHandle xTask, const xMemoryRegion * const xRegions )\r
 616 {\r
 617 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 618 \r
 619         vTaskAllocateMPURegions( xTask, xRegions );\r
 620         portRESET_PRIVILEGE( xRunningPrivileged );\r
 621 }\r
 622 /*-----------------------------------------------------------*/\r
 623 \r
 624 #if ( INCLUDE_vTaskDelete == 1 )\r
 625         void MPU_vTaskDelete( xTaskHandle pxTaskToDelete )\r
 626         {\r
 627     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 628 \r
 629                 vTaskDelete( pxTaskToDelete );\r
 630         portRESET_PRIVILEGE( xRunningPrivileged );\r
 631         }\r
 632 #endif\r
 633 /*-----------------------------------------------------------*/\r
 634 \r
 635 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 636         void MPU_vTaskDelayUntil( portTickType * const pxPreviousWakeTime, portTickType xTimeIncrement )\r
 637         {\r
 638     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 639 \r
 640                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 641         portRESET_PRIVILEGE( xRunningPrivileged );\r
 642         }\r
 643 #endif\r
 644 /*-----------------------------------------------------------*/\r
 645 \r
 646 #if ( INCLUDE_vTaskDelay == 1 )\r
 647         void MPU_vTaskDelay( portTickType xTicksToDelay )\r
 648         {\r
 649     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 650 \r
 651                 vTaskDelay( xTicksToDelay );\r
 652         portRESET_PRIVILEGE( xRunningPrivileged );\r
 653         }\r
 654 #endif\r
 655 /*-----------------------------------------------------------*/\r
 656 \r
 657 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 658         unsigned portBASE_TYPE MPU_uxTaskPriorityGet( xTaskHandle pxTask )\r
 659         {\r
 660         unsigned portBASE_TYPE uxReturn;\r
 661     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 662 \r
 663                 uxReturn = uxTaskPriorityGet( pxTask );\r
 664         portRESET_PRIVILEGE( xRunningPrivileged );\r
 665                 return uxReturn;\r
 666         }\r
 667 #endif\r
 668 /*-----------------------------------------------------------*/\r
 669 \r
 670 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 671         void MPU_vTaskPrioritySet( xTaskHandle pxTask, unsigned portBASE_TYPE uxNewPriority )\r
 672         {\r
 673     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 674 \r
 675                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 676         portRESET_PRIVILEGE( xRunningPrivileged );\r
 677         }\r
 678 #endif\r
 679 /*-----------------------------------------------------------*/\r
 680 \r
 681 #if ( INCLUDE_vTaskSuspend == 1 )\r
 682         void MPU_vTaskSuspend( xTaskHandle pxTaskToSuspend )\r
 683         {\r
 684     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 685 \r
 686                 vTaskSuspend( pxTaskToSuspend );\r
 687         portRESET_PRIVILEGE( xRunningPrivileged );\r
 688         }\r
 689 #endif\r
 690 /*-----------------------------------------------------------*/\r
 691 \r
 692 #if ( INCLUDE_vTaskSuspend == 1 )\r
 693         signed portBASE_TYPE MPU_xTaskIsTaskSuspended( xTaskHandle xTask )\r
 694         {\r
 695         signed portBASE_TYPE xReturn;\r
 696     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 697 \r
 698                 xReturn = xTaskIsTaskSuspended( xTask );\r
 699         portRESET_PRIVILEGE( xRunningPrivileged );\r
 700                 return xReturn;\r
 701         }\r
 702 #endif\r
 703 /*-----------------------------------------------------------*/\r
 704 \r
 705 #if ( INCLUDE_vTaskSuspend == 1 )\r
 706         void MPU_vTaskResume( xTaskHandle pxTaskToResume )\r
 707         {\r
 708     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 709 \r
 710                 vTaskResume( pxTaskToResume );\r
 711         portRESET_PRIVILEGE( xRunningPrivileged );\r
 712         }\r
 713 #endif\r
 714 /*-----------------------------------------------------------*/\r
 715 \r
 716 void MPU_vTaskSuspendAll( void )\r
 717 {\r
 718 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 719 \r
 720         vTaskSuspendAll();\r
 721     portRESET_PRIVILEGE( xRunningPrivileged );\r
 722 }\r
 723 /*-----------------------------------------------------------*/\r
 724 \r
 725 signed portBASE_TYPE MPU_xTaskResumeAll( void )\r
 726 {\r
 727 signed portBASE_TYPE xReturn;\r
 728 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 729 \r
 730         xReturn = xTaskResumeAll();\r
 731     portRESET_PRIVILEGE( xRunningPrivileged );\r
 732     return xReturn;\r
 733 }\r
 734 /*-----------------------------------------------------------*/\r
 735 \r
 736 portTickType MPU_xTaskGetTickCount( void )\r
 737 {\r
 738 portTickType xReturn;\r
 739 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 740 \r
 741         xReturn = xTaskGetTickCount();\r
 742     portRESET_PRIVILEGE( xRunningPrivileged );\r
 743         return xReturn;\r
 744 }\r
 745 /*-----------------------------------------------------------*/\r
 746 \r
 747 unsigned portBASE_TYPE MPU_uxTaskGetNumberOfTasks( void )\r
 748 {\r
 749 unsigned portBASE_TYPE uxReturn;\r
 750 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 751 \r
 752         uxReturn = uxTaskGetNumberOfTasks();\r
 753     portRESET_PRIVILEGE( xRunningPrivileged );\r
 754         return uxReturn;\r
 755 }\r
 756 /*-----------------------------------------------------------*/\r
 757 \r
 758 #if ( configUSE_TRACE_FACILITY == 1 )\r
 759         void MPU_vTaskList( signed char *pcWriteBuffer )\r
 760         {\r
 761         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 762         \r
 763                 vTaskList( pcWriteBuffer );\r
 764                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 765         }\r
 766 #endif\r
 767 /*-----------------------------------------------------------*/\r
 768 \r
 769 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 770         void MPU_vTaskGetRunTimeStats( signed char *pcWriteBuffer )\r
 771         {\r
 772     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 773 \r
 774                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 775         portRESET_PRIVILEGE( xRunningPrivileged );\r
 776         }\r
 777 #endif\r
 778 /*-----------------------------------------------------------*/\r
 779 \r
 780 #if ( configUSE_TRACE_FACILITY == 1 )\r
 781         void MPU_vTaskStartTrace( signed char * pcBuffer, unsigned long ulBufferSize )\r
 782         {\r
 783     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 784 \r
 785                 vTaskStartTrace( pcBuffer, ulBufferSize );\r
 786         portRESET_PRIVILEGE( xRunningPrivileged );\r
 787         }\r
 788 #endif\r
 789 /*-----------------------------------------------------------*/\r
 790 \r
 791 #if ( configUSE_TRACE_FACILITY == 1 )\r
 792         unsigned long MPU_ulTaskEndTrace( void )\r
 793         {\r
 794         unsigned long ulReturn;\r
 795     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 796 \r
 797                 ulReturn = ulTaskEndTrace();\r
 798         portRESET_PRIVILEGE( xRunningPrivileged );\r
 799                 return ulReturn;\r
 800         }\r
 801 #endif\r
 802 /*-----------------------------------------------------------*/\r
 803 \r
 804 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 805         void MPU_vTaskSetApplicationTaskTag( xTaskHandle xTask, pdTASK_HOOK_CODE pxTagValue )\r
 806         {\r
 807     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 808 \r
 809                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 810         portRESET_PRIVILEGE( xRunningPrivileged );\r
 811         }\r
 812 #endif\r
 813 /*-----------------------------------------------------------*/\r
 814 \r
 815 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 816         pdTASK_HOOK_CODE MPU_xTaskGetApplicationTaskTag( xTaskHandle xTask )\r
 817         {\r
 818         pdTASK_HOOK_CODE xReturn;\r
 819     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 820 \r
 821                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 822         portRESET_PRIVILEGE( xRunningPrivileged );\r
 823                 return xReturn;\r
 824         }\r
 825 #endif\r
 826 /*-----------------------------------------------------------*/\r
 827 \r
 828 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 829         portBASE_TYPE MPU_xTaskCallApplicationTaskHook( xTaskHandle xTask, void *pvParameter )\r
 830         {\r
 831         portBASE_TYPE xReturn;\r
 832     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 833 \r
 834                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 835         portRESET_PRIVILEGE( xRunningPrivileged );\r
 836                 return xReturn;\r
 837         }\r
 838 #endif\r
 839 /*-----------------------------------------------------------*/\r
 840 \r
 841 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 842         unsigned portBASE_TYPE MPU_uxTaskGetStackHighWaterMark( xTaskHandle xTask )\r
 843         {\r
 844         unsigned portBASE_TYPE uxReturn;\r
 845     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 846 \r
 847                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 848         portRESET_PRIVILEGE( xRunningPrivileged );\r
 849                 return uxReturn;\r
 850         }\r
 851 #endif\r
 852 /*-----------------------------------------------------------*/\r
 853 \r
 854 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 855         xTaskHandle MPU_xTaskGetCurrentTaskHandle( void )\r
 856         {\r
 857         xTaskHandle xReturn;\r
 858     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 859 \r
 860                 xReturn = xTaskGetCurrentTaskHandle();\r
 861         portRESET_PRIVILEGE( xRunningPrivileged );\r
 862                 return xReturn;\r
 863         }\r
 864 #endif\r
 865 /*-----------------------------------------------------------*/\r
 866 \r
 867 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 868         portBASE_TYPE MPU_xTaskGetSchedulerState( void )\r
 869         {\r
 870         portBASE_TYPE xReturn;\r
 871     portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 872 \r
 873                 xReturn = xTaskGetSchedulerState();\r
 874         portRESET_PRIVILEGE( xRunningPrivileged );\r
 875                 return xReturn;\r
 876         }\r
 877 #endif\r
 878 /*-----------------------------------------------------------*/\r
 879 \r
 880 xQueueHandle MPU_xQueueCreate( unsigned portBASE_TYPE uxQueueLength, unsigned portBASE_TYPE uxItemSize )\r
 881 {\r
 882 xQueueHandle xReturn;\r
 883 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 884 \r
 885         xReturn = xQueueCreate( uxQueueLength, uxItemSize );\r
 886         portRESET_PRIVILEGE( xRunningPrivileged );\r
 887         return xReturn;\r
 888 }\r
 889 /*-----------------------------------------------------------*/\r
 890 \r
 891 signed portBASE_TYPE MPU_xQueueGenericSend( xQueueHandle xQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
 892 {\r
 893 signed portBASE_TYPE xReturn;\r
 894 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 895 \r
 896         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 897         portRESET_PRIVILEGE( xRunningPrivileged );\r
 898         return xReturn;\r
 899 }\r
 900 /*-----------------------------------------------------------*/\r
 901 \r
 902 unsigned portBASE_TYPE MPU_uxQueueMessagesWaiting( const xQueueHandle pxQueue )\r
 903 {\r
 904 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 905 unsigned portBASE_TYPE uxReturn;\r
 906 \r
 907         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
 908         portRESET_PRIVILEGE( xRunningPrivileged );\r
 909         return uxReturn;\r
 910 }\r
 911 /*-----------------------------------------------------------*/\r
 912 \r
 913 signed portBASE_TYPE MPU_xQueueGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
 914 {\r
 915 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 916 signed portBASE_TYPE xReturn;\r
 917 \r
 918         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
 919         portRESET_PRIVILEGE( xRunningPrivileged );\r
 920         return xReturn;\r
 921 }\r
 922 /*-----------------------------------------------------------*/\r
 923 \r
 924 #if ( configUSE_MUTEXES == 1 )\r
 925         xQueueHandle MPU_xQueueCreateMutex( void )\r
 926         {\r
 927     xQueueHandle xReturn;\r
 928         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 929 \r
 930                 xReturn = xQueueCreateMutex();\r
 931                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 932                 return xReturn;\r
 933         }\r
 934 #endif\r
 935 /*-----------------------------------------------------------*/\r
 936 \r
 937 #if configUSE_COUNTING_SEMAPHORES == 1\r
 938         xQueueHandle MPU_xQueueCreateCountingSemaphore( unsigned portBASE_TYPE uxCountValue, unsigned portBASE_TYPE uxInitialCount )\r
 939         {\r
 940     xQueueHandle xReturn;\r
 941         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 942 \r
 943                 xReturn = xQueueHandle xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
 944                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 945                 return xReturn;\r
 946         }\r
 947 #endif\r
 948 /*-----------------------------------------------------------*/\r
 949 \r
 950 #if ( configUSE_MUTEXES == 1 )\r
 951         portBASE_TYPE MPU_xQueueTakeMutexRecursive( xQueueHandle xMutex, portTickType xBlockTime )\r
 952         {\r
 953         portBASE_TYPE xReturn;\r
 954         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 955 \r
 956                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
 957                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 958                 return xReturn;\r
 959         }\r
 960 #endif\r
 961 /*-----------------------------------------------------------*/\r
 962 \r
 963 #if ( configUSE_MUTEXES == 1 )\r
 964         portBASE_TYPE MPU_xQueueGiveMutexRecursive( xQueueHandle xMutex )\r
 965         {\r
 966         portBASE_TYPE xReturn;\r
 967         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 968 \r
 969                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
 970                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 971                 return xReturn;\r
 972         }\r
 973 #endif\r
 974 /*-----------------------------------------------------------*/\r
 975 \r
 976 #if configUSE_ALTERNATIVE_API == 1\r
 977         signed portBASE_TYPE MPU_xQueueAltGenericSend( xQueueHandle pxQueue, const void * const pvItemToQueue, portTickType xTicksToWait, portBASE_TYPE xCopyPosition )\r
 978         {\r
 979         signed portBASE_TYPE xReturn;\r
 980         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 981 \r
 982                 xReturn =       signed portBASE_TYPE xQueueAltGenericSend( pxQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 983                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 984                 return xReturn;\r
 985         }\r
 986 #endif\r
 987 /*-----------------------------------------------------------*/\r
 988 \r
 989 #if configUSE_ALTERNATIVE_API == 1\r
 990         signed portBASE_TYPE MPU_xQueueAltGenericReceive( xQueueHandle pxQueue, void * const pvBuffer, portTickType xTicksToWait, portBASE_TYPE xJustPeeking )\r
 991         {\r
 992     signed portBASE_TYPE xReturn;\r
 993         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
 994 \r
 995                 xReturn = xQueueAltGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
 996                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 997                 return xReturn;\r
 998         }\r
 999 #endif\r
1000 /*-----------------------------------------------------------*/\r
1001 \r
1002 #if configQUEUE_REGISTRY_SIZE > 0\r
1003         void MPU_vQueueAddToRegistry( xQueueHandle xQueue, signed char *pcName )\r
1004         {\r
1005         portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1006 \r
1007                 vQueueAddToRegistry( xQueue, pcName );\r
1008 \r
1009                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1010         }\r
1011 #endif\r
1012 /*-----------------------------------------------------------*/\r
1013 \r
1014 void *MPU_pvPortMalloc( size_t xSize )\r
1015 {\r
1016 void *pvReturn;\r
1017 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1018 \r
1019         pvReturn = pvPortMalloc( xSize );\r
1020 \r
1021         portRESET_PRIVILEGE( xRunningPrivileged );\r
1022 \r
1023         return pvReturn;\r
1024 }\r
1025 /*-----------------------------------------------------------*/\r
1026 \r
1027 void MPU_vPortFree( void *pv )\r
1028 {\r
1029 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1030 \r
1031         vPortFree( pv );\r
1032 \r
1033         portRESET_PRIVILEGE( xRunningPrivileged );\r
1034 }\r
1035 /*-----------------------------------------------------------*/\r
1036 \r
1037 void MPU_vPortInitialiseBlocks( void )\r
1038 {\r
1039 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1040 \r
1041         vPortInitialiseBlocks();\r
1042 \r
1043         portRESET_PRIVILEGE( xRunningPrivileged );\r
1044 }\r
1045 /*-----------------------------------------------------------*/\r
1046 \r
1047 size_t MPU_xPortGetFreeHeapSize( void )\r
1048 {\r
1049 size_t xReturn;\r
1050 portBASE_TYPE xRunningPrivileged = prvRaisePrivilege();\r
1051 \r
1052         xReturn = xPortGetFreeHeapSize();\r
1053 \r
1054         portRESET_PRIVILEGE( xRunningPrivileged );\r
1055         \r
1056         return xReturn;\r
1057 }\r
1058 \r