1 /*This file has been prepared for Doxygen automatic documentation generation.*/
\r
2 /*! \file *********************************************************************
\r
4 * \brief FreeRTOS port source for AVR32 UC3.
\r
6 * - Compiler: GNU GCC for AVR32
\r
7 * - Supported devices: All AVR32 devices can be used.
\r
10 * \author Atmel Corporation: http://www.atmel.com \n
\r
11 * Support and FAQ: http://support.atmel.no/
\r
13 *****************************************************************************/
\r
16 FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.
\r
18 ***************************************************************************
\r
22 * + New to FreeRTOS, *
\r
23 * + Wanting to learn FreeRTOS or multitasking in general quickly *
\r
24 * + Looking for basic training, *
\r
25 * + Wanting to improve your FreeRTOS skills and productivity *
\r
27 * then take a look at the FreeRTOS eBook *
\r
29 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
\r
30 * http://www.FreeRTOS.org/Documentation *
\r
32 * A pdf reference manual is also available. Both are usually delivered *
\r
33 * to your inbox within 20 minutes to two hours when purchased between 8am *
\r
34 * and 8pm GMT (although please allow up to 24 hours in case of *
\r
35 * exceptional circumstances). Thank you for your support! *
\r
37 ***************************************************************************
\r
39 This file is part of the FreeRTOS distribution.
\r
41 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
42 the terms of the GNU General Public License (version 2) as published by the
\r
43 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
44 ***NOTE*** The exception to the GPL is included to allow you to distribute
\r
45 a combined work that includes FreeRTOS without being obliged to provide the
\r
46 source code for proprietary components outside of the FreeRTOS kernel.
\r
47 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
\r
48 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
49 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
50 more details. You should have received a copy of the GNU General Public
\r
51 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
52 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
53 by writing to Richard Barry, contact details for whom are available on the
\r
58 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
61 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
64 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
65 licensing and training services.
\r
69 /* Standard includes. */
\r
70 #include <sys/cpu.h>
\r
71 #include <sys/usart.h>
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
78 /* AVR32 UC3 includes. */
\r
79 #include <avr32/io.h>
\r
81 #if( configTICK_USE_TC==1 )
\r
86 /* Constants required to setup the task context. */
\r
87 #define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
\r
88 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
\r
90 /* Each task maintains its own critical nesting variable. */
\r
91 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
92 volatile unsigned long ulCriticalNesting = 9999UL;
\r
94 #if( configTICK_USE_TC==0 )
\r
95 static void prvScheduleNextTick( void );
\r
97 static void prvClearTcInt( void );
\r
100 /* Setup the timer to generate the tick interrupts. */
\r
101 static void prvSetupTimerInterrupt( void );
\r
103 /*-----------------------------------------------------------*/
\r
106 * Low-level initialization routine called during startup, before the main
\r
108 * This version comes in replacement to the default one provided by Newlib.
\r
109 * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
\r
110 * vectors are not compatible with the SCALL management in the current FreeRTOS
\r
111 * port. More low-level initializations are besides added here.
\r
113 void _init_startup(void)
\r
115 /* Import the Exception Vector Base Address. */
\r
118 #if configHEAP_INIT
\r
119 extern void __heap_start__;
\r
120 extern void __heap_end__;
\r
121 portBASE_TYPE *pxMem;
\r
124 /* Load the Exception Vector Base Address in the corresponding system register. */
\r
125 Set_system_register( AVR32_EVBA, ( int ) &_evba );
\r
127 /* Enable exceptions. */
\r
128 ENABLE_ALL_EXCEPTIONS();
\r
130 /* Initialize interrupt handling. */
\r
131 INTC_init_interrupts();
\r
133 #if configHEAP_INIT
\r
135 /* Initialize the heap used by malloc. */
\r
136 for( pxMem = &__heap_start__; pxMem < ( portBASE_TYPE * )&__heap_end__; )
\r
138 *pxMem++ = 0xA5A5A5A5;
\r
143 /* Give the used CPU clock frequency to Newlib, so it can work properly. */
\r
144 set_cpu_hz( configCPU_CLOCK_HZ );
\r
146 /* Code section present if and only if the debug trace is activated. */
\r
149 static const gpio_map_t DBG_USART_GPIO_MAP =
\r
151 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
\r
152 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
\r
155 /* Initialize the USART used for the debug trace with the configured parameters. */
\r
156 set_usart_base( ( void * ) configDBG_USART );
\r
157 gpio_enable_module( DBG_USART_GPIO_MAP,
\r
158 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
\r
159 usart_init( configDBG_USART_BAUDRATE );
\r
163 /*-----------------------------------------------------------*/
\r
166 * malloc, realloc and free are meant to be called through respectively
\r
167 * pvPortMalloc, pvPortRealloc and vPortFree.
\r
168 * The latter functions call the former ones from within sections where tasks
\r
169 * are suspended, so the latter functions are task-safe. __malloc_lock and
\r
170 * __malloc_unlock use the same mechanism to also keep the former functions
\r
171 * task-safe as they may be called directly from Newlib's functions.
\r
172 * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
\r
173 * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
\r
174 * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
\r
175 * interrupts during memory allocation management as this may be a very time-
\r
176 * consuming process.
\r
180 * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
\r
181 * safe section as memory allocation management uses global data.
\r
182 * See the aforementioned details.
\r
184 void __malloc_lock(struct _reent *ptr)
\r
190 * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
\r
191 * a safe section as memory allocation management uses global data.
\r
192 * See the aforementioned details.
\r
194 void __malloc_unlock(struct _reent *ptr)
\r
198 /*-----------------------------------------------------------*/
\r
200 /* Added as there is no such function in FreeRTOS. */
\r
201 void *pvPortRealloc( void *pv, size_t xWantedSize )
\r
207 pvReturn = realloc( pv, xWantedSize );
\r
213 /*-----------------------------------------------------------*/
\r
215 /* The cooperative scheduler requires a normal IRQ service routine to
\r
216 simply increment the system tick. */
\r
217 /* The preemptive scheduler is defined as "naked" as the full context is saved
\r
218 on entry as part of the context switch. */
\r
219 __attribute__((__naked__)) static void vTick( void )
\r
221 /* Save the context of the interrupted task. */
\r
222 portSAVE_CONTEXT_OS_INT();
\r
224 #if( configTICK_USE_TC==1 )
\r
225 /* Clear the interrupt flag. */
\r
228 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
\r
229 clock cycles from now. */
\r
230 prvScheduleNextTick();
\r
233 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
\r
234 calls in a critical section . */
\r
235 portENTER_CRITICAL();
\r
236 vTaskIncrementTick();
\r
237 portEXIT_CRITICAL();
\r
239 /* Restore the context of the "elected task". */
\r
240 portRESTORE_CONTEXT_OS_INT();
\r
242 /*-----------------------------------------------------------*/
\r
244 __attribute__((__naked__)) void SCALLYield( void )
\r
246 /* Save the context of the interrupted task. */
\r
247 portSAVE_CONTEXT_SCALL();
\r
248 vTaskSwitchContext();
\r
249 portRESTORE_CONTEXT_SCALL();
\r
251 /*-----------------------------------------------------------*/
\r
253 /* The code generated by the GCC compiler uses the stack in different ways at
\r
254 different optimisation levels. The interrupt flags can therefore not always
\r
255 be saved to the stack. Instead the critical section nesting level is stored
\r
256 in a variable, which is then saved as part of the stack context. */
\r
257 __attribute__((__noinline__)) void vPortEnterCritical( void )
\r
259 /* Disable interrupts */
\r
260 portDISABLE_INTERRUPTS();
\r
262 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
263 directly. Increment ulCriticalNesting to keep a count of how many times
\r
264 portENTER_CRITICAL() has been called. */
\r
265 ulCriticalNesting++;
\r
267 /*-----------------------------------------------------------*/
\r
269 __attribute__((__noinline__)) void vPortExitCritical( void )
\r
271 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
\r
273 ulCriticalNesting--;
\r
274 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
276 /* Enable all interrupt/exception. */
\r
277 portENABLE_INTERRUPTS();
\r
281 /*-----------------------------------------------------------*/
\r
284 * Initialise the stack of a task to look exactly as if a call to
\r
285 * portSAVE_CONTEXT had been called.
\r
287 * See header file for description.
\r
289 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
291 /* Setup the initial stack of the task. The stack is set exactly as
\r
292 expected by the portRESTORE_CONTEXT() macro. */
\r
294 /* When the task starts, it will expect to find the function parameter in R12. */
\r
296 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
297 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
298 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
\r
299 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
\r
300 *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
\r
301 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
\r
302 *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
\r
303 *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
\r
304 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
\r
305 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
306 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
307 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
308 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
309 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
310 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
311 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
312 *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
\r
314 return pxTopOfStack;
\r
316 /*-----------------------------------------------------------*/
\r
318 portBASE_TYPE xPortStartScheduler( void )
\r
320 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
322 prvSetupTimerInterrupt();
\r
324 /* Start the first task. */
\r
325 portRESTORE_CONTEXT();
\r
327 /* Should not get here! */
\r
330 /*-----------------------------------------------------------*/
\r
332 void vPortEndScheduler( void )
\r
334 /* It is unlikely that the AVR32 port will require this function as there
\r
335 is nothing to return to. */
\r
337 /*-----------------------------------------------------------*/
\r
339 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
\r
340 clock cycles from now. */
\r
341 #if( configTICK_USE_TC==0 )
\r
342 static void prvScheduleFirstTick(void)
\r
344 unsigned long lCycles;
\r
346 lCycles = Get_system_register(AVR32_COUNT);
\r
347 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
\r
348 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
\r
349 // generation feature does not get disabled.
\r
354 Set_system_register(AVR32_COMPARE, lCycles);
\r
357 __attribute__((__noinline__)) static void prvScheduleNextTick(void)
\r
359 unsigned long lCycles, lCount;
\r
361 lCycles = Get_system_register(AVR32_COMPARE);
\r
362 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
\r
363 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
\r
364 // generation feature does not get disabled.
\r
369 lCount = Get_system_register(AVR32_COUNT);
\r
370 if( lCycles < lCount )
\r
371 { // We missed a tick, recover for the next.
\r
372 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
\r
374 Set_system_register(AVR32_COMPARE, lCycles);
\r
377 __attribute__((__noinline__)) static void prvClearTcInt(void)
\r
379 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
\r
382 /*-----------------------------------------------------------*/
\r
384 /* Setup the timer to generate the tick interrupts. */
\r
385 static void prvSetupTimerInterrupt(void)
\r
387 #if( configTICK_USE_TC==1 )
\r
389 volatile avr32_tc_t *tc = &AVR32_TC;
\r
391 // Options for waveform genration.
\r
392 tc_waveform_opt_t waveform_opt =
\r
394 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
\r
396 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
\r
397 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
\r
398 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
\r
399 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
\r
401 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
\r
402 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
\r
403 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
\r
404 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
\r
406 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
\r
407 .enetrg = FALSE, /* External event trigger enable. */
\r
408 .eevt = 0, /* External event selection. */
\r
409 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
\r
410 .cpcdis = FALSE, /* Counter disable when RC compare. */
\r
411 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
\r
413 .burst = FALSE, /* Burst signal selection. */
\r
414 .clki = FALSE, /* Clock inversion. */
\r
415 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
\r
418 tc_interrupt_t tc_interrupt =
\r
432 /* Disable all interrupt/exception. */
\r
433 portDISABLE_INTERRUPTS();
\r
435 /* Register the compare interrupt handler to the interrupt controller and
\r
436 enable the compare interrupt. */
\r
438 #if( configTICK_USE_TC==1 )
\r
440 INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
\r
442 /* Initialize the timer/counter. */
\r
443 tc_init_waveform(tc, &waveform_opt);
\r
445 /* Set the compare triggers.
\r
446 Remember TC counter is 16-bits, so counting second is not possible!
\r
447 That's why we configure it to count ms. */
\r
448 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
\r
450 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
\r
452 /* Start the timer/counter. */
\r
453 tc_start(tc, configTICK_TC_CHANNEL);
\r
457 INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
\r
458 prvScheduleFirstTick();
\r